JP3611041B2 - Semiconductor arithmetic circuit - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor circuit, and particularly has a function of comparing stored signal information and input signal information together with a function of storing signal information to check whether they match within a predetermined range or not. A retained high-performance semiconductor circuit is provided.
[0002]
[Prior art]
Conventionally, a huge amount of analog image data taken in by an image sensor and stored in a memory is transferred to a digital computer outside the memory, where processing such as matching is performed.
[0003]
In this method, the information processing operation is performed only by an arithmetic processing device outside the memory, so the load on the arithmetic processing unit increases as the number of data increases with the number of pixels, and signal processing in real time is impossible. is there.
[0004]
Therefore, there is a need for a high-performance memory that reduces the burden on the arithmetic processing unit and realizes information processing in real time by performing arithmetic processing such as matching, which is conventionally performed by an arithmetic processing unit outside the memory, in each memory itself. Become.
[0005]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is not only to store analog and multi-value data using a simple circuit, but also a semiconductor that can compare input data with stored data. Calculation A circuit is provided.
[0006]
[Means for Solving the Problems]
reference Invention semiconductor Calculation The circuit stores a first signal, and a predetermined second value when a difference in magnitude between the second signal and the stored first signal is smaller than or larger than a predetermined first value. Is output.
[0007]
The first signal may be an input signal dynamically stored at an arbitrary moment.
[0008]
Further, the first signal is stored by a mask pattern in a photolithography process.
[0009]
Semiconductor of the present invention Calculation The circuit is a semiconductor of the present invention. Calculation The circuit has a semiconductor region of one conductivity type on a substrate, and a source and drain region of opposite conductivity type provided in this region, and a region separating the source and drain regions via an insulating film. And a plurality of input gate electrodes capacitively coupled to the floating gate electrode through an insulating film. A CMOS-type neuron MOS inverter composed of an n-type neuron MOS transistor and a p-type neuron MOS transistor has two CMOS type neuron MOS inverters and has at least one first input. A signal is input in common to an input gate that is capacitively coupled to the floating gate electrodes of the first CMOS type neuron MOS inverter and the second CMOS type neuron MOS inverter through an insulating film. The logical OR (XOR) of the output signal of the first CMOS type neuron MOS inverter and the output signal of the second CMOS type neuron MOS inverter can be performed. It is characterized by that.
[0010]
Also input from outside First Depending on the signal Via the first MOS transistor, the potential of the floating gate electrode of the first CMOS type neuron MOS inverter is set. Predetermined value In Can change At the same time, the potential of the floating gate electrode of the second CMOS type neuron MOS inverter can be changed to a predetermined value via the second MOS transistor by the second signal inputted from the outside. It is characterized by that.
[0011]
Further, the semiconductor of the present invention Calculation The circuit compares a plurality of signal sequences stored in the memory unit with a first signal sequence input from the outside, and determines a signal sequence that is most similar to or completely coincides with the first signal sequence. A memory unit of an associative memory having a function of searching from a plurality of signal sequences stored in the memory unit is configured.
[0012]
Furthermore, the semiconductor of the present invention Calculation The circuit stores the first image information, and is used in a circuit that compares the stored first image information and second image information.
[0013]
[Action]
reference invention In According to the conventional memory function for storing information, a function for comparing the input information and the stored information to check for coincidence / mismatch is added. In this case, it is possible to reduce the burden on the arithmetic processing circuit outside the memory and to perform information processing in real time.
[0014]
reference According to the invention, since information at an arbitrary moment can be dynamically captured, it can be used, for example, for comparing signals constituting moving image information that changes every moment.
[0015]
reference According to the invention, for example, when an input image is compared with a predetermined image, the input signal information may be compared with predetermined signal information determined by a mask level. There is an advantage that information can be retained even if it is cut.
[0016]
Claim 1 According to this invention, the number of elements can be greatly reduced as compared with the conventional method by configuring the circuit using νMOS that can handle all analog, multilevel, and binary digital signals as inputs.
[0017]
Claim 2 According to the present invention, the match / mismatch determination criteria can be made variable, so it is possible to roughly determine match / mismatch or to strictly match / mismatch, and flexibly according to the application. The function can be changed.
[0018]
Claim 3 According to the present invention, associative memory that is applied to a dictionary with an associative function, etc. is difficult to increase in scale and integration because the number of wirings and the number of elements is enormous in conventional binary digital processing. The memory can be scaled up and highly integrated.
[0019]
Claim 4 According to the invention, when transmitting a huge amount of moving image information, not all the signal information constituting each rotating image is transmitted, but the portion of the image signal that is different from the signal information of the image currently stored in the memory is transmitted. Only the signal information is transmitted, and the other signal information is used as it is, so that the amount of information to be transmitted can be drastically reduced. By incorporating the circuit of the present invention into a pixel, a new image and a currently stored image can be simultaneously compared at the pixel level, which can be very useful for data compression of this moving image information.
[0020]
【Example】
The present invention will be described in detail below with reference to examples, but it goes without saying that the present invention is not limited to these examples.
[0021]
Example 1
reference A first embodiment of the invention will be described with reference to the circuit of FIG. This is a circuit that compares input 6-bit signal information with stored 6-bit signal information and outputs 1 if they match. 114 is a 2-input XNOR circuit that outputs 1 only when the signals input to the terminals 101 and 107 match, 115 is a NAND, and 116 is a circuit that implements NOR logic. These circuits can be constituted by ordinary CMOS circuits.
[0022]
First, a signal is input to the inputs 101 to 106. For example, the inputs 101 to 106 may be connected to the power source or the ground through a switch, or may be directly connected to the power source or the ground without passing through the switch. When the inputs 101 to 106 are connected to the power supply or the ground through the switch, the signal information of the power supply voltage or the ground voltage is temporarily stored in the capacitance of the inputs 101 to 106 by turning off the switch after the connection. . Further, when connecting directly to a power supply or ground without passing through a switch, the inputs 101 to 106 may be connected to a predetermined voltage by a mask in a photolithography process.
[0023]
Next, when signal information is input to the inputs 107 to 112, the input signal information is compared with the signal information stored in 101 to 106, respectively, and if all 6 bits match, 1 appears in the output 113. .
[0024]
In addition to the memory function of storing a signal, this circuit itself also has a function of performing a comparison operation between the input signal and the stored signal. Since the comparison operation of matching / mismatching can be performed in parallel for each memory cell that stores information, the contents of the memory can be compared sequentially with the input signal while reading the contents of the memory in time series using the operation processing outside the memory. Information processing such as image matching can be performed at a higher speed than the conventional system.
[0025]
FIG. 1B shows a circuit configuration when the input is an analog signal. An A / D converter 134 for converting an analog signal into a digital signal is attached to the input stage. The analog input signal 120 is A / D converted into 6 bits and input to the terminals 121 to 126 through the switches 135 to 140 and stored. Next, the input analog signal is A / D converted into 6 bits by the A / D converter 134 and is input to the terminals 127 to 132 through the switches 135 to 140. The input signal information is compared with the signal information stored in 121 to 126, respectively. If all 6 bits match, 1 appears in the output 133.
[0026]
In this circuit, signals A / D converted are stored in 121 to 126, but may be directly connected to a power source or a ground through a switch in the same manner as in FIG. After connection, the signal can be temporarily stored in the capacity of the inputs 121 to 126 by turning off the switch. Further, the inputs 121 to 126 may be connected to a predetermined voltage by a mask in the photolithography process.
[0027]
In this circuit, determination of coincidence / mismatch between the input analog signal and the stored analog signal is made with an accuracy of 6 bits, which is determined by the number of bits of the A / D converter.
[0028]
Therefore, although the circuit is composed of 6 bits here, it may be composed of any number of bits depending on the application.
[0029]
(Example 2)
A second embodiment of the present invention is shown in FIG. This is a circuit that compares input analog signal information with stored analog signal information and outputs 1 if they match within a certain range.
[0030]
The difference from FIG. 1B is that a νMOS inverter that can handle all analog, multilevel, and binary digital signals as inputs is used. As a result, the number of elements could be greatly reduced.
[0031]
In order to explain the circuit operation of FIG. 2, first, the structure and operating principle of the νMOS will be described. FIG. 12A shows an example of a cross-sectional structure of a four-input N-channel νMOS transistor (N-νMOS), where 401 is a P-type silicon substrate, and 402 and 403 are N + diffusion layers. Source and drain formed 404, a gate insulating film (for example, SiO2 film) provided on a channel region 405 between the source and drain, 406 is electrically insulated, and is electrically floating. A floating gate electrode 407 is an insulating film such as SiO2, and 408a, 408b, 408c, and 408d are input gate electrodes. FIG. 12B is a diagram further simplified to analyze the νMOS operation. As shown in the figure, the capacitive coupling coefficients between each input gate electrode and the floating gate are C1, C2, C3, C4, and the capacitive coupling coefficient between the floating gate and the silicon substrate is C0. The potential ΦF of the ting gate is given by the following equation.
[0032]
ΦF = (1 / CTOT) (C1V1 + C2V2 + C3V3 + C4V4)
However, CTOT = C0 + C1 + C2 + C3 + C4
V1, V2, V3, and V4 are voltages applied to the input gates 408a, 408b, 408c, and 408d, respectively, and the potential of the silicon substrate is assumed to be 0V, that is, grounded.
[0033]
Now, the potential of the source 402 is set to 0V. That is, it is set to a value measured using the potentials of all the electrodes as a source reference. Then, if the floating gate 406 is regarded as a normal gate electrode, it is the same as a normal N-channel MOS transistor, and when the gate potential ΦF becomes larger than the threshold value (VTH *), the An electron channel (N channel) is formed in a region 405 between the source 402 and the drain 403, and the source and drain are electrically connected. That is,
(1 / CTOT) (C1V1 + C2V2 + C3V3 + C4V4)> VTH *
When the above condition is satisfied, the νMOS conducts (turns on).
[0034]
The above is an explanation of an N-channel νMOS transistor. In FIG. 12A, there is a device in which the source 402, the drain 403, and the substrate 401 are all of opposite conductivity types. That is, the substrate is an N type, and the source / drain is a νMOS formed of a P + diffusion layer, which is called a P channel MOS transistor (P-νMOS).
[0035]
In FIG. 2, 211 and 212 are νMOS inverters composed of N-νMOS and P-νMOS, 205 and 206 are NMOS transistors, 215 is a normal inverter, and 217 is an AND circuit.
[0036]
When storing a signal, an analog signal to be stored is input to the input 201 and the storage command signal 202 is set to 1. At this time, the potentials VL (<VTH *) and VH (> VTH *) are written to the floating gates 209 and 210 of the two νMOS inverters 211 and 212 through the transistors 205 and 206, respectively.
[0037]
VTH * is a threshold value seen from the floating gates 209 and 210 of the νMOS inverters 211 and 212. At this time, since the νMOS inverter output 213 is 0 at 1 and 214, the circuit output 218 is 1.
[0038]
Next, when .PHI.c is set to 0, the floating gates 209 and 210 of the .nu.MOS inverter enter the floating state, and the subsequent floating gate potential changes as VIN changes.
[0039]
FIG. 3 shows the relationship between the floating gate voltage of the νMOS inverters 211 and 212 after storing the signal information and the voltage of 201. For example, this is the case when writing is performed with VIN = V0. The relationship between the floating gate potential of the νMOS inverter and VIN is shown. Reference numeral 221 denotes the floating gate voltage of the νMOS inverter 212, and 222 denotes the floating gate voltage of the νMOS inverter 211.
[0040]
The floating gate potential of each νMOS inverter changes with a slope of γ / 2 with respect to VIN if the capacitive coupling of the two inputs of the νMOS inverter is made equal. Here, γ is the ratio of the total coupling capacitance of the two input terminals of the νMOS inverter to the floating gate in the total capacity of the floating gate.
[0041]
When VH and VL are set larger or smaller by ΔV than the threshold value VTH * viewed from the floating gate, VOL = 1 and VOH = 0 only in the range of V0−2ΔV / γ <VIN <V0 + 2ΔV / γ. Thus, VOUT = 1. VOL and VOH are both 1 or 0 and VOUT is 0 regardless of whether VIN is lower or higher. That is, VOUT is output as 1 only when VIN falls within the range defined by VL and VH.
[0042]
In this circuit, VL and VH may be circuit-fixed voltages or may be given arbitrary voltages from the outside. At this time, the range of coincidence / mismatch determination can be freely changed.
[0043]
After a multi-level signal is stored in the memory, after a certain period of time, the window function range fluctuates from the write range due to leakage of the transistor connected to the floating gate, and the multi-level signal stored in the memory In order to prevent the occurrence of accurate association, it is necessary to periodically refresh the stored multilevel signal. An example of a circuit obtained by adding a refresh circuit to the circuit of FIG. 2 is shown in FIG. In this refresh operation, all multi-level levels handled with the refresh signal ΦRE set to 1 are input to VΙN, so that Φc is automatically set to 1 when VIN matches the stored signal. Will be done. This refresh operation can be performed simultaneously on all DRAM cells periodically.
[0044]
However, in the circuit of the νMOS configuration, the width of the window function to be separated becomes narrower as the multi-bit association is realized, so that the refresh interval of the dynamically stored signal may be shortened. When handling N-bit multi-values, the input voltage needs to be divided by the width of VDD / 2N, but this input voltage width is γ / 2 times at the floating gate level, so that γVDD / 2N + 1. If the capacitance of the floating gate is CTOT, the amount of charge leaked from the floating gate during the refresh time T must be suppressed to CTOTγVDD / 2N + 1 or less. In order to satisfy this, the leakage current of the transistor connected to the floating gate needs to be equal to or less than CTOTγVDD / (2N + 1T).
[0045]
For example, if the power supply voltage is 3 V, N = 6 bits, γ = 0.8, and CTOT = 10f (F) T = lmsec, the leakage current must be about 2 × 10 −13 (A) or less.
[0046]
Further, since the shift in the threshold value seen from the floating gates of the two νMΟS inverters directly affects the matching accuracy, it is necessary to suppress this as much as possible.
[0047]
FIG. 5 is a photomicrograph of an associative DRAM fabricated by a two-layer polysilicon process, and FIG. 6 shows the measurement result. It can be seen that the output is 1 when the written multi-value signal matches the input signal.
[0048]
When such a multi-valued memory having a match / mismatch determination function is realized with the CMOS configuration of FIG. 1B and the νMOS configuration of FIG. 2, the number of transistors required is the CMOS of FIG. The configuration requires about 1000 transistors, whereas the νMOS configuration of FIG. 2 can be realized with about 20 transistors, and it can be seen that the number of elements is dramatically reduced by using νMOS.
[0049]
Here, the transistors 205 and 206 are NMOS, but this may be PMOS. In this case, the signal 202 may be reversed from that for NMOS. Further, the outputs 213 and 214 may be inverted any number of times as long as they are input to a logic circuit that can detect the difference between the signals of the outputs 213 and 214.
[0050]
(Example 3)
Using the same principle, it is possible to design a multi-value ROM having a match / mismatch determination function. FIG. 7 shows a multi-value ROM having a matching / mismatch determination function for eight types of multi-value signals. The input terminals 301 of the νMOS inverters 306 and 307 are for input signals. The inputs 302 and 303 are divided into eight at the same ratio for threshold adjustment of each νMOS inverter as viewed from the input terminal 301, and VDD and VSS are capacitively coupled through the divided eight input terminals.
[0051]
In the two νMOS inverters 306 and 307, the threshold value of each νMOS inverter viewed from the input 301 is changed by changing the ratio of the number of terminals connected to VDD and VSS in the inputs 302 and 303. In this example, three of the eight inputs in input 302 are connected to the power supply and five are connected to ground. On the other hand, of the eight inputs in the input 303, four are connected to the power source and three are connected to the ground.
[0052]
As a result, the threshold values seen from the input terminals of the two νMOS inverters are different, and the outputs 306 and 309 are 1 and 0, respectively, only when the signal of the input 301 enters the window function sandwiched between the two threshold values.
[0053]
Reference numeral 311 denotes an XNOR circuit configured using a νMOS, which outputs 1 only when the signals 308 and 309 are different.
[0054]
Therefore, the output 310 becomes 1 only when the signal of the input 301 enters the window function sandwiched between the thresholds viewed from the input terminals 301 of the two νMOS inverters.
[0055]
FIG. 8 shows the simulation result of this circuit. FIG. 8 (a) shows the time change of the input signal, and FIG. 8 (b) shows the outputs of eight types of multi-value ROMs having a match / mismatch determination function for multi-value signals. By shifting the number of nodes connected to VDD and VSS by one, the threshold value seen from the input terminal changes between the two νMOS inverters, and eight types A to H sandwiched between adjacent threshold values. A window function is formed. When the input signal enters this window, it can be seen that 1 is output.
[0056]
In this circuit, the XOR 311 may be constituted by a normal CMOS logic circuit. Further, if one of the outputs 308 and 309 is inverted, this may be an XNOR circuit.
[0057]
Needless to say, another logic circuit may be used as long as the difference between the outputs of 308 and 309 can be detected. Here, an example is shown in which the inputs 302 and 303 are divided into eight, but this may be any division.
[0058]
As described above, the input voltage is given as an analog value in FIGS. 2 and 7, but this may be given as a plurality of binary digital signals. At that time, the input terminal is provided only for the bit and is coupled to the floating gate of the νMOS inverter. What is necessary is just to give a weight to capacity and combine. The binary / digital signal is automatically D / A converted on the floating gate of the νMOS inverter and stored in the memory as an analog / multilevel signal.
[0059]
Example 4
A fourth embodiment of the present invention is shown in FIG. This is an example in which the circuit of the present invention is applied to an associative memory. Reference numeral 502 denotes a memory array portion. Here, a memory of 4 bits × 4 words is shown as an example, but this may be composed of an arbitrary number of bits and words.
[0060]
Reference numeral 501 denotes an input signal which is also input to the memory array in a 4-bit configuration. The input signal 501 is compared with a signal stored in each memory in the memory array, and a match / mismatch is checked. In this example, for example, in 512 words, the bits 503 and 505 do not match, and the bits 504 and 506 match.
[0061]
Similarly, the words 513, 514, and 515 are checked for coincidence / mismatch. The number of matching bits is checked for each word. For example, in the 512, 513, 514, and 515 words, it can be seen that 2, 1, 3, 0 of the 4 bits match. .
[0062]
From this result, it can be seen that 514 words that match in 3 bits are the most similar words to the input signal 501.
[0063]
In this circuit, each memory of the memory array is realized by using the circuits shown in FIGS. 2 and 7, thereby realizing an associative memory having a large number of elements and impossible to be integrated with a small number of elements. Is possible.
[0064]
(Example 5)
A fifth embodiment of the present invention is shown in FIG. This shows a memory plane having a function of comparing two pieces of image information and detecting different portions.
[0065]
In FIG. 10A, reference numeral 601 denotes a memory plane. On this plane, for example, the functional memory 602 shown in FIG. The functional memory in FIG. 11 has a structure in which the output of the optical sensor 608 is connected to the input terminal 609 portion of 607 having the same structure as the functional memory in FIG.
[0066]
This optical sensor 608 can be easily configured by a conventional technique using, for example, a bipolar transistor, and a voltage corresponding to the intensity of light is output to 609.
[0067]
Image information at a certain moment is output as a signal to a terminal 609 of each function memory, a signal “1” of a storage command is input to a terminal 610, and the image information at this time is stored in the high function memory plane 601. Thereafter, the signal of the storage command becomes “0” at the terminal 610, the floating gates 613 and 614 of the νMOS inverters 611 and 612 are in a floating state, and the storage operation is completed.
[0068]
Thereafter, the image information at that time is output to the terminal 609 every moment, and if the stored information and the information input to the 609 at that moment are from the range defined by VL and VH, the output 615 is 0, and 1 if within range.
[0069]
FIG. 10B shows a comparison result at a certain moment. For example, reference numerals 603, 604, and 605 represent functional memory portions where the comparison results do not match.
[0070]
When image information at a certain moment in a moving image is transferred to, for example, a display, if all the images of the next frame are also transferred again, the number of data becomes enormous and the transfer becomes slow and cannot be reproduced as a moving image.
[0071]
In order to solve this problem, when transferring the next frame image, compared to the currently displayed image information, the method of transferring only the signals of the pixels with different information is very effective in compressing the data amount. It becomes effective.
[0072]
That is, the image information currently displayed on the display is stored in the function memory plane 601 and is compared with the next frame information in real time.
[0073]
As a result, as shown in FIG. 10B, if only the pixels 603, 604, and 605 are inconsistent, only this pixel information needs to be transmitted to the display.
[0074]
At this time, if the storage command signal “1” is again input to the terminal 610 in the function memory plane 601 to store the latest image information, the same data compression is performed for the on-screen information of the next frame. It becomes possible.
[0075]
In all of the neuron MOS transistors in the circuit described above, a floating gate may be switched to initialize the floating gate potential to an arbitrary potential. Needless to say, the power supply voltage, the threshold value of the transistor, the ratio of the capacitance, and the value may be arbitrarily set according to the design in addition to the values given as examples.
[0076]
【The invention's effect】
According to the present invention, not only can analog and multi-value data be stored, but also a high-performance semiconductor that can compare input data with stored data. Calculation It became possible to realize the circuit.
[0077]
Moreover, since it can be realized with a very small number of elements by using a neuron MOS transistor, it is easy to implement LSI. Therefore, a wide range of application fields such as a new circuit architecture using multiple values can be pioneered, including the field of image processing that requires high-speed and real-time processing.
[Brief description of the drawings]
[Figure 1] reference It is a circuit diagram explaining Example 1 of invention.
FIG. 2 is a circuit diagram illustrating Example 2 of the present invention.
FIG. 3 is a graph showing a relationship between a floating gate voltage and an input voltage.
FIG. 4 is a circuit diagram showing a circuit configuration example incorporating a refresh circuit.
FIG. 5 is a photomicrograph showing the associative DRAM chip of FIG. 4;
6 is a graph showing characteristics of the circuit of FIG.
FIG. 7 is a circuit showing a third embodiment of the present invention.
8 is a graph showing a simulation result of the circuit of FIG.
FIG. 9 is a graph showing a fourth embodiment of the present invention.
FIG. 10 is a graph showing a fifth embodiment of the present invention.
FIG. 11 is a circuit diagram of a functional memory constituting a memory plane.
FIG. 12 is a conceptual diagram showing a configuration of a neuron MOS (νMOS) transistor.
[Explanation of symbols]
101-112 inputs,
113 outputs,
114 XNOR circuit,
115 NAND circuit,
116 NOR circuit,
134 A / D converter,
120 analog input signal,
135-140 switches,
121-126 terminals,
133 outputs,
205, 206 NMOS transistors,
209, 210 floating gate,
211, 212 νMOS inverter,
215 inverter,
217 AND circuit,
306, 307 νMOS inverter
301-303 inputs,
306, 309 output,
311 XNOR circuit,
401 silicon substrate,
402, 403 source and drain,
404 Gate insulating film,
406 floating gate electrode,
407 insulating film,
408a, 408b, 408c, 408d input gate electrode,
501 input signal,
512 words,
503, 505, 504, 506
513, 514, 515
601 memory plane,
602 functional memory,
609 Input terminal
608 optical sensor,
610 terminals,
611, 612 νMOS inverter,
613, 614 Floating gate.

Claims (4)

A semiconductor region of one conductivity type is provided on the substrate, and the source and drain regions of opposite conductivity type provided in this region and the region separating the source and drain regions are provided via an insulating film. N-type neuron having a floating gate electrode floating in potential and a plurality of input gate electrodes capacitively coupled to the floating gate electrode via an insulating film. A CMOS-type neuron MOS inverter composed of a MOS transistor and a P-type neuron MOS transistor has two CMOS-type neuron MOS inverters, and one or more first input signals are the first ones. Inputs capacitively coupled to the floating gate electrodes of the CMOS type neuron MOS inverter and the second CMOS type neuron MOS inverter through an insulating film. - is commonly input to preparative, first CMOS type news - that can be logically ORed with the output signal of Ron MOS inverters (XOR) performed - Ron MOS inverter output signal and the second CMOS type News A semiconductor arithmetic circuit. The first signal input from the outside, through the first MOS transistor, a first CMOS-type New - Ron MOS inverter furo - Tinguge - it is possible to change the potential of the gate electrode to a predetermined value, external The potential of the floating gate electrode of the second CMOS type neuron MOS inverter can be changed to a predetermined value via the second MOS transistor by the second signal input from The semiconductor arithmetic circuit according to claim 2 . A plurality of signal sequences stored in the memory unit and a first signal sequence input from the outside are compared, and a signal sequence that is most similar to or completely coincides with the first signal sequence is determined in the memory unit. 3. The semiconductor arithmetic circuit according to claim 1, wherein the semiconductor arithmetic circuit is used in a memory unit of an associative memory having a function of searching from a plurality of signal strings stored in the memory. Semiconductor computing circuit according to claim 1 to 3 for storing the first image information, it is characterized by using in the circuit for comparing the first image information and second image information that stored.

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