JP3603343B2 - Waveform reading device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a waveform reading apparatus for generating a waveform by reading, from a storage means, waveform data in which a difference between amplitude values of a waveform is encoded into floating-point data including a mantissa part and an exponent part using a predetermined waveform compression method. About.
[0002]
Problems to be solved by the prior art and the invention
In recent years, for example, digitalization has been advanced in electronic musical instruments, and computer technology has been widely introduced. For this reason, in an electronic musical instrument, a PCM digital sound source device (PCM sound source device) that generates (reproduces) a waveform by digital processing is widely mounted.
[0003]
In the PCM system, a sound (musical sound) emitted from a natural musical instrument or the like is sampled at a predetermined sampling cycle, and a sample value obtained by the sampling is quantized and converted into binary code to form waveform data. , The PCM tone generator has a memory that stores or stores such waveform data. A waveform reading device mounted on such a PCM tone generator reads waveform data from a memory and generates a waveform, and the PCM tone generator reproduces a musical tone using the waveform generated by the waveform reading device. Things.
[0004]
The PCM method has the advantage that the timbres of various sounds in the natural world can always be faithfully reproduced. However, in order to reproduce a sound having excellent frequency characteristics and an excellent S / N ratio, it is necessary to sample the sound at a high sampling frequency and quantize the sample value obtained thereby with a large number of bits. For this reason, the PCM method has a problem that a large-capacity memory is required to store waveform data.
[0005]
In order to avoid this problem, many waveform compression methods for compressing waveform data have been developed. For example, a DPCM method in which a difference value of waveform data is stored in a memory is a typical example. In some cases, the waveform data is converted into floating-point data including an exponent part and a mantissa part, thereby maintaining high data accuracy and reducing the amount of data (floating-point method). One of the decimal point methods is a differential compression floating point method.
[0006]
In this differential compression floating-point method, the difference value of the amplitude value of a waveform is not simply represented by floating-point data, but its exponent is further represented by a difference value, that is, a value obtained by accumulating the exponent up to that point ( Hereinafter, the difference value from the integral exponent value) is used as the value of the exponent part. Therefore, when this method is used, the data amount can be further reduced as compared with a case where the DPCM method and the floating point method are simply combined. In addition, in this method, there is a method in which one exponent part is shared by a plurality of mantissa parts to further reduce the data amount.
[0007]
The waveform data encoded by this method is first decoded by sequentially accumulating the exponent part, and then the mantissa part is decoded using the decoded exponent part (integral exponent value), that is, the waveform is decoded. The difference value of the amplitude value is decoded, and finally, the decoded difference value is sequentially accumulated to decode the amplitude value of the waveform.
[0008]
Incidentally, a general waveform reading apparatus has a loop function as a function for reducing the amount of waveform data stored in a memory. This function is a function of repeatedly reading out a part (loop range) of the waveform data stored in the memory to generate a waveform.
[0009]
Most natural instruments have long duration sounds, so sampling all of the sounds would result in a huge amount of data. However, since the generation of a waveform (reproduction of a musical tone) can be continued by this loop function, the amount of data stored in the memory can be significantly reduced. The waveform generated by the loop function can be attenuated by adding an envelope.
[0010]
The loop range that is repeatedly read by the loop function is usually managed by a start address (point) and an end address (point). However, when the waveform data is stored in the memory by the above-described differential compression exponent floating point method, for example, after reading out the waveform data to the end address, returning to the start address and reading out the waveform data, the exponent portion of the waveform data is read. , And the mantissa are each encoded with a difference value, so that the waveform data stored at this start address is decoded using an integral index value or the like accumulated up to that point, and a waveform cannot be accurately generated. There was a problem.
[0011]
Although the amount of waveform data can be reduced by the differential compression exponent floating-point method, the amount of waveform data increases according to the length of the sampling period. There has been a demand for a waveform reading device capable of maintaining the above.
[0012]
In order to avoid such a problem, there is a waveform reading apparatus that selects an address at which the amplitude value of the waveform data stored therein becomes 0 as a start address and an end address. However, in this waveform reading device, since an arbitrary loop range cannot be selected, there is a problem that a waveform of a desired portion cannot be generated, and a problem that a complicated operation for detecting the address is required.
[0013]
Another type of waveform reading device corrects waveform data (difference value) stored in a memory so that the average value of waveform data in the loop range becomes zero. However, in this device, when applied to a sound source device in which many types (tone colors) of waveform data are stored, the above-described correction must be performed for each type, and the work required for the correction becomes extremely complicated. There was a problem. In addition, there is also a problem that the sound quality of the reproduced musical tone may be deteriorated by this correction.
[0014]
An object of the present invention is to provide a waveform reading device that further reduces the data amount when waveform data obtained by encoding a difference value between waveform amplitude values is stored, and that accurately maintains waveform generation. It is in.
[0015]
[Means for Solving the Problems]
According to the waveform reading apparatus of the present invention, first, a waveform data in which a difference value of the amplitude value of a waveform is encoded into floating-point data including a mantissa part and an exponent part using a predetermined waveform compression method.And generation information for generating a waveform amplitude value from waveform data within a preset loop range.Is stored.
[0016]
In this storage means, for example, floating point dataAre stored in the same storage location as a predetermined number N of mantissa parts and a differential exponent part having an exponent part shared by the predetermined number N as a difference value.From the top of the loop range, the waveform data and the amplitude value and integral exponent value of the waveform corresponding to the number of storage locations based on the maximum value of the step amount of the storage location corresponding to the pitch are stored.
[0017]
The designation means specifies a storage location from which the waveform data is read from the storage means.At a predetermined timingWhile sequentially specifying, the storage location within the loop range of the waveform data stored in the storage means is repeatedly specified.
[0018]
The waveform generating means reads the waveform data from the storage location specified by the specifying means., At a first arithmetic processing timing obtained by dividing the predetermined timing by N + 1,The difference exponent part is sequentially accumulated to generate an integral exponent value,At the second and subsequent arithmetic processing timings,Expand the mantissa using the generated integral index value., Corresponding to each of the arithmetic processing timingsA difference value is generated, a waveform is generated by sequentially accumulating the generated difference value, and when the designating means returns to the head portion in the loop range and designates a storage location, the mantissa read from the storage location is designated. A difference value is generated using the integral index value of the generated information corresponding to the storage location and the storage location, and a waveform is generated using the amplitude value of the generated information corresponding to the storage location.
[0020]
[Action]
The waveform reading device of the present invention generates a waveform from waveform data in a loop range.DoWhen the designation of the loop range is repeated, the information used for generating the waveform is replaced with the generated information, and the waveform is generated by the waveform data in the loop range. Thus, the loop range can be arbitrarily specified, and the waveform to be generated within the loop range is accurately generated.
[0021]
For example, when the differential compression floating-point method is adopted as the waveform compression method, for example, in order to decode the waveform data at the beginning of the loop range, the integral exponent value and the integral waveform value corresponding to the waveform data are generated. When the loop range specification is repeated and the first waveform data is specified again, the difference value of the amplitude value is decoded using the integral index value of the generation information, and the decoded difference value is generated as the generation information. A waveform is generated by adding the integral waveform value to
[0022]
【Example】
Hereinafter, embodiments of the present invention will be described in detail in the order of the first embodiment and the second embodiment with reference to the drawings.
[0023]
FIG. 1 is a block diagram showing a configuration of a waveform reading device 100 according to a first embodiment. This waveform reading device 100 is applied to a sound source device mounted on an electronic musical instrument.
[0024]
As shown in FIG. 1, the waveform reading apparatus 100 includes a waveform memory 101 storing waveform data (storage data) obtained by compressing a difference value (waveform difference value) of the amplitude value of a musical sound waveform by a differential compression exponent floating point method. An address generator 102 for updating an address for reading waveform data from the waveform memory 101 as described later, and an address generator for inputting storage data read from the waveform memory 101,102And an integral interpolation circuit 103 which decodes the signals based on various signals input from the CPU and generates a musical tone waveform.
[0025]
The schematic operation of the above configuration will be described.
The address generator 102 determines an address from which stored data is read from the waveform memory 101 based on an instruction such as a tone color and a pitch (pitch) from a control unit of an electronic musical instrument (not shown), and uses this as address data. Output to As will be described later, a plurality of the address data are continuously output at a predetermined timing.
[0026]
Although details will be described later, the address generator 102 performs interpolation decimal point data, integral value step signal, and loop signal for the integral interpolation circuit 103 to generate a musical tone waveform using the storage data input from the waveform memory 101. And outputs these signals to the integration interpolation circuit 103.
[0027]
Here, the storage data stored in the waveform memory 101 will be described. FIG. 2A is an explanatory diagram showing a format of storage data stored in the waveform memory 101, and FIG. 2B is an explanatory diagram showing a musical tone waveform generated by the storage data.
[0028]
In FIG. 2, a symbol whose head is "A" indicates an address, and in the other symbols, "E" indicates an exponent part (value) of stored data, and "D" indicates a waveform difference value. Subscripts such as n and n + 1 in each symbol indicate a given position and displacement from this position (hereinafter, the same applies to other symbols, and unless otherwise limited, “x” is a subscript. Do).
[0029]
In FIG. 2A, each frame represents one bit (the same applies to other drawings hereinafter). In the first embodiment, the exponent part (differential exponent part) is two bits and the mantissa part. Indicates that a total of 8 bits of 6 bits are stored in the waveform memory 101 as storage data obtained by one sampling.
[0030]
In the differential compression exponent floating-point method adopted in the first embodiment, when a musical tone is sampled, the difference between the amplitude values obtained this time and the previous time is encoded into floating-point data, and the exponent part is converted to an exponent. This is the difference value in the section.
[0031]
Therefore, in order to generate a musical tone waveform for each address from the stored data stored in the waveform memory 101 in this manner, first, the differential exponents of the stored data stored at each address are sequentially accumulated to obtain the exponential part. Then, the mantissa is decoded using the decoded exponent (integral exponent value), that is, the waveform difference value is decoded, and finally the value obtained by accumulating the waveform difference value so far (integral waveform value) ) Is generated.
[0032]
The generation of the musical tone waveform is performed not only for each address according to the speed at which the stored data is read (address increment), but also for obtaining an amplitude value between a certain address and the next address, that is, interpolation. In many cases, (operation) must be performed.
[0033]
In the interpolation calculation in this case, for example, if an interpolation calculation (linear interpolation calculation) is performed between addresses An + 2 and An + 3, as can be seen from the tone waveform shown in FIG. Is the integral value of IW, the difference value stored as floating point data at address An + 2 is DW,AnAssuming that the difference from +2 to the position where the amplitude value is to be obtained (usually, the address is increased by one, this value is a ratio to the address expressed as a decimal number) is DA, and the amplitude value W is as follows: It can be calculated as follows.
[0034]
(Equation 1)
W = IW + DW · DA
The waveform memory 101 reads the stored data as described above in accordance with the address data output from the address generator 102, and outputs this to the integration interpolation circuit 103. Although described in detail later, the integral interpolation circuit 103 generates a musical tone waveform based on various signals input from the address generator 102 with respect to the storage data input from the waveform memory 101, and outputs this to a tone output unit (not shown). Output. Thereby, the musical sound is emitted from the musical sound output unit.
[0035]
The above is the schematic operation. Next, the address generator 102 will be described in detail with reference to FIG. FIG. 3 is a block diagram showing a circuit configuration of the address generator 102. The address generator 102 is roughly divided into an address updating unit, a step calculator 310, and an address generator.Generator311.
[0036]
The address updating unit includes a current value address RAM (Random Access Memory) 301, an address increment RAM 302, an end address RAM 303, a loop start address RAM 304, an adder 305, a data selector 306, a comparator 307, a subtractor 308, and an adder. 309.
[0037]
In this configuration, the operation of the address updating unit will be described first. Each of the RAMs 301 to 304 described above is controlled by the control unit of the electronic musical instrument. The current value address RAM 301 holds the initial value of the address of the waveform memory 101 in which the storage data corresponding to the timbre specified by the user is stored. The quantity RAM 302 holds the address increment corresponding to the pitch assigned to the performance operator (not shown) operated by the user, and the end address RAM 303 stores the value of the last address where the stored data of the timbre is stored. (End address value), and the loop start address RAM 304 holds the value of the start address (loop start address value) of the loop range in the stored data. This end address value indicates the last address of the waveform memory 101 in which the stored data is stored and also indicates the last address of the loop range.
[0038]
The current value address RAM 301 updates a current value (current value address) of an address from which stored data is read from the waveform memory 101 as needed, and holds the updated value. The adder 305 adds the current value address and the address increment stored in the address increment RAM 302, and outputs the addition result to the data selector 306, the comparator 307, and the subtractor 308.
[0039]
FIG. 4 is an explanatory diagram showing data output from each unit, and shows each data of the current value address, the address increment, and the output of the adder 305 (operation result).
[0040]
As described above, since each frame represents one bit, as shown in FIG. 4, the current value address is a total of 12 bits for the integer part and 6 bits for the decimal part.18This indicates that the address increment is 2 bits of the integer part and 6 bits of the decimal part, that is, a total of 8 bits of data. The output of the adder 305, which is a value obtained by adding the current value address and the address increment, is a total of 12 bits for the integer part and 6 bits for the decimal part, like the current value address.18This indicates that the data is bit data. In the first embodiment, since the address increment is 8-bit data in which the integer part is 2 bits, the pitch can be changed within a range that can be represented by the bit data.
[0041]
Here, in FIG. 4, as described later, the step calculator 310 generates an integration step signal at the time of normal address update, as will be described later, with respect to the current value address and the lower three bits of the integer part of the output of the adder 305. This is a signal for performing
[0042]
The comparator 307 compares the output value of the adder 305 with the end address value stored in the end address RAM 303, and outputs the comparison result as a 1-bit signal (loop signal). The comparison result is L (logical value is 0) when the output value of the adder 305 is smaller than the end address value, and is H (logical value is 1) otherwise.
[0043]
The subtractor 308 is an adder305And the end address value are subtracted, and the operation result is output to the adder 309. The adder 309 adds this operation result to the loop start address value held in the loop start address RAM 304, and outputs the operation result to the data selector 306.
[0044]
FIG. 6 is an explanatory diagram showing each data of the loop start address, the output of the subtractor 308, and the output of the adder 309. In FIG. 6, la and lb, which are the lower 3 bits of the integer part of the output of the loop start address and the subtractor 308, are used in a step operation during the loop operation to return the current value address to the beginning of the loop range, as described later. Device 310 is a signal for generating an integration step signal.
[0045]
When the data selector 306 receives the operation results of the adders 305 and 309, the data selector 306 selects one of them according to the comparison result input from the comparator 307. That is, when the comparison result is L, the operation result of the adder 305, H In this case, the operation result of the adder 309 is selected and output. The operation result output from the data selector 306 is updated in the current value address by being newly held in the current value address RAM 301, and the decimal part thereof is output to the integral interpolation circuit 103 as decimal part data for interpolation. You.
[0046]
When the comparator 307 outputs H, as described above, since the output value of the adder 305 is equal to or larger than the end address value, it is time to return to the beginning of the loop range and read stored data. That is, the comparator 307 indicates whether or not to perform a loop operation, and the result of the comparison is output to the integration and interpolation circuit 103 as a loop signal.
[0047]
When the comparator 307 outputs H, the subtractor 308 outputs a value obtained by subtracting the end address value from the output value of the adder 305 (hereinafter, referred to as an excess), and the adder 309 compares this value with the loop start value. The address value is added. That is, the output value of the adder 309 at this time is a value obtained by adding the excess of the end address value to the loop start address value. The output value of the adder 309 is input to the current value address RAM 301 via the data selector 306, and is newly held as the current value address.
[0048]
The operation of the address updating unit is summarized as follows.
The current value address initially held in the current value address RAM 301 by the control unit of the electronic musical instrument is sequentially updated by adding the address increment to the end address value until the current address exceeds the end address value. When the value obtained by adding the address increment exceeds the end address value, the excess is added to the loop start address value, and the added value is used as a new current value address to perform a loop, and the signal level is set to H. The loop signal is output to the integral interpolation circuit 103.
[0049]
Next, the step calculator 310 will be described.
In the first embodiment, since the differential compression floating-point method is employed, the integral index value and integral waveform value must be updated in accordance with the update of the current value address. However, as described above, since the address increment is a value having an integer part and a decimal part, even if the address increment is constant, the change amount of the integer part of the current value address is different. The step calculator 310 generates the update amount in the integer part of the current value address, that is, the update amount of the read address in the waveform memory 101, as an integral value step, and outputs this to the integral interpolation circuit 103.
[0050]
In order to generate an integrated value step signal, the step calculator 310 starts with the signal na which is the lower 3 bits of the integer part of the current value address read out from the current value address RAM 301, and similarly operates the adder 305. A signal nb from the output, a signal la from the loop start address RAM 304, and a signal lb from the output of the adder 309 are input (see FIGS. 4 and 6), and a loop signal is input from the comparator 307.
[0051]
As described above, the update of the current value address is performed at the time of the normal address update performed when the value is smaller than the end address value, and at the time of the loop operation performed when the value becomes equal to or more than the end address value. is there.
[0052]
The step calculator 310 normally subtracts the signal la from the signal lb when the address is updated, that is, when the loop signal is L, and the signal la when the loop signal is H, when the loop signal is H. The value is output to the integration interpolation circuit 103 as an integration step signal.
[0053]
FIG. 5 is an explanatory diagram showing an integral value step when updating a normal address, and FIG. 7 is an explanatory diagram showing an integral value step during a loop operation.
In the first embodiment, as described above, the integer part of the address increment is 2 bits. Therefore, as shown in FIG. 5, the value of the integral value step is in the range of 1 to 4D (4D = 100B) depending on the combination of the values of the signal na and the signal nb. This is the same during the loop operation shown in FIG.
[0054]
Next, the operation of the address generator 311 will be described. The address generator 311 inputs the output value of the data selector 306, the comparison result of the comparator 307, the end address value held by the end address RAM 303, and the integrated value step signal output by the step calculator 310. The address is generated according to the comparison result of 307.
[0055]
When the comparison result of the comparator 307 is L, the address generator 311 converts the input output value of the data selector 306, that is, the current value address, into an integer by rounding up or down, when updating the normal address. When the current value address is converted into an integer, three types of address values obtained by subtracting the value from the integer are generated, and these are sequentially output to the waveform memory 101 at predetermined timing as address data.
[0056]
FIG. 8A is an explanatory diagram showing an example of address data output by the address generator 311 at the time of updating the normal address. As shown in FIG. 7A, four address data are output in ascending order of the value.
[0057]
On the other hand, when the comparison result of the comparator 307 is H, the address generator 311 converts the current value address value into an integer in the same manner as described above, and adds the integral value step to the end address value in the loop operation. Then, an address value obtained by adding 5 to the address value and a current value address returned to the beginning of the loop range are generated.
[0058]
FIG. 8B is an explanatory diagram showing an example of address data output by the address generator 311 during this loop operation. The generated address data is output as shown in FIG.
[0059]
Here, the stored data of the loop range stored in the waveform memory 101 will be described with reference to FIG. FIG. 9A is an explanatory diagram showing an example of data stored after the beginning of the loop range and the end address, and FIG. 9B shows a musical tone generated from the stored data at the beginning of the loop range. FIG. 4 is an explanatory diagram showing a waveform. In FIG. 9, Ln is a loop start address, and EA is an end address.
[0060]
In the first embodiment, as described above, since the excess from the end address EA is 4D at the maximum, the current value address when returning to the beginning of the loop range is between addresses Ln to Ln + 4. Become. In the first embodiment, the integral exponent value and the integral waveform value corresponding to the storage data at the addresses Ln to Ln + 4 are calculated in advance so that a tone waveform can be generated from the storage data at the head portion, and these are calculated as end addresses. This is stored after EA.
[0061]
That is, the integrated waveform value IWV0 and the integrated exponent value IEV0 up to the storage data of the loop start address Ln are stored at the end address EA and the address EA + 5, respectively, and the integrated waveform values IWV1 to IWV1 corresponding to the storage data at the addresses Ln + 1 to Ln + 4 are stored. 4, and the integral exponent values IEV1 to IEV4 are similarly stored after the end address EA.
[0062]
Therefore, for example, when the current value address is looped to the loop start address Ln, by reading out the data stored in the end address EA and the address EA + 5, it is possible to accurately generate a tone waveform corresponding to the data. The same applies to the other addresses Ln + 1 to 4.
Next, the integral interpolation circuit 103 will be described with reference to FIG. FIG. 10 is a block diagram showing a circuit configuration of the integral interpolation circuit 103.
[0063]
The control circuit 1001 receives an integrated value step signal and a loop signal from the address generator 102, and generates and outputs various signals of sub, sel1, sel2, clr1, and clr2 based on these signals. It performs overall control (various signals will be described later).
[0064]
The data register 1002 stores the storage data output from the waveform memory 101 and outputs the stored data to the data selector 1003 and the shifter 1004. Since the stored data is floating point data, the data register 1002 outputs only the exponent data to the data selector 1003 together with the stored data.
[0065]
The data selector 1003 receives the select signal sel2 and the control signal clr2 from the control circuit 1001, and operates according to each signal. Specifically, when the value of the select signal sel2 is 0, the exponent part data input from the data register 1002 is 1, when it is stored data (floating point data) stored therein, and when it is 2, it is input from the shifter 1004. When the data is selected and the value of the control signal clr2 is 0, the data selected in this way is output to the adder / subtractor 1005, and when the value is 1, the output of the data is stopped (at this time). The data value is 0).
[0066]
The shifter 1004 expands by shifting the mantissa part of the storage data input from the data register 1002 according to the operation result input from the adder / subtractor 1005. That is, it decodes the waveform difference value and converts floating point data to fixed point data.
[0067]
The integral index value RAM 1007 stores the current integral index value. The integral exponent value RAM 1007 is controlled by the control circuit 1001 and writes the operation result of the adder / subtractor 1005 at a timing described later, thereby updating the integral exponent value in accordance with the reading of the stored data from the waveform memory 101.
[0068]
The integrated waveform value RAM 1008 stores the current integrated waveform value. Like the integral exponent value RAM 1007, the integral waveform value RAM 1008 is controlled by the control circuit 1001 and writes the operation result of the adder / subtractor 1005 at a timing described later, so as to read the stored data from the waveform memory 101. Update the integral waveform value.
[0069]
The data selector 1006 inputs the data read from the integral exponent value RAM 1007 and the integral waveform value RAM 1008, and operates according to the select signal sel1 and the control signal clr1 inputted from the control circuit 1001. Specifically, when the value of the select signal sel1 is 0, the integral waveform value data input from the integral waveform value RAM 1008 is selected, and when the value of the select signal sel1 is 1, the integral index value data input from the integral exponent value RAM 1007 is selected. Depending on the value, when the value is 0, the data selected in this way is output to the adder / subtractor 1005, and when the value is 1, the output of the data is stopped (the data value at this time is 0).
[0070]
The adder / subtractor 1005 performs addition / subtraction of data input from the data selector 1003 and the data selector 1006. The adder / subtractor 1005 receives a control signal sub from the control circuit 1001, and performs addition when the value of the signal is 0 and subtraction when the value of the signal is 1. The operation result of the adder / subtractor 1005 is output to the integral exponent value RAM 1007, the integral waveform value RAM 1008, and the data register 1009 in addition to the shifter 1004 described above.
[0071]
The data register 1009 holds the operation result of the adder / subtractor 1005 to perform the interpolation operation. Multiplier 1010 multiplies the decimal part data for interpolation output from address generator 102 by the waveform difference value output from shifter 1004, and outputs the multiplication result to adder 1011. Upon receiving the multiplication result from multiplier 1010, adder 1011 adds the multiplication result to the integral waveform value held in data register 1009, and outputs the addition result. The result of the addition is a waveform output output from the interpolation operation circuit 103.
[0072]
The above operation of the interpolation operation circuit 103 is divided into a normal address update operation and a loop operation, and the operation will be described with reference to FIGS. FIG. 11 is a timing chart showing an operation state of each unit at the time of normal address update, and FIG. 12 is a timing chart showing an operation state of each unit at the time of loop operation.
[0073]
As in FIG. 2, in FIG. 11, An and An + 1 to 3 are address data output from the address generator 102 to the waveform memory 101, and dn and dn + 1 to 3 are storage data read by the address data. .
[0074]
First, the basic operation of the integration interpolation circuit 103 will be described with reference to FIG. Here, in FIG. 11A, op1 to op8 are adder / subtracters.1005Shows the arithmetic processing performed by the program, and An + 3 is the current value address.
[0075]
For example, when the address data An is output from the address generator 102 to the waveform memory 101, the storage data dn is read from the address specified by the address data An, and stored in the data register 1002 at the timing shown in FIG.
[0076]
The select signal sel1 input to the data selector 1006 switches its value from 1 to 0, that is, from the integral exponent value RAM 1007 to the integral waveform value RAM 1008, while the data register 1002 stores the data dn. . Similarly, the select signal sel2 input to one data selector 1003 changes its value from 0 to 2, ie, from the exponent part data of the stored data stored in the data register 1002, the shifter 1004 The output to be selected is switched to the waveform difference value of the decoded storage data dn.
[0077]
During this time, that is, while the data register 1002 stores the data dn, the adder / subtractor 1005 executes the operation indicated by op1 and op2, and outputs the operation result. Thereafter, each time the data register 1002 stores another storage data, each unit performs the same operation. Here, in FIG. 10, the control signal esl is output from the control circuit 1001 to the data register 1003, and the decimal part data for interpolation is input to the shifter 1004. This will be described later in the second embodiment. Things.
[0078]
Taking the case where the contents stored in the integral index value RAM 1007 and the integral waveform value RAM 1008 are updated as an example, the outline of this operation is as follows.
That is, at the timing when the operation process op1 is performed, the data selector 1003 selects the data of the differential exponent part output from the data register 1002, and the data selector 1006 selects the integral exponent value output from the integral exponent value RAM 1007. , The adder / subtractor 1005 adds the difference exponent data and the integral exponent value. The result of this addition is input to the shifter 1004 and written into the integral index RAM 1007 as a new integral index, and the integral index is updated.
[0079]
At the timing when the operation process op2 is performed, the shifter 1004 outputs to the data selector 1003 the data obtained by expanding the mantissa of the data dn in accordance with the operation result input from the adder / subtractor 1005 in the operation process op1, that is, the decoded waveform difference value. This waveform difference value is output to the adder / subtractor 1005 via the data selector 1003. At this time, the data selector1006Outputs the integrated waveform value output from the integrated waveform value RAM 1008 to the adder / subtractor 1005, and the adder / subtractor 1005 adds the integrated waveform value and the waveform difference value. The result of this addition is written to the integrated waveform value RAM 1008, whereby the integrated waveform value is updated.
[0080]
Such an operation is performed each time the data register 1002 stores the storage data read from the waveform memory 101. Thus, the contents stored in the integral exponent value RAM 1007 and the integral waveform value RAM 1008 are updated in accordance with the address from which the stored data is read from the waveform memory 101.
[0081]
Next, the operation of each unit according to the size of the integral value step will be described. This integral value step is, as described above, the update amount of the address of the waveform memory 101 output from the address generator 102 to the integral interpolation circuit 103 (actually, the control circuit 1001).
[0082]
First, with reference to FIGS. 11A and 11B, the operation when the integral value step is 0 will be described.
FIG. 11 (b)Integral index valueAn operation example in the case where the RAM 1007 and the integrated waveform value RAM 1008 have already stored the integrated index value and the integrated waveform value up to the address An + 3 (current value address), respectively. For this reason, although not specifically shown, in FIG. 11B, the control circuit 1001 controls each of the RAMs 1007 and 1008 so that writing is not performed.
[0083]
When the interpolation operation is performed when the integral value step is 0, the necessary data is, as can be seen from Equation 1, the integral waveform value up to the address An + 2, the waveform difference value at the address An + 3, and the decimal part data for interpolation. It is. Since the decimal part data for interpolation is output from the address generator 102, the integral waveform value and the waveform difference value must be obtained.
[0084]
In FIG. 11B, the control signal clr2 is 0 (the signal selected by the select signal sel2 is output) and the control signal sub is 1 (subtraction) only when the operation process op8 is performed. . In the operation op7, since the integral index value from the adder / subtractor 1005 to the address An + 3 is output to the shifter 1004, the shifter 1004 outputs the waveform difference value corresponding to the address An + 3.
[0085]
Accordingly, in the operation op8, a value obtained by subtracting the waveform difference value at that time from the integrated waveform value up to the address An + 3 is output from the adder / subtractor 1005 to the data register 1009. On the other hand, the multiplier 1010 outputs a result obtained by multiplying the decimal part data for interpolation by the output value of the shifter 1004 at this time. Therefore, by adding the value stored in the data register 1009 and the multiplication result of the multiplier 1010 by the adder 1011, the tone waveform (the amplitude value thereof) is generated.
[0086]
Note that the addition result of the adder 1011 is an output of a waveform generated by the integration interpolation circuit 103. The output of the adder 1011 is input to the musical sound output unit at the timing when the arithmetic processing OP8 is performed. I have. That is, during the operation processes op1 to op7, the output from the adder 1011 is ignored.
[0087]
FIG. 11C shows an operation example when the integral value step is 1. In this operation example, in the operation process op7Integral index valueHas been updated, indicating that the integrated waveform value has been updated in the operation process op8.
[0088]
FIGS. 11D, 11E, and 11F show operation examples when the integral value step is 2, the integral value step is 3, and the integral value step is 4, respectively. . From these figures, it is understood that the integration index value and the integration waveform value are updated according to the value of the integration value step.
[0089]
Next, the operation of each unit during the loop operation will be described with reference to FIG. FIG. 12 is a timing chart showing an example of the operation state of each unit during the loop operation.
[0090]
As shown in FIG. 12, during the loop operation, the control signal clr1 is 1 and the select signal sel2 is1, The control signal clr2 is 0. For this reason, the adder / subtractor 1005 outputs the integrated waveform value IWVx stored in the data register 1002 in the operation processes op3 and opposition 4 and the integration exponent value IEVx stored in the data register 1002 in the operation processes op5 and op6. Is output.
[0091]
The control circuit 1001 causes the operation result of the adder / subtractor 1005 to be written into the integral waveform value RAM 1008 when the operation process op4 is performed, and the operation result of the adder / subtractor 1005 to the integral index value RAM 1007 when the operation process op5 is performed. Write. As a result, the stored contents of the integral exponent value RAM 1007 and the integral waveform value RAM 1008 are rewritten in accordance with the loop operation, that is, the transition of the current value address to the beginning of the loop range.
[0092]
In the operation op7, since the control signal clr2 is 1, the adder / subtractor 1005 outputs the integral exponent value output from the integral exponent value RAM 1007 as the operation result. At this time, the integral exponent value stored in the integral exponent value RAM 1007 is obtained by accumulating the differential exponents up to the storage data dn + x. Therefore, the shifter 1004 can correctly decode the waveform difference value by expanding the mantissa of the storage data dn + x according to the operation result of the adder / subtractor 1005.
[0093]
In the operation process op8, subtraction is performed between the integrated waveform value output from the integrated waveform value RAM 1008 and the waveform difference value decoded by the shifter 1004. As a result, the adder / subtractor 1005 outputs the integrated waveform values up to the address Ln + x to the data register 1009.
[0094]
Meanwhile, at this time, the multiplier 1010 outputs a value obtained by multiplying the waveform difference value input from the shifter 1004 by the decimal part data for interpolation to the adder 1011. By adding the value multiplied by the multiplier 1010 and the integrated waveform value stored in the data register 1009 by the adder 1011, a tone waveform during the loop operation is accurately generated.
[0095]
As described above, even if the current value address is returned to the head of the loop range, the tone waveform can be accurately generated from the stored data of the head. For this reason, since the period for sampling the sound can be shortened, the amount of stored data can be reduced, and the generation of the musical sound waveform can be continued. Further, since the generation of the musical tone waveform from the stored data of the head portion of the loop range is performed using the data (generation information) held for generating the musical tone waveform of the head portion, the held data is changed. Thus, the loop range can be arbitrarily and easily changed. Note that after this loop operation, the operation is a normal address update operation.
[0096]
Next, a second embodiment will be described. In the second embodiment, stored data in which two mantissas share one differential exponent is stored in the waveform memory 101, and the configuration is substantially the same as the configuration of the first embodiment. is there. Therefore, only the parts different from the first embodiment will be described using the same reference numerals as those in the first embodiment.
[0097]
FIG. 13A is an explanatory diagram showing a format of storage data stored in the waveform memory 101, and FIG. 13B is an explanatory diagram showing a musical tone waveform generated by the stored data.
[0098]
As shown in FIG. 13 (a), in the second embodiment, one address of the waveform memory 101 is 16 bits, 2 bits of the 16 bits are a difference exponent part, and the remaining 14 bits are 7 bits. Is the stored data as the mantissa of. Therefore, by reading stored data at one address from the waveform memory 101, two waveform difference values can be obtained as shown in FIG.
[0099]
Here, each symbol in FIG. 13B is, for example, Dn-1 and Dm-1 are the waveform difference values stored at this address An-1, and En-1 is the difference stored at this address An-1. It shows the value of the chemical exponent.
[0100]
As described above, in the second embodiment, the storage data stored at one address has two mantissas. Therefore, the address generator 102 stores the data from the waveform memory 101 as follows.dataIs determined.
[0101]
14A and 14B are explanatory diagrams showing data output from each unit. FIG. 14A shows data (current value address) output from the current value address RAM 301 and data (address) output from the address increment RAM 302. 2 shows the output data of the adder 305.
[0102]
As shown in FIG. 14A, in the second embodiment, select bits are allocated between a 12-bit integer part and a 5-bit decimal part. This select bit is for designating which of the two mantissa parts stored in one address is to be selected. For example, when the address An-1 is designated, if the value of the select bit is 0, the mantissa Dn-1 is selected, and if it is 1, the mantissa Dm-1 is selected.
[0103]
This select bit corresponds to the lower one bit of the integer part in the first embodiment. Therefore, the adder 305 simply adds the current value address and the address increment, and outputs the addition result.
[0104]
FIG. 14B shows data output from the loop start address RAM 304, output data of the subtractor 308, and output data of the adder 309. FIG.
[0105]
The addition result of the adder 305 is set as the current value address when updating the normal address, and the addition result of the adder 309 is set as the current value address during the loop operation. As shown in FIG. 14B, the select bits are assigned during the loop operation as in the case of the normal address update.
[0106]
FIG. 15A is an explanatory diagram showing the data stored after the beginning of the loop range and the end address in the second embodiment, and FIG. 15B is generated by using the stored data of this beginning. FIG. 4 is an explanatory diagram showing a musical sound waveform.
[0107]
In the second embodiment, as shown in FIG. 15A, the integrated waveform values IWV0 to IWV4 corresponding to the storage data at the beginning of the loop range are respectively stored at the end address EA to the address EA + 4, and the integrated exponent values IEV0 to IEV0 are stored. 4 is stored in the address EA + 5. In the second embodiment, the use efficiency of the waveform memory 101 is improved by storing all of the integral exponent values IEV0 to IEV4, which require a small number of bits for expressing the same, at the address EA + 5, that is, storage of storage data. Required area is reduced.
[0108]
For this reason, in the second embodiment, the address data output from the address generator 311 during the loop operation is the same as the address data obtained by adding the end address EA and the integral value step in FIG. , The address data obtained by adding 5 to the end address EA is output. Here, in the second embodiment, the stored data has two mantissas at one address.Integrated waveform value IWVAs in the case of the first embodiment, 0 to 4 and the integral exponent values IEV0 to 4 are integral waveform values and integral exponent values accumulated up to the address at the head of the loop range.
[0109]
Next, an integral interpolation circuit 103 according to a second embodiment will be described. First, with reference to FIG. 10, main points different from the first embodiment will be described.
As described above, in the integration interpolation circuit 103 according to the second embodiment, the control signal esl is output from the control circuit 1001 to the data selector 1003, and the interpolation decimal part data output from the address generator 102 is output in addition to the multiplier 1010. The data is input to the shifter 1004.
[0110]
The control signal esl is a control signal for selecting an integral index value (generation information) stored collectively at one address. For example, when the data selector 1003 inputs the integrated exponent values IEV0 to IEV4 stored in the address EA + 5 via the data register 1002, when the value of the control signal esl is 0, it selects the integrated exponent value IEV0 and sets the value to 1 When the value is 2, the integral index value IEV2 is selected when the value is 2, the integral index value IEV3 is selected when the value is 3, and the integral index value IEV4 is selected when the value is 4.
[0111]
Shifter 1004 receives storage data from data register 1002, expands two mantissa parts of the storage data according to the operation result (integral exponent value) input from adder / subtractor 1005, and outputs the data to data selector 1003 separately and sequentially. I do. Further, it selects the decoded waveform difference value according to the input select bits of the decimal part data for interpolation (which is the most significant bit of the decimal part data for interpolation), and outputs this to the multiplier 1010.
[0112]
The above is a main point different from the first embodiment. Next, the operation at the time of updating the normal address will be described with reference to FIG. FIG. 16 is a timing chart showing an operation state example of each unit at the time of normal address update.
[0113]
As shown in FIG. 16, in the second embodiment, since the storage data stored at one address has two mantissas, three operations are performed while the data register 1002 stores one storage data. Processing is executed.
[0114]
In the basic operation of FIG. 16A, for example, while the data register 1002 stores the storage data dn, the following basic operation is performed.
At the timing when the operation process op1 is performed, the select signal sel1 is 1 and the select signal sel2 is 0. Is added. The result of this addition is input to shifter 1004 and written to integral index RAM 1007. As a result, the integral index value is updated.
[0115]
At the timing when the operation process op2 is performed, the select signal sel1 is 0 and the select signal sel2 is 2, and at this time, the shifter 1004 outputs one of the waveform difference values (select (The bit specified by 0) is output to the data selector 1003. The adder / subtractor 1005 adds the decoded waveform difference value input via the data selector 1003 and the integrated waveform value input from the integrated waveform value RAM 1008. The result of this addition is written to the integrated waveform value 1008, and the integrated waveform value is updated. The control circuit 1001 controls the shifter 1004 so as not to input the result of the addition, so that the shifter 1004 performs the operation op1. Maintain the input integral exponent value.
[0116]
At the timing when the operation process op3 is performed, the select signal sel1 is 0 and the select signal sel2 is 2. At this time, the shifter 1004 outputs to the data selector 1003 the other of the mantissa part expanded in accordance with the operation result input in the operation process op1 (the one whose select bit is specified by 1). The adder / subtractor 1005 adds the decoded waveform difference value input via the data selector 1003 and the integrated waveform value input from the integrated waveform value RAM 1008. The result of this addition is written to the integrated waveform value RAM 1008, and the integrated waveform value is updated.
[0117]
Such an operation is performed each time the data register 1002 stores new storage data. Thus, the contents of the integral exponent value RAM 1007 and the integral waveform value RAM 1008 are updated in accordance with the update of the current value address for reading out the stored data from the waveform memory 101.
[0118]
Next, with reference to FIGS. 16A and 16B, the operation when the integral value step is 0 will be described.
FIG. 16 (b)Integral index valueAn operation example in the case where the RAM 1007 and the integrated waveform value RAM 1008 have already stored the integrated index value and the integrated waveform value up to the address An + 3 (current value address), respectively. For this reason, although not particularly shown, the control circuit 1001 controls so that these RAMs 1007 and 1008 do not perform writing.
[0119]
In FIG. 16B, the control signal clr2 is 0 only when the operation processes op11 and op12 are performed, and the control signal sub at this time is 1 (subtraction). In the operation process op10, the shifter 1004 inputs the integral exponent value from the adder / subtractor 1005 to the address An + 3. Output.
[0120]
Therefore, by performing the operation processes op11 and op12, the data register 1009 stores the integrated waveform values up to the storage data dn + 2. On the other hand, the multiplier 1010 multiplies the interpolation decimal part data by the waveform difference value selected and output by the shifter 1004 at this time, and the multiplication result of the multiplier 1010 and the data register 1009 store. The adder 1011 adds the integrated waveform value to generate a tone waveform.
[0121]
FIG. 16C shows an operation example when the integral value step is 1. In this operation example, in the operation process op10Integral index valueHas been updated, and the integrated waveform values have been updated in the operation processes op11 and op12.
[0122]
FIGS. 16D, 16E, and 16F show operation examples when the integral value step is 2, the integral value step is 3, and the integral value step is 4, respectively. . From these figures, it is understood that the integration index value and the integration waveform value are updated according to the value of the integration value step.
[0123]
Next, the operation of each unit during the loop operation will be described with reference to FIG. FIG. 17 is a timing chart showing an example of the operation state of each unit during the loop operation.
[0124]
As shown in FIG. 17, during this loop operation, the control signal clr1 is 1, the select signal sel2 is 1, and the control signal clr2 is 0 during the operation processes op4 to op9. For this reason, the adder / subtractor 1005 outputs the integrated waveform value IWVx stored in the data register 1002 in the operation processes op4 to op6, and outputs the integrated exponent value IEVx stored in the data register 1002 in the operation processes op7 to op9. Is output.
[0125]
The control circuit 1001 causes the operation result of the adder / subtractor 1005 to be written into the integral waveform value RAM 1008 when the operation process op6 is performed, and stores the operation result of the adder / subtractor 1005 in the integral index value RAM 1007 when the operation process op7 is performed. Write. As a result, the stored contents of the integral exponent value RAM 1007 and the integral waveform value RAM 1008 are rewritten in accordance with the loop operation, that is, the transition of the current value address to the beginning of the loop range.
[0126]
In the operation process op10, since the control signal clr2 is 1, the value of the select signal sel2 isRegardless, The adder / subtractor 1005 outputs the integral index value output from the integral index value RAM 1007 as a calculation result. At this time, the integral exponent value stored in the integral exponent value RAM 1007 is obtained by accumulating the differential exponents up to the storage data dn + x. Therefore, the shifter 1004 can correctly decode the waveform difference value by expanding the two mantissa parts of the storage data dn + x according to the operation result of the adder / subtractor 1005.
[0127]
In the operation op11, subtraction is performed by subtracting one of the waveform difference values decoded by the shifter 1004 from the integral waveform value output from the integral waveform value RAM 1008. In the operation op12, the adder / subtractor 1005 outputs in the operation op11. Subtraction for subtracting the other waveform difference value decoded by shifter 1004 from the integrated waveform value is performed. As a result, the adder / subtractor 1005 outputs the integrated waveform value up to the address Ln + x (Ln + x−1) to the data register 1009.
[0128]
On the other hand, at this time, shifter 1004 outputs the waveform difference value selected by the select bit of the decimal part data for interpolation to multiplier 1010, and multiplier 1010 compares the waveform difference value input from shifter 1004 with the decimal part for interpolation. The value obtained by multiplying the data is output to the adder 1011. By adding the value multiplied by the multiplier 1010 and the integrated waveform value stored in the data register 1009 by the adder 1011, a tone waveform during the loop operation is accurately generated.
[0129]
As described above, the second embodiment has the same effect as the first embodiment. However, in the second embodiment, one differential exponent is shared by two mantissas, and a loop operation is performed. Since the integral exponent value used at one time is collectively written into one address and written in the waveform memory 101, there is an effect that the amount of data stored in the waveform memory 101 can be further reduced.
[0130]
In the first and second embodiments (this embodiment), the generation information (a plurality of integral waveform values and integral exponent values) used during the loop operation is stored in advance after the end address. Since the integral waveform value and integral exponent value must be updated sequentially for generation, when the integral waveform value and integral exponent value at the beginning of the loop range are updated, these are retained as generation information. Is also good. This is effective in reducing the amount of data in a sound source device or the like having many tones.
[0131]
【The invention's effect】
As described above, the waveform reading apparatus of the present invention holds the generation information for generating a musical tone waveform from the waveform data of the loop range, and when the loop range is repeatedly specified, the generation of the musical tone waveform has been performed until then. This information is replaced with the generated information, and the generation of the musical tone waveform is performed using the waveform data within the loop range, so that the generation of the musical tone waveform can be accurately maintained, and the generation of the musical tone waveform can be accurately performed. Since the sound can be sustained, the sampling period of the sound (musical sound) can be shortened, so that the data amount of the waveform data can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a waveform reading device according to a first embodiment.
FIGS. 2A and 2B are an explanatory diagram showing a format of stored data and an explanatory diagram showing a tone waveform generated by the stored data; FIGS.
FIG. 3 is a block diagram showing a circuit configuration of an address generator.
FIG. 4 is an explanatory diagram showing data output from each unit.
FIG. 5 is an explanatory diagram showing an integral value step when updating a normal address.
FIG. 6 is an explanatory diagram showing data output from each unit.
FIG. 7 is an explanatory diagram showing an integral value step during a loop operation.
FIG. 8 is an explanatory diagram showing an example of address data output by an address generator.
FIGS. 9A and 9B are an explanatory diagram showing data stored after the beginning of the loop range and the end address, and an explanatory diagram showing a musical tone waveform generated based on the stored data at the beginning of the loop range. FIGS.
FIG. 10 is a block diagram illustrating a circuit configuration of an integration interpolation circuit.
FIG. 11 is a timing chart showing an operation state example of each unit at the time of updating a normal address (first embodiment);
FIG. 12 is a timing chart showing an example of an operation state of each unit during a loop operation (first embodiment).
FIGS. 13A and 13B are an explanatory diagram showing a format of stored data and an explanatory diagram showing a musical tone waveform generated by the stored data (second embodiment).
FIG. 14 is an explanatory diagram showing data output from each unit (second embodiment).
FIGS. 15A and 15B are an explanatory diagram showing data stored after the beginning of the loop range and the end address, and an explanatory diagram showing a musical tone waveform generated based on data stored at the beginning of the loop range; FIGS. Second Embodiment).
FIG. 16 is a timing chart showing an operation state example of each unit at the time of updating a normal address (second embodiment).
FIG. 17 is a timing chart showing an example of an operation state of each unit during a loop operation (second embodiment).
[Explanation of symbols]
100 Waveform reading device
101 Waveform memory
102 Address Generator
103 Integral interpolation circuit
301 Current value address RAM
302 Address increment RAM
303 End address RAM
304 Loop start address RAM
310 step calculator
311 Address generator
1001 control circuit
1003, 1006 Data selector
1004 shifter
1005 adder / subtractor
1007 Integral exponent value RAM
1008 Integrated waveform value RAM

Claims (1)

Using a predetermined waveform compression method, a difference value between a mantissa part of a predetermined number N whose difference value of a waveform amplitude value is floating-point data and an exponent part shared by the mantissa part of the predetermined number N is set as a difference value. The waveform data storing the exponent part in the same storage location, and as generation information for generating the amplitude value of the waveform from the waveform data in a preset loop range, from the beginning of the loop range to the pitch Storage means for storing an amplitude value and an integral index value of the waveform corresponding to the number of storage locations based on the maximum value of the amount of advance of the corresponding storage location;
Designating means for sequentially designating storage locations for reading waveform data from the storage means at predetermined timing, and repeatedly designating storage locations within the loop range of the waveform data stored in the storage means,
It reads waveform data from the storage location in which the designating means designates the predetermined timing in the first arithmetic processing timing N + 1 division, to produce an integrated index value by sequentially accumulating the difference of the exponent, the second and subsequent In the arithmetic processing timing, the mantissa is expanded using the generated integral exponent value, a difference value corresponding to each of the arithmetic processing timings is generated, and the generated difference value is sequentially accumulated, thereby forming the waveform. When the specifying means returns to the head portion in the loop range and specifies a storage location, the mantissa part read from the storage location and an integral index value of the generation information corresponding to the storage location are generated. A waveform generation unit that generates a difference value and generates the waveform using an amplitude value of the generation information corresponding to the storage location;
A waveform reading device comprising:

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