JP3599567B2 - Image reading apparatus and control method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing an analog signal using a clock signal whose frequency is continuously modulated. Reading Equipment and Its control About the method.
[0002]
[Prior art]
Conventional image forming apparatuses are mainly designed so that operation and control of each section are performed using a control / drive clock signal generated by a clock having high oscillation accuracy.
[0003]
However, in recent years, regulations that require suppression of radiation noise generated during the operation of an image forming apparatus have become stricter year by year. As a countermeasure, a frequency spreading technique that intentionally lowers the apparent oscillation accuracy is known. . This frequency spreading technology has the effect of periodically lowering the peak of radiation noise by continuously changing the oscillation frequency, and various types of control generated based on the frequency-spread clock signal. -Since the phase relationship is preserved for the drive clock, a normal operation can be performed in a digital system except for special cases.
[0004]
[Problems to be solved by the invention]
However, when frequency spreading is used for analog signal processing, such as a CCD line sensor, a device driven by a digital clock signal and outputting an analog signal waveform related to the phase relationship and pulse width of the clock signal When processing the output signal of the CCD line sensor, the frequency diffusion cycle and the driving cycle of the CCD line sensor cannot be synchronized, and the CCD line sensor changes subtly due to the influence of the frequency diffusion of the driving clock signal of the CCD line sensor. Of the output signal waveform and the data fluctuation of the sampling position, beat noise responding to the frequency spreading cycle may be generated, and an image may be formed in which the reference signal contains asynchronous beat noise during image formation. There was a problem.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an image forming apparatus for processing image data using a frequency spreading technique. At Images that can suppress the occurrence of beat noise and achieve good image formation Reading Equipment and Its control The aim is to provide a method.
[0006]
[Means for Solving the Problems]
To achieve the above objectives, According to the image reading device of the present invention, Oscillating means for oscillating a reference clock at a predetermined cycle, and using the reference clock oscillated by the oscillating means, generate a clock signal having a frequency higher than the frequency of the reference clock; this Frequency spreading means for continuously changing the frequency of the clock signal at a predetermined cycle with respect to the frequency of the reference clock; resetting for resetting the continuous change of the frequency of the clock signal by the frequency spreading means at a predetermined timing Means and the frequency spreading means And the operation of the reset means Control clock generation means for generating a control clock, Image reading means for reading image data based on the control clock, storage means for storing image data read in the correction data acquisition mode by the image reading means as correction reference data, and correction reference stored in the storage means Image correction means for correcting image data read in the normal reading mode by the image reading means using the data. It is characterized by the following.
[0007]
According to the control method of the image reading apparatus of the present invention, a clock signal having a frequency higher than the frequency of the reference clock is generated by using a reference clock oscillated by an oscillating unit that oscillates the reference clock at a predetermined cycle. A frequency spreading step of continuously changing the frequency of the signal at a predetermined cycle with respect to the frequency of the reference clock; and a resetting step of resetting the continuous change of the frequency of the clock signal by the frequency spreading step at a predetermined timing. A control clock generation step of generating a control clock based on the processing of the frequency spreading step and the reset step; and image data read in a correction data acquisition mode by image reading means for reading image data based on the control clock. In the storage means as correction reference data, and Using the correction reference data, to perform an image correction process for correcting the image data read by the normal read mode by said image reading means It is characterized by the following.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
(1st Embodiment)
First, a first embodiment of the present invention will be described with reference to FIGS.
[0017]
FIG. 1 is a block diagram showing a configuration of a clock signal generator capable of realizing a frequency spreading technique generally used in the related art.
[0018]
In FIG. 1, a clock signal generation unit 100 includes an oscillator 101, a frequency spreading circuit 102, and a drive / control clock generator 103. The oscillator 101 is an oscillating unit having a commonly used crystal oscillator, crystal oscillator, or the like. In recent years, some oscillators have a programmable oscillation frequency, and the oscillator 101 and the frequency spreading circuit 102 can be configured using an oscillator including a frequency spreading circuit.
[0019]
FIG. 2 is a timing chart showing the output timing of the clock signal output from the oscillator 101 and the frequency spreading circuit 102. FIG. 2A shows the clock signal output from the oscillator 101, and FIG. 3 shows a clock signal output from the circuit 102.
[0020]
As the oscillator 101, a high-precision oscillator having an oscillation accuracy of 100 PPM or 500 PPM is generally used. On the other hand, the frequency spreading circuit unit 102 oscillates while gradually changing the frequency of the clock signal output from the oscillator 101, as shown in FIGS. That is, the frequency of the output signal of the frequency spreading circuit unit 102 is continuous with a predetermined width such as ± 0.5% or ± 1.0% in the frequency calculation, for example, around the frequency (reference frequency) of the output signal of the oscillator 101. It is controlled so as to change. FIG. 2C illustrates such a frequency change.
[0021]
The clock signal output from the frequency spreading circuit 102 usually has a regular frequency spreading period, and as shown in FIG. 2C, the clock signal period becomes shorter (modulation toward a higher frequency). After changing by the predetermined modulation width, the frequency of the clock signal changes along the same characteristic curve in the direction in which the period of the clock signal becomes longer (modulation toward the lower frequency side) and returns to oscillation at the reference frequency. Repeat the modulation cycle. In other words, a timing at which the reference frequency and the phase coincide with each other occurs periodically for each frequency spreading cycle.
[0022]
Note that when the radiation noise is compared between the clock signal of the reference frequency of the oscillator 101 and the clock signal frequency-spread by the frequency spreading circuit 102, the result shown in FIG. 3 is obtained. FIG. 3 is a diagram showing a waveform of an output clock in the circuit shown in FIG.
[0023]
In FIG. 3, reference numeral 104 denotes a spectrum waveform of a clock signal having a reference frequency output from the oscillator 101, and reference numeral 105 denotes a spectrum waveform of a clock signal output from the frequency spreading circuit 102. As shown in the figure, the waveform 104 of the clock signal of the reference frequency output from the oscillator 101 has a peak at the natural frequency, whereas the waveform 105 of the clock signal output from the frequency spreading circuit 102 is Because of the divergence of the frequency, the peak level decreases as integrated. In general, even if the configuration conditions of the device are not good, the effect can be expected to be a noise reduction effect of at least about 4 to 5 dB · μV / m as the electric field strength as shown in FIG. In this case, a reduction effect of 10 dB · μV / m or more can be expected.
[0024]
Returning to FIG. 1, the clock signal frequency-spread by the frequency spreading circuit 102 is input to the drive / control clock generator 103. Various drive / control clock signals output from the drive / control clock generator 103 are all output as frequency-spread clock signals. Therefore, the noise reduction effect of the entire image forming apparatus employing the clock signal generation unit 100 can be obtained.
[0025]
Here, a phenomenon that becomes a problem when the clock signal generation unit 100 having the above configuration is used will be described.
[0026]
FIG. 4 is a diagram showing the signal output timing of the analog signal processing system performed in the image forming apparatus using the frequency spread. FIG. 4A shows the output timing of the output signal of the CCD line sensor (that is, the output timing of the CCD line sensor). FIG. 4B shows the output timing of the S / HF pulse for sampling the field-through portion, that is, the reference level, of the output signal of the CCD line sensor. 4 (c) shows the output timing of the S / HD pulse for sampling the data level of the output signal of the CCD line sensor, and FIG. 4 (d) shows the image data signal obtained as a result of sampling and holding. 4 (e) shows a state in which the operating frequency of each control signal is changing every moment.
[0027]
As described above, by using the frequency spreading technique, the driving clock signal of the CCD line sensor is frequency-modulated along the frequency spreading cycle, and the output signal width slightly changes for each pixel. Further, the output signal waveform of the CCD line sensor changes depending on the pulse width or phase relationship of the output stage transfer clock (φ2B) (not shown) and the residual charge reset pulse (RS) at the output stage. Therefore, as shown in FIG. 4A, the waveforms of both the reference level and the data level of the output signal of the CCD line sensor change. As shown in FIGS. 4B and 4C, the S / HF pulse for sampling the feed-through portion (reference level) of the output signal of the CCD and the S / HD pulse for sampling the data level are: , The pulse width and the sampling position are slightly changed. As a result, as shown in FIG. 4D, the output signal obtained as a result of the sample-and-hold becomes a signal on which beat noise responding to the frequency spreading period is loaded.
[0028]
FIG. 5 is a timing chart showing the output timing of the output signal when beat noise due to frequency spread occurs. FIG. 5A shows the output timing of the synchronization signal HSYNC, and FIG. 4) to 4 (d) show output signals for each pixel obtained as a result of sampling and holding the output signal of the CCD line sensor. FIG. 6 is an explanatory diagram illustrating an example of an output image obtained as a result of forming an image using read image data.
[0029]
As shown in FIGS. 5B to 5D, beat noise along the frequency spreading period appears in the output signal of the CCD line sensor, that is, the analog image signal for each pixel. When there is no synchronous relationship between the frequency spreading circuit and the synchronization signal HSYNC, beat noise flows as shown in FIGS. Therefore, when the image forming process is performed based on the output signal including the beat noise, an image including the beat noise is formed as illustrated in FIG.
[0030]
Therefore, in this embodiment, in order to fix the beat noise at a fixed position and realize noise elimination by the fixed noise pattern processing, a zero reset function is added to the frequency spreading circuit and the frequency is synchronized with the accumulation time of the CCD line sensor. A circuit configured to control generation of a drive / control clock is employed.
[0031]
FIG. Above Adopts a clock generator like Image reading device FIG. 2 is a block diagram illustrating an overall configuration of the image forming apparatus.
[0032]
In the figure, reference numeral 401 denotes an oscillator that oscillates a clock signal at a constant period, and is similar to the oscillator 101 shown in FIG. Reference numeral 402 denotes a clock generation unit having a built-in frequency spread circuit. In addition to the above-described frequency spread circuit, a PLL (Phase Lock Logic) circuit, a multiplication drive circuit, a counter circuit, and a comparison circuit are built in, and a plurality of types of drive / control clocks are provided. Generate a signal. The clock generating unit 402 log The drive control clock signal is connected to the IC 406 and the A / D converter 407, and the generated drive control clock signal is log It is supplied to the IC 406 and the A / D converter 407.
[0033]
Reference numeral 403 denotes a reference clock generation unit for supplying a stable clock signal to the clock generation unit 402, and includes a PLL circuit, a multiplication drive circuit, a counter circuit, and a comparison circuit. The reference clock generator 403 generates a frequency spread 0 reset signal HSYNC.
[0034]
The clock signal oscillated by the oscillator 401 is sent to the clock generator 402 and the reference clock generator 403. The reference clock generator 403 generates a reference clock, that is, a frequency spread 0 reset signal HSYNC, based on the clock signal sent from the oscillator 401, and sends it to the clock generator 402. When the frequency spread 0 reset signal HSYNC is input, the frequency modulation of the frequency spread circuit inside the clock generation unit 402 is reset once, and the frequency spread control is restarted from the reference frequency according to predetermined control.
[0035]
Reference numeral 404 denotes a multiple setting unit for setting the oscillation multiple of the PLL circuit in the clock generation unit 402 and the reference clock generation unit 403. When the power of the image forming apparatus is turned on, a predetermined multiple is set. Oscillation starts at the speed required for generation.
[0036]
Reference numeral 405 denotes a CCD line sensor used in a copying machine, an image scanner, a facsimile machine, and the like. The CCD line sensor 405 is supplied with a frequency-spread drive clock signal generated by the clock generator 402, and is driven and controlled by the drive clock signal.
[0037]
406 is Ana log It is an IC, and its driving is controlled by a driving clock signal generated in a clock generation unit 402. Anna log The IC 406 samples the output signal of the CCD line sensor 405 and performs offset control and gain control for adjusting the sampling signal to the input range of the A / D converter 407 at the subsequent stage. Anna log The above-described beat noise is included in the output signal of the IC 406, and is directly converted into video data which is digital data in the A / D converter 407. The video data is sent to the correction memory 409 via the line memory 408.
[0038]
If it is determined that the beat noise removal correction by the correction memory 409 is unnecessary by a method described later, the video data is sent to the printer control unit 413 as it is, and the image is formed by a known method.
[0039]
On the other hand, when it is necessary to perform correction data acquisition by the data control unit 410 (Correction data acquisition mode) First, after turning off a document irradiation unit (light source not shown) of the image forming apparatus, beat noise data is stored in the correction data storage unit 412 via the transfer unit 411. That is, the video data (default data for a black original) output from the CCD line sensor 405 when the reading operation is performed with the light source turned off is the video obtained when the reading operation is performed with the light source turned on. It corresponds to the beat noise included in the data.
[0040]
When the beat noise data is stored, the light source is turned on in the correction memory 409, and the normal method is used. (Normal reading mode) The correction processing for removing beat noise is performed by subtracting the correction data stored in the correction data storage unit 412 from the video data read by. The video data obtained as a result of this correction is sent to the printer control unit 413 as an image signal from which beat noise has been removed.
[0041]
When image formation is performed under the control of the printer control unit 413 after the beat noise has been removed as described above, an image in which no beat noise appears can be obtained as an output image, as shown in FIG.
[0042]
FIG. 8 is a timing chart showing output timings of signals generated in the image forming apparatus shown in FIG. FIG. 8A shows the output timing of the frequency spread 0 reset signal HSYNC, and FIG. 8B shows the output timing before the beat noise removal correction. log 8C shows output signals of the IC 406, FIG. 8C shows data stored in the correction data storage unit 412 when the correction data is taken in, that is, beat noise data, and FIG. 8D shows the output of the correction memory 409 after the beat noise removal correction. The output signal is shown.
[0043]
Ana shown in FIG. 8 (b) log The output signal of the IC 406 generates beat noise at a timing synchronized with the frequency spread 0 reset signal HSYNC. Therefore, in the configuration shown in FIG. 7, the output signal after the sample hold is repeatedly output in the sub-scanning direction in the same phase. Ana shown in FIG. 8 (c) log The output signal of the IC 406 corresponds to the beat noise data stored in the correction data storage unit 412 as described above. Therefore, when beat noise data is removed and corrected in the correction memory 409, a read image signal as shown in FIG. 8D can be obtained.
[0044]
FIG. 9 is a flowchart illustrating an operation procedure of the image forming apparatus illustrated in FIG. In this procedure, when the power of the image forming apparatus is turned on and a predetermined copy start operation is performed by an operator (step S601), the circuit system around the CCD line sensor 405 can perform a copy operation in conjunction with the operation. State.
[0045]
Normally, the CCD line sensor 405 and the like are in a state in which the image forming apparatus does not operate by controlling a power supply and a driving clock in a standby state as a countermeasure against temperature rise due to self-heating. Then, it is determined whether or not the CCD line sensor 405 has been turned on (step S602).
[0046]
When the CCD line sensor 405 is turned on, the drive clock is activated at the turned-on timing, and the output of the drive / control clock signal is started at the same time as the frequency spread 0 reset (steps S603 and 604). Then, the oscillation from the oscillator 401 is started and the counting of the number of clocks is started, and the clock signal subjected to frequency spreading is counted until the number of clocks corresponding to the accumulation time of the CCD line sensor 405 is counted (step S605). The clock is output from the clock generator 402.
[0047]
If it is determined in step S605 that the number of clocks corresponding to the accumulation time of the CCD 405 has been counted, the internal counter is reset and the frequency spread 0 is reset. After this processing, control of the system synchronized with the frequency spread 0 reset signal is performed. Becomes possible.
[0048]
Since a predetermined start-up time is required from when the power of the CCD line sensor 405 is actually turned on and the driving of the CCD line sensor 405 is started until the output signal of the CCD line sensor 405 is stabilized, a timer (not shown) is used. It is determined whether a predetermined start-up time has elapsed (step S606). Then, when a predetermined start-up time has elapsed, sampling of the correction data is performed (step S607). In the sampling of the correction data, the beat noise on the reference black level is sampled in the off state.
[0049]
The sampled correction data is stored in the correction data storage unit 412. When the sampling is completed, the light source is turned on (step S608), the image on the document is read line by line in accordance with a normal image reading procedure, and each line is read using the correction data stored in the correction data storage unit 412. Is corrected (step S609). At this time, the reset of the frequency spreading to 0 is executed every time the image is read for one line. The image data corrected in this way is sent to the printer control unit 413, and the printer control unit 413 forms an image (step S610).
[0050]
By such a series of operations, beat noise as shown in FIG. 6A generated due to frequency spreading is corrected and removed, and a good image as shown in FIG. 6B can be obtained. it can.
[0051]
As described above, according to the present embodiment, the frequency modulation of the frequency spread circuit is reset once by inputting the frequency spread 0 reset signal to the clock generator 402 each time the copy operation is started, and then the image reading is performed. Since the operation is started, as shown in FIG. 5, the occurrence position of the beat noise does not shift every time one line is read, and the beat noise is fixed at a fixed position, and the noise by the fixed noise pattern processing is fixed. Removal can be achieved. That is, by acquiring correction data at the start of reading and correcting the image data of each line using the correction data, it is possible to remove beat noise due to frequency spreading and obtain a good image. Become. Accordingly, it is possible to realize high-quality image formation while maintaining the quality of the read image data while maintaining the radiation noise reduction effect.
[0052]
(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.
[0053]
FIG. 10 is a block diagram illustrating a schematic configuration of the image forming apparatus according to the present embodiment. In the figure, reference numeral 801 denotes an oscillator that oscillates at a natural frequency, and 802 denotes a frequency spreading circuit including a PLL circuit capable of setting a multiplication factor. Depending on the PLL circuit configuration, it may not be possible to sufficiently follow the frequency spreading speed, and it may not be possible to realize smooth tracking of the frequency spreading. Therefore, in the present embodiment, the PLL circuit and the multiplication circuit are combined in the preceding stage, and the output clock is configured to use frequency spreading.
[0054]
Reference numeral 803 denotes a control device that controls the entire image forming apparatus. The control device 803 changes the driving speed of the frequency spreading circuit by setting a multiplication factor, on / off control of a power supply control unit 805 that supplies power to the CCD line sensor 807, and It performs control of taking in correction data.
[0055]
Reference numeral 804 denotes a drive / control clock generation circuit which outputs a drive clock for driving the CCD line sensor 807 in accordance with a clock output control signal output from the power supply control unit 805, thereby turning on / off the CCD line sensor 807. And an on / off control unit 806 for controlling the operation. When the frequency-spread clock signal output from the frequency spreading circuit 802 is input, the drive / control generation circuit 804 responds to the state of the output voltage of the power supply control unit 805 (that is, ON / OFF of the clock output control signal). The output of the on / off control clock from the on / off control unit 806 to the CCD line sensor 807 is controlled. That is, when the power is not supplied from the power control unit 805, the output of the CCD drive clock signal from the on / off control unit 806 is stopped because there is no need to output the CCD drive clock signal. When the power supply is turned on under the control of the power supply control unit 805, the CCD line sensor 807 receives the CCD drive clock signal output from the on / off control unit 806, and reads at a predetermined speed set by the control unit 803. Start operation.
[0056]
The output signal of the CCD line sensor 807 is sent to an analog signal processing circuit 808, and the analog signal processing circuit 808 performs processing such as sample hold, offset adjustment, and gain adjustment. The analog signal processing circuit 808 executes the above various processes in accordance with the analog processing control signal sent from the on / off control unit 806.
[0057]
The signal processed by the analog signal processing circuit 808 is converted into a digital video signal in an A / D converter 809. This video signal is input to the memory device 810.
[0058]
The memory device 810 has a line memory 811, a correction memory 812, and a correction data storage device 813. The line memory 811 is configured to take in the video signal output from the A / D converter 809 every main scanning line.
[0059]
In the above configuration, at the time of copy start, the video signal captured in the line memory 811 is captured in the correction data storage device 813 via the correction memory 812 at a timing corresponding to the correction data capture control signal input from the control device 803. Is memorized. As in the first embodiment described above, the correction data is taken in by sampling beat noise on the black level, which is a reference, with the light source (not shown) turned off. Therefore, the video signal stored in the correction data storage device is data corresponding to beat data.
[0060]
After storing the correction data in the correction data storage device 813, a normal document image reading operation is performed. In the document image reading operation, beat noise removal correction is performed in the correction memory 812 for each line data of the document image read by the CCD line sensor 807. The video signal corrected for the beat noise is sent to the image processor 814. Then, in synchronization with the frequency spread 0 reset signal, that is, the synchronization signal HSYNC, the image processor 814 performs an image forming process including an image decoration process.
[0061]
As described above, even in the case of the configuration shown in the present embodiment, the beat noise is fixed to a fixed position and fixed noise pattern processing is performed similarly to the case of the above-described first embodiment. In addition, beat noise due to the frequency spreading period can be removed. Therefore, it is possible to realize high quality image formation while maintaining the quality of the read image data while maintaining the radiation noise reduction effect.
[0062]
【The invention's effect】
As explained above According to the present invention, Beat noise generated by performing wave number spreading The Simple method Divided by You can leave. Therefore, the effect of suppressing generation of beat noise and achieving good image formation can be obtained.
[0063]
According to the image forming apparatus of claim 3 or 4, or the clock control method of claim 7, 8, or 9, the image data read in synchronization with the reference signal is stored as correction reference data, and the stored correction reference is stored. Since the read image data is corrected using the data, it is possible to remove the beat noise caused by the frequency spread and obtain a good image. This is an image forming apparatus that performs processing, and has an effect that generation of beat noise can be suppressed and good image formation can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a clock signal generator capable of realizing a frequency spreading technique generally used conventionally.
FIG. 2 is a timing chart showing the output timing of a clock signal output by an oscillator 101 and a frequency spreading circuit 102.
FIG. 3 is a diagram showing a waveform of an output clock in the circuit shown in FIG. 2;
FIG. 4 is a diagram illustrating signal output timing of an analog signal processing system performed in an image forming apparatus using frequency spreading.
FIG. 5 is a timing chart showing the output timing of an output signal when beat noise due to frequency spreading occurs.
FIG. 6 is an explanatory diagram illustrating an example of an output image obtained as a result of forming an image using read image data.
FIG. 7 is a block diagram illustrating an overall configuration of an image forming apparatus employing the clock generation unit according to the first embodiment of the present invention.
8 is a timing chart showing output timings of signals generated in the image forming apparatus shown in FIG.
FIG. 9 is a flowchart illustrating an operation procedure of the image forming apparatus illustrated in FIG. 7;
FIG. 10 is a block diagram illustrating a schematic configuration of an image forming apparatus according to a second embodiment of the present invention.
[Explanation of symbols]
401, 801 oscillator (oscillation means)
402 clock generator (frequency spreading means, control clock generating means)
403 Reference clock generator (reset means, reference signal generation means)
405, 807 CCD line sensor (image reading means)
409, 812 Correction memory (image correction means)
412, 813 correction data storage unit (storage means)
802 Frequency spreading circuit (frequency spreading means)
804 Drive / control clock generation circuit (control clock generation means)

Claims (8)

Oscillating means for oscillating a reference clock at a predetermined cycle;
Using the reference clock oscillated by said oscillation means to generate a clock signal of higher frequency than the frequency of the reference clock, the frequency of the clock signal is continuously changed at a predetermined period with respect to the frequency of the reference clock Frequency spreading means;
Reset means for resetting the continuous change of the frequency of the clock signal by the frequency spreading means at a predetermined timing,
Control clock generating means for generating a control clock based on the operation of the frequency spreading means and the reset means ,
Image reading means for reading image data based on the control clock,
Storage means for storing image data read by the image reading means in the correction data acquisition mode as correction reference data,
An image reading apparatus , comprising: image correction means for correcting image data read in the normal reading mode by the image reading means using the correction reference data stored in the storage means . Includes a reset signal generating means for generating a reset signal generated based on the reference clock,
2. The image reading apparatus according to claim 1, wherein the reset unit is configured to reset a continuous change in the frequency of the clock signal using a reset signal generated by the reset signal generation unit. . The image reading apparatus according to claim 1, wherein the reset by the reset unit is performed at a timing immediately after the image reading unit is turned on . 4. The image reading apparatus according to claim 1, wherein the reset by the reset unit is performed at each timing when reading of one line of image data is completed . A clock signal having a frequency higher than the frequency of the reference clock is generated by using a reference clock oscillated by an oscillating unit that oscillates the reference clock at a predetermined cycle, and the frequency of the clock signal is adjusted with respect to the frequency of the reference clock. A frequency spreading process that changes continuously at a fixed period;
A reset step of resetting a continuous change of the frequency of the clock signal by the frequency spreading step at a predetermined timing;
A control clock generation step of generating a control clock based on the processing of the frequency spreading step and the reset step;
A storage step of storing the image data read in the correction data acquisition mode by the image reading unit that reads the image data based on the control clock in the storage unit as correction reference data,
An image correction process for correcting image data read in a normal reading mode by the image reading unit using the correction reference data stored in the storage unit . Wherein the reset signal reset signal generated based on the reference clock, the control method of the image reading apparatus according to claim 5, wherein the resetting the continuous change of the frequency of the clock signal. 7. The method according to claim 5, wherein the reset by the reset process is performed at a timing immediately after the image reading unit is turned on . 8. The method according to claim 5, wherein the reset by the reset step is performed at each timing when reading of one line of image data is completed .

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