JP3596209B2 - Switch circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a switch circuit that handles high frequencies such as microwaves, and more particularly to a switch circuit that is suitable for use where high isolation is required or matching is required at the time of switch-off.
[0002]
[Prior art]
In recent years, FETs (field effect transistors) made of gallium arsenide (GaAs) have often been used as switching elements of switch circuits that handle high frequencies such as microwaves. In particular, MMIC (Monolithic Microwave Integrated Circuit) switches have been regarded as important because of the expectation of miniaturization, high performance, and low cost of circuits due to the integration.
[0003]
Even if the same switch IC is used, various circuit configurations are adopted depending on the required performance and functions. In general, an equivalent circuit of a GaAs FET for a switch can be simply represented as a resistor Ron connected to a series when turned on and a capacitance Coff connected to a series when turned off. As an example, the on-state resistance Ron is 2 Ωmm, and the off-state capacitance Coff is about 300 fF / mm.
[0004]
Recently, personal communications such as mobile phones have become popular, but the communication band in which they are used is almost 2 GHz or less. When relatively large isolation is required in such a frequency band and the OFF port is matched to 50Ω, for example, a switch circuit having a circuit configuration as shown in FIG. 6 is used.
[0005]
That is, in FIG. 6, between the first input / output terminal 61 and the second input / output terminal 62, the FET Q61 and the FET Q62 are connected in series. A shunt FET Q63 is connected between the common connection point of these FETs Q61 and Q62 and the ground, and a shunt FET Q64 is connected in series with the resistor R69 between the second input / output terminal 62 and the ground. Resistances R61 to R64 are connected to the gates of the FETs Q61 to Q64, respectively.
[0006]
Similarly, an FET Q65 and an FET Q66 are connected in series between the first input / output terminal 61 and the third input / output terminal 63. A shunt FET Q67 is connected between the common connection point of the FETs Q65 and Q66 and the ground, and a shunt FET Q68 is connected in series with the resistor R70 between the third input / output terminal 63 and the ground. Resistors R65 to R68 are connected to the gates of the FETs Q65 to Q68, respectively.
[0007]
In the circuit configuration described above, when the path between the first input / output terminal 61 and the second input / output terminal 62 is made conductive, the series FETs Q61, Q62 and the shunt FETs Q67, Q68 are turned on, and the shunt FETs Q63, Q64 and the series The FETs Q65 and Q66 are turned off. Since the series FETs Q61 and Q62 are on, there is no loss in this path, and since the shunt FETs Q63 and Q64 are off, there is little signal leakage from the path to ground. Therefore, the path between the first input / output terminal 61 and the second input / output terminal 62 becomes conductive.
[0008]
On the other hand, in the path between the first input / output terminal 61 and the third input / output terminal 63, since the series FETs Q65 and Q66 are turned off, the path itself is non-conductive, but the signal frequency increases. Accordingly, a signal leaks through the off-capacitance of the series FETs Q65 and Q66, and the isolation characteristics deteriorate. For this reason, the shunt FET Q67 is provided. When the shunt FET Q67 is turned on, a signal leaking from the series FET Q65 is pulled to the ground, and a large isolation can be secured. Further, the shunt FET Q68 in the ON state draws a signal leaked from the series FET Q66 to the ground, and improves isolation.
[0009]
Further, the impedance seen from the third input / output terminal 63 indicates that only the R70 (= 50Ω) can be seen approximately because the series FET Q66 in the off state cannot see the impedance inside the IC from the FET Q66. To 50Ω, and if the impedance of the transmission line is 50Ω, matching is achieved. As described above, the circuit shown in FIG. 6 can realize 50 Ω matching at the off-port and large isolation. FIG. 7 shows the isolation characteristics of this circuit. As is apparent from FIG. 7, the isolation at 2 GHz is as large as 66 dB.
[0010]
In the above circuit example, it is assumed that the mounting of the FET switch is ideal. However, actually, since various parasitic components are added, these cannot be ignored. For example, in a mobile phone terminal or the like, as the price of the terminal decreases, the cost of the IC used therein also needs to be reduced. For this reason, a ceramic package or the like having excellent high-frequency characteristics is not worth the cost, and an inexpensive plastic mold package is often used. In this case, the parasitic component that particularly affects the characteristics of the switch is an inductance component existing in a series between the signal terminal of the IC and the ground terminal and the outside of the IC. This is due to wires connecting the IC chip and the I / O pins of the package, pins of the package, and the like. For example, it becomes 1 nH or more with one wire.
[0011]
FIG. 8 shows a conventional example in which a common ground is used on a chip. In the figure, the same parts as those in FIG. 6 are denoted by the same reference numerals. Thus, when the ground is shared on the chip, the parasitic inductance Lb is interposed between the common ground on the chip and the ground outside the IC. FIG. 9 shows the isolation characteristics in this case. From FIG. 9, it can be seen that the isolation is greatly degraded by a small parasitic inductance. For example, the parasitic inductance Lb is 0.5 nH, and the isolation is deteriorated to 33 dB.
[0012]
This is because the common ground on the chip is not sufficient as the ground due to the presence of the parasitic inductance Lb between the common ground on the chip and the ground outside the IC. As an example, a case where a path between the first input / output terminal 61 and the second input / output terminal 62 becomes conductive will be described. At this time, a signal leaks from the ON-side shunt FETs Q63 and Q64 and the OFF-side shunt FET Q67 to the common ground on the chip. Since the common ground on the chip is not sufficient as the ground, the leaked signal leaks to the third input / output terminal 63 via the shunt FET Q68 in the ON state, thereby deteriorating the isolation. As described above, in the conventional example in which the ground is shared on the chip, it is difficult to obtain a large isolation.
[0013]
As a conventional example for preventing the deterioration of the isolation as described above, there is a circuit configuration shown in FIG. In this conventional example, the ground side of each of the shunt FETs Q63, Q64, Q67, Q68 is directly connected to an ideal ground via a parasitic inductance Lb. In practice, the ground side of each of the shunt FETs Q63, Q64, Q67, Q68 on the IC is directly connected to the I / O pins of the IC via a wire. It can be seen that the isolation characteristics in this case are greatly improved as is clear from FIG.
[0014]
As an example, when the parasitic inductance Lb is 0.5 nH, about 60 dB of isolation is obtained. However, in this case, ground I / O pins are required by the number of shunt FETs, so that the number of package pins increases, which leads to an increase in the size of the package. This is particularly inconvenient when miniaturization of the device is required, such as in a portable terminal.
[0015]
There is also a method in which the ground on the IC is made independent and connected to the die pad, which is the ground of the IC, with a wire. According to this method, the isolation is greatly improved, and the number of I / O pins of the IC package can be reduced. However, as can be seen from FIG. 9, the isolation is greatly degraded by the slight parasitic inductance Lb, and a certain degree of parasitic inductance intervenes between the die pad and the ideal ground outside the IC, although not as much as the wire. Is inevitable. As a result, very large isolation characteristics cannot be obtained.
[0016]
[Problems to be solved by the invention]
In a switch circuit used in the quasi-microwave band, as shown in FIG. 8, when the ground on the chip is shared, it is difficult to obtain a large isolation. In this case, the isolation can be improved by increasing the number of wires connecting the common ground and the die pad of the package. However, as can be seen from FIG. 9, a very large isolation cannot be obtained.
[0017]
Further, if the number of wires is increased, the inductance of the wires is reduced, and the isolation characteristics are considerably improved, but the number of pads for the wires on the chip is increased, thereby increasing the chip size and further increasing the cost. . Further, in the case of FIG. 10, the number of pins of the package increases, which leads to an increase in the size of the package. This is particularly inconvenient when miniaturization of the device is required, such as in a portable terminal. As described above, in the conventional technology, it has been difficult to realize high isolation, low cost, and downsizing of the device in the quasi-microwave band.
[0018]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a switch circuit having extremely large isolation characteristics even when an inexpensive plastic mold package is used.
[0019]
[Means for Solving the Problems]
A switch circuit according to the present invention is a switch circuit integrated on a chip, and is connected in series between at least first, second, and third input / output terminals and first and second input / output terminals. A first signal path including at least two switching elements, a second signal path including at least two switching elements connected in series between the first and third input / output terminals, and a first signal path. A first switching element connected between a second input / output terminal side end of the switching element connected to the first input / output terminal and a common ground on the chip, and a first signal path A second switching element connected between the second input / output terminal side end of the switching element connected to the second input / output terminal and the ground outside the chip; connected to scan the first input-output terminal of the A third switching element connected between the third common ground on the end of the output terminal side and the tip of the switching element, which is connected to the third input terminal of the second signal path in The fourth switching element is connected between the third input / output terminal side end of the switching element and the ground outside the chip .
[0020]
In the switch circuit having the above-described configuration, the ground sides of the first and third switching elements on the first input / output terminal side in the first and second signal paths are connected to a common ground on the chip. First, the wire length when connecting the ground side of the third switching element to the die pad can be set short, and the number of pins of the IC package can be reduced. On the other hand, by connecting the ground sides of the second and fourth switching elements on the second and third input / output terminals side in the first and second signal paths to the ground outside the chip , insufficient grounding is achieved. No signal wraparound.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention.
[0022]
In FIG. 1, an FET Q11 and an FET Q12 are connected in series in a first signal path 14 between a first input / output terminal 11 and a second input / output terminal 12. A shunt FET Q13 is connected between a common connection point of these FETs Q11 and Q12 and a common ground, and a shunt FET Q14 is connected in series with a matching resistor R19 between the second input / output terminal 12 and the ground outside the IC. It is connected. The parasitic inductance Lb is interposed between the resistor R19 and the common ground and the ground outside the IC. Resistances R11 to R14 are respectively connected to the gates of the FETs Q11 to Q14.
[0023]
Similarly, an FET Q15 and an FET Q16 are connected in series in a second signal path 15 between the first input / output terminal 11 and the third input / output terminal 13. A shunt FET Q17 is connected between the common connection point of these FETs Q15 and Q16 and a common ground, and a shunt FET Q18 is connected in series with the matching resistor R20 between the third input / output terminal 13 and the ground outside the IC. It is connected. Note that a parasitic inductance Lb is interposed between the resistor R20 and the ground outside the IC. Resistors R15 to R18 are connected to the gates of the FETs Q15 to Q18, respectively.
[0024]
In the configuration described above, for example, a junction FET made of gallium arsenide (GaAs) is used as the switching elements FETs Q11, Q12, Q15, Q16 and the shunt FETs Q13, Q14, Q17, Q18. These junction FETs are configured as MMICs together with the resistors R11 to R20 and the like.
[0025]
Here, in the first signal path 14, the series FET Q11 and the shunt FET Q13 form a pair, and the series FET Q12 and the shunt FET Q14 form a pair. Similarly, in the second signal path 15, the series FET Q15 and the shunt FET Q17 form a pair, and the series FET Q16 and the shunt FET Q18 form a pair.
[0026]
FIG. 2 is a conceptual diagram showing the mounting structure of the switch IC having the above-described configuration. In the drawing, the same parts as those in FIG. 2, a die pad 23 on which an IC chip 22 is mounted is mounted in an IC package 21, and the die pad 23 is connected to a ground outside the IC. The IC package 21 has, for example, two first and second ground terminals (pins) 24-1 and 24-2 connected to the ground outside the IC.
[0027]
The IC chip 22 has, for example, four first to fourth grounds 25-1 to 25-4. The first ground 25-1 is connected to the die pad 23 by a wire 26. The second ground 25-2 is connected to a first ground terminal 24-1 on the IC package 21 by a wire 27. The third ground 25-3 is connected to the die pad 23 by a wire 28. The fourth ground 25-4 is connected to a second ground terminal 24-2 on the IC package 21 by a wire 29.
[0028]
On the IC chip 22, the drain / source of the shunt FET Q13 on the first signal path 14 side is connected to the first ground 25-1. The drain / source of the shunt FET Q14 is connected to the second ground 25-2 via the resistor R19. Similarly, the drain / source of the shunt FET Q17 on the second signal path 15 side is connected to the third ground 25-3, and the drain / source of the shunt FET Q18 is connected to the fourth ground 25-4 via the resistor R20. It is connected.
[0029]
In the switch circuit according to this embodiment having the above configuration, when the first signal path 14 between the first input / output terminal 11 and the second input / output terminal 12 is made conductive, the series FETs Q11 and Q12 and the shunt FETs Q17 and Q18 Are turned on, and the shunt FETs Q13 and Q14 and the series FETs Q15 and Q16 are turned off. Since the series FETs Q11 and Q12 are on, there is no loss in the first signal path 14, and since the shunt FETs Q13 and Q14 are off, there is little signal leakage from the signal path to ground. Therefore, the path between the first input / output terminal 11 and the second input / output terminal 12 is in a conductive state.
[0030]
On the other hand, in the second signal path 15 between the first input / output terminal 11 and the third input / output terminal 13, since the series FETs Q15 and Q16 are turned off, this path itself is non-conductive. Here, when the signal frequency increases, the signal leaks via the off-capacitance of the series FETs Q15 and Q16. However, since the shunt FET Q17 is in the ON state, a signal leaking from the series FET Q15 is drawn to the ground through the series FET Q17, and a large isolation can be secured. Further, the shunt FET Q18 in the ON state draws a signal leaked from the FET Q16 to the ground, and has an action of improving isolation.
[0031]
As described above, in the first and second signal paths 14 and 15, the ground side of the shunt FETs Q13 and Q17 on the first input / output terminal 11 side is connected to the die pad 23 by the wires 26 and 28, so that the wire Since the lengths of 26 and 28 can be reduced, the parasitic inductance Lb can be reduced. As a result, it is possible to contribute to higher isolation. FIG. 3 shows the isolation characteristics. As is clear from this figure, it can be seen that a considerably large isolation has been achieved. For example, even when the parasitic inductance Lb of the wire is 0.5 nH, isolation of about 55 dB can be realized.
[0032]
The ground sides of the shunt FETs Q14 and Q18 on the second and third input / output terminals 12 and 13 are connected by wires 27 and 29 to the first and second ground terminals 24-1 and 24-2 on the IC package 21. , There is no insufficient signal wraparound from the ground, so that isolation is not degraded. In addition, since the ground side of all shunt FETs is not connected to the I / O pins of the IC package 21, the number of pins can be reduced and the IC package 21 can be downsized.
[0033]
In the above embodiment, the case where two pairs of the series FET and the shunt FET provided in each signal path are described, but a configuration in which three or more pairs are provided may be used. FIG. 4 is a circuit diagram when four pairs of a series FET and a shunt FET are provided. In this case, by connecting the ground sides of the series FETs of the three sets on the first input / output terminal 11 side to the common ground on the die pad, the same operation and effect as in the above embodiment can be obtained. The connection to the common ground does not necessarily have to be made for all three sets on the first input / output terminal 11 side, but may be made for at least one of the three sets.
[0034]
In the above embodiment, the first signal path 14 between the first input / output terminal 11 and the second input / output terminal 12, and the first input / output terminal 11 and the third Although the configuration has two second signal paths 15 between the input / output terminals 13, the present invention is not limited to this, and three or more signal paths starting from the first input / output terminals 11 are provided. It may be.
[0035]
By the way, generally, a negative power supply is required to drive a GaAs FET. Therefore, as shown in FIG. 5, capacitors C11, C12, C13, and C14 are provided between the shunt FETs Q13, Q14, Q17, and Q18 disposed between the signal paths 14 and 15 and the ground and the ground area. With this configuration, the switch IC can be separated in a DC manner, so that the GaAs FET can be controlled only by the positive power supply.
[0036]
【The invention's effect】
As described above, according to the present invention, the ground sides of the first and third switching elements on the first input / output terminal side in the first and second signal paths are connected to the common ground on the chip. On the other hand, the ground sides of the second and fourth switching elements on the second and third input / output terminal sides are connected to the ground outside the chip, so that the ground sides of the first and third switching elements are connected. Since the wire length when connecting to the die pad can be set short, the number of pins in the IC package can be reduced, and there is no insufficient signal sneak from the ground, so even if an inexpensive plastic mold package is used, A switch IC having a large isolation characteristic can be realized, and furthermore, it can greatly contribute to cost reduction and size reduction of the IC.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a conceptual diagram showing a mounting structure of a switch IC according to the present invention.
FIG. 3 is an isolation characteristic diagram according to the present invention.
FIG. 4 is a circuit diagram showing a modification of the present invention.
FIG. 5 is a circuit diagram showing another modified example of the present invention.
FIG. 6 is a circuit diagram for an ideal mounting.
FIG. 7 is an isolation characteristic diagram for an ideal mounting.
FIG. 8 is a circuit diagram showing a conventional example.
FIG. 9 is an isolation characteristic diagram according to a conventional example.
FIG. 10 is a circuit diagram showing another conventional example.
FIG. 11 is an isolation characteristic diagram according to another conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 1st input / output terminal 12 2nd input / output terminal 13 3rd input / output terminal 14 1st signal path 15 2nd signal path 21 IC package 22 IC chip 23 Die pad 26,27,28,29 Wire Lb Parasitic inductance Q11, Q12, Q15, Q16 Series FET
Q13, Q14, Q17, Q18 Shunt FET

Claims (5)

A switch circuit integrated on a chip ,
At least first, second, and third input / output terminals;
A first signal path including at least two switching elements connected in series between the first and second input / output terminals;
A second signal path including at least two switching elements connected in series between the first and third input / output terminals;
First connected between the common ground on the first of the said end portion of the second input-output terminal side of the switching element connected to said first input-output terminal of the signal path in the chip A switching element;
A second switching element connected between an end of the switching element connected to the second input / output terminal in the first signal path on the side of the second input / output terminal and a ground outside the chip; Element,
Third connected between a common ground on the second of the said third input-output terminal side of the end of the first switching elements connected to the input and output terminals of the signal paths in the chip A switching element;
Fourth switching connected between an end on the third input / output terminal side of a switching element connected to the third input / output terminal in the second signal path and ground outside the chip. A switch circuit comprising: an element; 2. The switching device according to claim 1, wherein each of the switching elements in the first and second signal paths and the first, second, third, and fourth switching elements comprises a gallium arsenide field effect transistor. Switch circuit. 3. The switch according to claim 2, wherein each of the switching elements in the first and second signal paths and the first, second, third and fourth switching elements are junction field effect transistors. circuit. 2. The switch circuit according to claim 1, wherein a matching resistor is provided between the second and fourth switching elements and a ground outside the chip . 3. The switch circuit according to claim 2, further comprising a capacitor between the first, second, third, and fourth switching elements and the common ground or a ground outside the chip .

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