JP3593822B2 - Intermediate frequency processing circuit - Google Patents

Description

【００５５】
そして、式（５）に示す掛算処理の結果が、図１に図示しないローパスフィルタを通過することにより、高周波成分 ｃｏｓ｛（Ｎω_ＳＣ＋ω_ＰＣ）ｔ＋ Ｎ ｍ ｓｉｎρｔ｝が減衰し、低周波成分 ｃｏｓ｛（Ｎω_ＳＣ−ω_ＰＣ）ｔ＋ Ｎ ｍ ｓｉｎρｔ｝のみが位相検出器２０に出力される。
即ち、位相検出器２０に入力される信号Ｓ_ｍ は次式のように表すことができる。
【００５６】
【数６】
Ｓ_Ｍ （ｔ） ＝ Ｃ ｃｏｓ ｛（Ｎω_ＳＣ −ω_ＰＣ）ｔ ＋ Ｎ ｍ ｓｉｎρｔ｝ …（６）
【００５７】
これにより、信号Ｓ_ｍ のＦＭ変調指数は元の音声中間周波信号ＳＩＦの変調指数のＮ倍となり、また、映像搬送波ＶＩＦ_Ｃ との掛算の結果、信号Ｓ_ｍ の搬送波の周波数ｆ_ｍ は（Ｎ ω_ＳＣ−ω_ＰＣ）ｔ となり、逓倍器１０の逓倍数Ｎを設定することにより、信号Ｓ_ｍ の搬送波周波数は、音声中間周波信号ＳＩＦの搬送波周波数（ｆ_ＳＩＦ ＝ω_ＳＣｔ）より低く変換することができる。
【００５８】
例えば、ここで、音声中間周波信号ＳＩＦの搬送波周波数は４．５ＭＨｚ、映像中間周波信号の搬送波周波数は５８．７５ＭＨｚ、逓倍器１０の逓倍数Ｎは１４とすると、ＰＬＬ回路の位相検出器２０に入力された信号の搬送波周波数は４．２５ＭＨｚとなる。
【００５９】
このように、音声中間周波信号ＳＩＦは上述した中間周波処理回路により、変調指数がＮ倍となり、また、音声中間周波信号の搬送波の周波数が低域に変換され、ＦＭ信号としての音声中間周波信号ＳＩＦの低域化を実現できる。
即ち、狹帯域のＦＭ変調信号である音声中間周波信号ＳＩＦを広帯域化することができる。そして、この広帯域化されたＦＭ変調信号を、例えば、本例のように、ＰＬＬ回路により構成されたＦＭ検波回路により復調することにより、高Ｓ／Ｎ比の音声信号が得られる。
【００６０】
次に、図１を参照しながら、数式を用いて、ＡＦＴ信号Ｖ_ＡＦＴ の生成動作について説明する。
掛算器ＭＵＬには、映像搬送波ＶＩＦ_Ｃ が入力され、この信号が逓倍器１０によりＮ逓倍した逓倍信号とともに掛算器ＭＵＬに入力され、掛算処理の結果、低域変換される。そして、低域変換された信号Ｓ_ｍ がＰＬＬ回路によりＦＭ検波され、信号Ｓ_ｍ の位相変化分に応じた信号Ｓ４０１がＰＬＬ回路により出力される。
【００６１】
信号Ｓ４０１はローパスフィルタ６０により、なかに含まれている音声信号Ｖ_ＭＰＸ の成分が除去され、映像搬送波ＶＩＦ_Ｃ の周波数変換に応じた信号成分のみが残される。そして、この信号が増幅器７０により増幅され、ＡＦＴ信号Ｖ_ＡＦＴ としてチューナー回路にフィードバックされ、チューナー回路の局部発振器の発振周波数を微調整することにより、チューナー回路により出力された中間周波信号の周波数を一定に保持させる。
【００６２】
ＰＬＬ回路において、電圧制御発振器５０の中心角周波数ｆ_ＶＣＯ は （Ｎ ω_ＳＣ−ω_ＰＣ） と設定する。このため、位相検出器２０に入力された信号Ｓ_ｍ に位相の変換がないとき、電圧制御発振器５０からの出力信号Ｓ５０は、次式により表される。
【００６３】
【数７】
Ｓ５０（ｔ） ＝ Ｖ ｃｏｓ（Ｎω_ＳＣ −ω_ＰＣ）ｔ …（７）
【００６４】
掛算器ＭＵＬに入力された映像搬送波ＶＩＦ_Ｃ の周波数には、Δωのずれがあるとすると、位相検出器２０に入力された信号Ｓ_ｍ は次式のように表せる。
【００６５】
【数８】
Ｓ_Ｍ （ｔ） ＝ Ｃｃｏｓ｛（Ｎω_ＳＣ −ω_ＰＣ ＋ Δω）ｔ ＋ Ｎ ｍ ｓｉｎρｔ｝ …（８）
【００６６】
信号Ｓ_ｍ はＰＬＬ回路により、ＦＭ検波され、ローパスフィルタ４０により出力された信号Ｓ４０１には、映像搬送波ＶＩＦ_Ｃ の周波数ずれΔωおよび音声信号成分 Ｎ ｍ ｓｉｎρｔに比例した電圧信号が含まれている。
図１に示すローパスフィルタ６０により、音声信号成分が除去され、映像搬送波ＶＩＦ_Ｃ の周波数ずれΔωに比例する電圧信号のみが残される。そして、この電圧信号が増幅器７０により増幅され、ＡＦＴ信号Ｖ_ＡＦＴ として、出力端子Ｔ_ＡＦＴ に出力される。
【００６７】
ＡＦＴ信号Ｖ_ＡＦＴ がチューナー回路に出力され、例えば、チューナー回路にある局部発振器の発振周波数を微調整することにより、チューナー回路から出力された中間周波信号の周波数を一定に保持する。
【００６８】
このように、本発明の中間周波処理回路により、映像搬送波ＶＩＦ_Ｃ の周波数ずれの量を検出して、ずれの量に応じて変化するＡＦＴ信号Ｖ_ＡＦＴ を発生し、チューナー回路にフィードバックすることにより、中間周波信号の周波数の安定化を図る。
【００６９】
一般的に、映像搬送波ＶＩＦ_Ｃ の周波数ずれを検出するための基準信号の周波数は映像搬送波ＶＩＦ_Ｃ の要求された周波数精度と同様若しくはそれ以上の精度が必要である。
本実施形態においては、映像搬送波ＶＩＦ_Ｃ の周波数は、掛算器ＭＵＬにより、低域に変換され、位相比較の基準信号として用いられる電圧制御発振器５０の発振信号Ｓ５０の中心周波数ｆ_ＶＣＯ は（Ｎ ω_ＳＣ−ω_ＰＣ） であるため、電圧制御発振器５０に要求される精度と従来の基準信号発生器に要求される精度比ｘは、次式のように表すことができる。
【００７０】
【数９】
ｘ ＝ ω_ＰＣ／（Ｎ ω_ＳＣ−ω_ＰＣ） …（９）
【００７１】
ここで、本実施形態において、逓倍器の逓倍数Ｎは（Ｎ＝１４）とすると、電圧制御発振器５０の中心周波数ｆ_ＶＣＯ は（ｆ_ＶＣＯ ＝４．２５ＭＨｚ）となる。式（９）に示す精度比ｘは約１３．８倍である。また、逓倍数（Ｎ＝１６）とすると、電圧制御発振器５０の中心周波数ｆ_ＶＣＯ は（ｆ_ＶＣＯ ＝１３．２５ＭＨｚ）となり、式（９）に示す精度比ｘは約４．４３倍である。
【００７２】
即ち、本実施形態において、映像搬送波ＶＩＦ_Ｃ が掛算器ＭＵＬにより低域に変換することにより、基準信号を発生する電圧制御発振器５０に対する精度要求は従来のＡＦＴ信号生成回路の基準信号発生器と比べて、緩和される。
【００７３】
以上説明したように、本実施形態によれば、音声中間周波信号ＳＩＦを逓倍器１０によりＮ逓倍し、映像搬送波ＶＩＦ_Ｃ と掛算して、低域に変換した信号Ｓ_ｍ をＰＬＬ回路に入力される。ＰＬＬ回路により、信号Ｓ_ｍ をＦＭ検波して、音声信号および映像搬送波ＶＩＦ_Ｃ の周波数ずれに応じた信号Ｓ４０１を発生し、キャパシタＣ_１ により、直流成分が除去され、さらに増幅器９０により増幅された音声信号Ｖ_ＭＰＸ を出力し、また、ローパスフィルタ６０により、音声信号成分が除去され、映像搬送波ＶＩＦ_Ｃ の周波数ずれ分に比例した信号のみを出力し、増幅器７０により増幅して、ＡＦＴ信号Ｖ_ＡＦＴ としてチューナー回路にフィードバックするので、音声信号のＳ／Ｎ比の向上を実現でき、位相比較の基準信号を発生する電圧制御発振器５０に対する精度の要求を緩和でき、一つの中間周波処理回路により、音声検波およびＡＦＴ信号Ｖ_ＡＦＴ の発生を実現できる。
【００７４】
第２実施形態
図２は本発明に係る中間周波処理回路の第２の実施形態を示す回路図である。図示のように、本実施形態の中間周波処理回路は、逓倍器１０、発振器１２、掛算器ＭＵＬ、位相検出器２０、増幅器３０、ローパスフィルタ４０、電圧制御発振器５０、ローパスフィルタ６０、キャパシタＣ_１ および増幅器８０，９０により構成されている。
【００７５】
なお、本実施形態と図１に示す第１の実施形態と比べると、掛算器ＭＵＬに入力された映像搬送波ＶＩＦ_Ｃ の代わりに、本実施形態では、発振器１２からの発振信号Ｓ１２を用いることで異なる。
ＰＬＬ回路を構成する各部分は第１の実施形態と同様であり、ここで、これらの構成部分を図１と同様な符号を用いて表記している。なお、図１と同様な構成部分についてはその詳細の説明を省略する。
【００７６】
図２に示すように、本例では、音声中間周波信号ＳＩＦを逓倍器１０によりＮ逓倍した逓倍信号Ｓ１０と発振器１２により発生された発振信号Ｓ１２がともに掛算器ＭＵＬに入力される。掛算器ＭＵＬにより掛算処理した結果を図示しないローパスフィルタを介して、高周波成分が除去され、低周波成分のみが残された信号Ｓ_ｍ１がＰＬＬ回路を構成する位相検出器２０に入力される。
【００７７】
ここで、発振器１２の出力信号Ｓ１２は、例えば、映像搬送波ＶＩＦ_Ｃ と同様な周波数を有する発振信号である。なお、この発振器は、例えば、セラミック発振器などにより構成することができる。
逓倍信号Ｓ１０と発振信号Ｓ１２との掛算処理の結果、音声中間周波信号ＳＩＦの変調指数が逓倍数Ｎ倍となり、また、ＦＭ信号である音声中間周波信号ＳＩＦの搬送波周波数が低域に変換されるので、ＰＬＬ回路で構成されたＦＭ検波回路により、高Ｓ／Ｎ比の音声信号Ｖ_ＭＰＸ が得られる。
【００７８】
以上説明したように、本実施形態によれば、ＡＦＴ信号Ｖ_ＡＦＴ の発生を実現できないが、音声中間周波信号ＳＩＦを逓倍して、発振信号Ｓ１２との掛算処理により、音声中間周波信号ＳＩＦの変調指数の向上および搬送波周波数の低域変換を実現でき、高Ｓ／Ｎ比の音声信号が得られる。
【００７９】
第３実施形態
図３は本発明に係る中間周波処理回路の第３の実施形態を示す回路図である。
図示のように、本実施形態の中間周波処理回路は、発振器１４、掛算器ＭＵＬ、位相検出器２０、増幅器３０、ローパスフィルタ４０、電圧制御発振器５０および増幅器７０により構成されている。
【００８０】
なお、本実施形態と図１に示す第１の実施形態と比べると、掛算器ＭＵＬに入力された逓倍信号Ｓ１０の代わりに、本実施形態では、発振器１４からの発振信号Ｓ１４を用いることで異なる。
ＰＬＬ回路を構成する各部分は第１の実施形態と同様であり、ここで、これらの構成部分を図１と同様な符号を用いて表記している。なお、図１と同様な構成部分についてはその詳細の説明を省略する。
【００８１】
図３に示すように、本例では、発振器１４からの発振信号Ｓ１４と映像搬送波ＶＩＦ_Ｃ がともに掛算器ＭＵＬに入力される。掛算器ＭＵＬにより掛算処理した結果を図示しないローパスフィルタを介して、高周波成分が除去され、低周波成分のみが残された信号Ｓ_ｍ２がＰＬＬ回路を構成する位相検出器２０に入力される。
【００８２】
ＰＬＬ回路に入力された信号Ｓ_ｍ２の周波数は、映像搬送波ＶＩＦ_Ｃ の周波数ずれに応じて変化するので、ＰＬＬ回路により、映像搬送波ＶＩＦ_Ｃ の周波数ずれに比例する電圧信号Ｓ４０が出力される。電圧信号Ｓ４０が増幅器７０により増幅され、ＡＦＴ信号Ｖ_ＡＦＴ としてチューナー回路にフィードバックされ、チューナー回路の局部発振器の発振周波数を微調整することにより、チューナー回路から出力される中間周波信号の周波数を一定に保持される。
【００８３】
なお、本例において、発振器１４は、例えば、セラミック発振器などにより構成することができる。発振器１４の動作周波数は、例えば、図１に示す逓倍器１０からの逓倍信号Ｓ１０と略同様な周波数に設定されている。ここで、発振器１４からの発振信号Ｓ１４の角周波数をω_ＯＳＣ とすると、位相検出器２０に入力される信号Ｓ_ｍ２の角周波数は、掛算器ＭＵＬに入力された二つの信号の角周波数の差（ω_ＰＣ−ω_ＯＳＣ ）となる。また、これに応じて、ＰＬＬ回路の電圧制御発振器５０の中心周波数ｆ_ＶＣＯ は（ω_ＰＣ−ω_ＯＳＣ ）に設定される。
【００８４】
このように、映像搬送波ＶＩＦ_Ｃ の周波数が低域に変換され、ＡＦＴ信号Ｖ_ＡＦＴ を発生するための基準信号として、電圧制御発振器５０からの発振信号Ｓ５０が用いられる。このため、電圧制御発振器５０に対する精度の要求は、従来の基準信号発生器に要求される精度に比べて緩和される。
【００８５】
以上説明したように、本実施形態によれば、発振器１４からの発振信号Ｓ１４と映像搬送波ＶＩＦ_Ｃ との掛算処理により、映像搬送波ＶＩＦ_Ｃ の周波数を低域に変換し、ＰＬＬ回路により、映像搬送波ＶＩＦ_Ｃ の周波数ずれに比例した電圧信号を検波して出力し、ＡＦＴ信号Ｖ_ＡＦＴ としてチューナー回路にフィードバックするので、映像搬送波ＶＩＦ_Ｃ 周波数の低域変換により、位相比較の基準信号を発生する電圧制御発振器５０の精度に対する要求を緩和でき、高精度なＡＦＴ信号Ｖ_ＡＦＴ を発生できる。
【００８６】
【発明の効果】
以上説明したように、本発明の中間周波処理回路によれば、復調された音声信号のＳ／Ｎ比の向上を実現でき、ＡＦＴ信号を発生するための基準信号発生器の精度に対する要求が緩和できる利点がある。
さらに、本発明によれば、一つの回路により、音声信号の復調とＡＦＴ信号の発生を実現でき、回路構成の簡単化を実現できる。
【図面の簡単な説明】
【図１】本発明に係る中間周波処理回路の第１の実施形態を示す回路図である。
【図２】本発明に係る中間周波処理回路の第２の実施形態を示す回路図である。
【図３】本発明に係る中間周波処理回路の第３の実施形態を示す回路図である。
【図４】インターキャリア方式の中間周波処理回路のブロック図である。
【図５】擬似スプリットキャリア方式の中間周波処理回路のブロック図である。
【図６】従来の音声信号復調回路の一例を示すブロック図である。
【図７】音声信号復調回路に用いる単同調回路の一例を示す回路図である。
【図８】単同調回路の振幅および位相特性を示すグラフである。
【図９】従来のＡＦＴ回路の一例を示すブロック図である。
【図１０】π／２移相器の一例を示す回路図である。
【図１１】π／２移相器の周波数特性を示すグラフである。
【図１２】ＡＦＴ回路の出力特性を示すグラフである。
【符号の説明】
１０…逓倍器、１２，１４…発振器、ＭＵＬ…掛算器、２０…位相検出器、３０…増幅器、４０…ローパスフィルタ、５０…電圧制御発振器、６０…ローパスフィルタ、Ｃ_１ …キャパシタ、７０，８０，９０…増幅器。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an intermediate frequency processing circuit for video and audio signals used for, for example, a television receiver.
[0002]
[Prior art]
In a television receiver or the like, a desired channel signal is selected by a tuner circuit (tuning circuit) from a VHF or UHF band television high frequency signal received by a receiving antenna. For example, in Japan, the video signal is 58.75 MHz. The audio signal is converted into an intermediate frequency signal of 54.25 MHz to obtain an intermediate frequency signal. Generally, an intermediate frequency signal from a tuner circuit includes both a video signal and an audio signal. The video and audio intermediate frequency signals are separated from the composite intermediate frequency signal, amplified by a video intermediate amplifier circuit and an audio intermediate amplifier circuit, and input to a video and audio detection circuit, respectively.
[0003]
For this reason, a separating circuit for separating the video signal and the audio signal from the composite intermediate frequency signal from the tuner circuit is provided at the next stage of the tuner circuit. As such a circuit, a circuit of the inter-carrier system shown in FIG. 4 and a circuit of the pseudo split carrier system shown in FIG. 5 are used.
[0004]
The intermediary audio intermediate frequency detection circuit shown in FIG.₁, Video carrier reproduction circuit VCG₁, Multiplier MUL₁And bandpass filter BPF₂It consists of:
Bandpass filter BPF₁Is set wide so that both an audio signal having an intermediate frequency of 54.25 MHz and a video signal having an intermediate frequency of 58.75 MHz can pass through. On the other hand, the bandpass filter BPF₂The center frequency is 4.5 MHz which is the difference between the video intermediate frequency 58.75 MHz and the audio intermediate frequency 54.25 MHz, and the bandwidth is set to, for example, 50 KHz in consideration of the case of audio multiplex broadcasting. I have.
[0005]
Video carrier reproduction circuit VCG₁ Is a carrier VIF of the video signal according to the intermediate frequency signal of the input video signal._C And the multiplier MUL₁ Output to
Multiplier MUL₁ Is the input video carrier VIF_C And the video intermediate frequency signal are multiplied and output. And the multiplier MUL₁ High-frequency component through a low-pass filter (not shown)ButRemoved and the video signal V_P Only output.
[0006]
On the other hand, the multiplier MUL₁Output of the band pass filter BPF₂, Frequency components other than the audio intermediate frequency signal are removed, and are output to the audio signal demodulation circuit as an audio intermediate frequency signal SIF.
Note that the audio intermediate frequency signal SIF is an FM signal, and the audio signal demodulation circuit includes, for example, an FM detection circuit.
[0007]
In the inter-carrier type circuit having such a configuration, the band-pass filter BPF₁Composite intermediate frequency signal VIF input to_SIs a bandpass filter BPF₁As a result, components other than the video and audio intermediate frequency signals are removed, and the intermediate frequency signal VIF_BIs output as
[0008]
Intermediate frequency signal VIF_BIs a video carrier reproduction circuit VCG₁Is a video carrier VIF having a frequency of 58.75 MHz._CIs generated. Video carrier VIF_CAnd intermediate frequency signal VIF_BAre both multipliers MUL₁Is input to the multiplier MUL₁As a result, a video signal and a signal including a high frequency component having a frequency twice as high as the video intermediate frequency 58.75 MHz are generated. Then, a high-frequency component is removed by a low-pass filter not shown in FIG._POnly output.
[0009]
On the other hand, the multiplier MUL₁Output signal contains a 4.5 MHz audio intermediate signal, which is the difference between the 58.75 MHz video intermediate frequency and the 54.25 MHz audio intermediate frequency, so that the multiplier MUL₁Output signal is a band pass filter BPF having a center frequency of 4.5 MHz₂, Other components are removed, and only the audio intermediate frequency signal SIF having a center frequency of 4.5 MHz is output.
[0010]
FIG. 5 is a circuit diagram showing a pseudo split carrier type separation circuit. As shown, this circuit comprises a bandpass filter BPF₃, BPF₄, Video carrier reproduction circuit VCG₂, Multiplier MUL₂, MUL₃It consists of.
[0011]
Bandpass filter BPF₃Of the band pass filter BPF shown in FIG.₁Is the same as Bandpass filter BPF₃From the video intermediate frequency signal VIF_BIs output.
Also, a bandpass filter BPF₄Is a narrow band-pass filter having a center frequency of 54.25 MHz and a bandwidth of, for example, about 50 KHz in consideration of the case of audio multiplex broadcasting. Therefore, the band-pass filter BPF₄From, the frequency is 54.25 MHz audio intermediate frequency signal SIF_BIs output.
[0012]
Video carrier reproduction circuit VCG₂Is a video carrier reproduction circuit VCG shown in FIG.₁Has substantially the same configuration and function as that of the first embodiment, except that the video carrier reproducing circuit VCG₂Video carrier VIF generated by_CIs the multiplier MUL₂, MUL₃Is output to both.
[0013]
Multiplier MUL₂Is a video carrier reproduction circuit VCG₁Video carrier VIF generated by_CAnd video intermediate frequency signal VIF_BThen, these signals are multiplied to output a signal including a video signal and a high-frequency component. The output signal is filtered by a low-pass filter (not shown) to remove the high-frequency component, and_POnly output.
[0014]
Multiplier MUL₃Is a video carrier reproduction circuit VCG₂Video carrier VIF generated by_CAnd audio intermediate frequency signal SIF_BIn response, a signal containing a frequency component corresponding to the difference between the frequencies of these signals and the sum of the frequencies is output. Then, a high-frequency component is removed by a low-pass filter (not shown), and only a 4.5 MHz audio intermediate frequency signal SIF is output.
[0015]
The audio intermediate frequency signal SIF obtained as described above is an FM signal having a center frequency of 4.5 MHz, and is demodulated by the audio signal demodulation circuit shown in FIG._MPXIs output.
[0016]
As shown in FIG. 6, the audio signal demodulation circuit includes a π / 2 phase shifter PSF._S, Single tuning circuit TC and multiplier MUL_SIt consists of.
π / 2 phase shifter PSF_SIs a circuit for rotating the phase of the input audio intermediate frequency signal SIF by π / 2. As shown in FIG. 7, the single tuning circuit TC is a tuning circuit that includes a capacitor C and a coil L and tunes to the center frequency of the audio intermediate frequency signal SIF of 4.5 MHz.
[0017]
FIG. 8 is a graph showing the amplitude and phase characteristics of the single tuning circuit TC. In FIG. 8, the frequency f_S0Is the center frequency of the audio intermediate frequency signal SIF, 4.5 MHz.
[0018]
π / 2 phase shifter PSF_SThe audio intermediate frequency signal passed through the single tuning circuit TC and the original audio intermediate frequency signal SIF are both multiplied by a multiplier MUL._SIs entered. As a result of the multiplication process, the audio signal V_MPXAnd a signal containing other high-frequency components. The high-frequency component is removed by a low-pass filter (not shown), and the audio signal V_MPXOnly output.
[0019]
Thus, the audio intermediate frequency signal SIF is FM-demodulated by the audio signal demodulation circuit, and the audio signal V_MPXIs obtained.
[0020]
Further, the video carrier VIF obtained from the video signal and audio signal separation circuits shown in FIGS._CAnd an AFT (Automatic Fine Tuning) circuit shown in FIG._AFTIs generated.
[0021]
As shown in FIG. 9, the AFT circuit is a π / 2 phase shifter PSF._AAnd multiplier MUL_AIt consists of.
π / 2 phase shifter PSF_AAn example is shown in FIG. As shown in FIG. 10, the π / 2 phase shifter PSF of this example_AIs the output node ND₁And ND₂External coil L connected between_AAnd capacitor C_AAnd using this as a reference, the input video carrier VIF_CIs detected. Video carrier VIF_CMultiplied by an oscillation signal having a phase change corresponding to the amount of frequency shift of_AOutput to
FIG. 11 shows this π / 2 phase shifter PSF._A5 is a graph showing frequency characteristics of the sigma.
[0022]
Multiplier MUL_AIs the phase-changed video carrier VIF_CAnd original video carrier VIF_C, And multiplies the image carrier VIF by a low-pass filter (not shown)._CSignal V corresponding to the frequency shift of_AFTTo occur.
FIG. 12 shows the output characteristics of the AFT circuit. In FIGS. 11 and 12, the frequency f_V0Is the center frequency of the video intermediate frequency signal, 58.75 MHz.
[0023]
With the AFT circuit thus configured, the video carrier VIF_CAFT signal V according to the change of the frequency of_AFTIs generated and fed back to the tuner circuit to finely adjust the oscillation frequency of the local oscillation circuit in the tuner circuit, thereby keeping the frequency of the intermediate frequency signal output from the tuner circuit constant.
For this reason, the AFT circuit is required to have high sensitivity and operational stability, and is required to have a high accuracy capable of suppressing an error including temperature characteristics to within 0.05%.
[0024]
[Problems to be solved by the invention]
By the way, in the conventional video and audio intermediate frequency processing circuit described above, since an external coil is used, it is necessary to adjust the coil. In the AFT circuit, high accuracy is required. Is difficult to adjust.
The audio intermediate frequency signal SIF is a narrow-band FM signal, and it is difficult to obtain a high S / N ratio equivalent to that of a coil in order to incorporate an audio demodulation circuit in an IC.
[0025]
Furthermore, in the above-mentioned conventional intermediate frequency processing circuit, the demodulation circuit of the audio intermediate frequency signal SIF and the AFT circuit require separate circuits, and there is a problem that the circuit configuration becomes complicated.
[0026]
The present invention has been made in view of such circumstances, and has as its object to simplify the circuit configuration, to increase the modulation index of the audio signal by frequency multiplication and frequency conversion, and to improve the S of the demodulated audio signal. An object of the present invention is to provide an intermediate frequency processing circuit capable of improving the / N ratio and relaxing the accuracy of the reference frequency of the AFT circuit.
[0027]
[Means for Solving the Problems]
To achieve the above object, the present invention is an intermediate frequency processing circuit for demodulating an audio signal from an audio intermediate frequency signal and outputting the demodulated audio signal, wherein the audio intermediate frequency signal is multiplied by a predetermined number N (N is an integer). Multiplying means for outputting a multiplied signal,An input having the frequency of the carrier of the video intermediate frequency signalA frequency conversion unit for multiplying the output signal by a signal and removing a high-frequency component included in the multiplication result; and a demodulation unit for receiving an output signal of the frequency conversion unit and demodulating an audio signal included in the output signal. .
[0028]
In the present invention, preferably,inputThe signal is a carrier of the video intermediate frequency signal from the tuning circuit, and the demodulation means is constituted by a PLL circuit.
[0029]
Further, in the present invention, the video intermediate frequency signal from the tuning circuit is received, and a control signal corresponding to the frequency change of the carrier of the video intermediate frequency signal is output to the tuning circuit, and the output frequency of the tuning circuit is stabilized. An intermediate frequency processing circuit for controlling the carrier of the video intermediate frequency signal.An input having a frequency obtained by multiplying the audio intermediate frequency signal by a predetermined multiple N (N is an integer)Frequency conversion means for multiplying the signal and the high frequency component included in the multiplication result, receiving the output signal of the frequency conversion means, and converting the frequency change of the video intermediate frequency signal included in the output signal into Demodulating means for extracting a corresponding signal, outputting the extracted signal to the tuning circuit, and controlling an output frequency of the tuning circuit.
[0030]
Furthermore, in the present invention, preferably,inputThe signal is, DepartureThis is an oscillation signal from the vibrator.
[0031]
According to the present invention, a multiplied signal obtained by multiplying an audio intermediate frequency signal from a tuning circuit, for example, a tuner circuit by N, is output by a multiplying unit, and further, the multiplied signal and a video intermediate signal from the tuner circuit are output by a frequency converting unit. The frequency signal is multiplied, a high-frequency component of the multiplication result is removed, and a signal whose frequency is converted to a low frequency is output.
[0032]
The frequency-converted signal is demodulated by, for example, a demodulation circuit including a PLL circuit, and an audio signal is output. Also, the output signal of the demodulation circuit is removed through a low-pass filter that removes the audio signal, whereby the audio signal component is removed, and a signal corresponding to the frequency change of the carrier of the video intermediate frequency signal is obtained. The amplified signal is supplied to the tuner circuit as an AFT signal for stabilizing the output frequency of the tuner circuit.
[0033]
As described above, the frequency is multiplied by the frequency multiplying means, and the frequency is converted by the frequency converting means, so that the bandwidth of the audio intermediate frequency signal, which is a narrow-band FM signal, can be widened, and the modulation index of the audio intermediate frequency signal can be improved. An audio signal with a high S / N ratio is obtained.
Further, according to the present invention, demodulation of an audio signal and output of an AFT signal can be realized by one circuit, and the circuit configuration is simplified.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
First embodiment
FIG. 1 is a circuit diagram showing a first embodiment of the intermediate frequency processing circuit according to the present invention. As shown in the figure, the intermediate frequency processing circuit of the present example includes a multiplier 10, a multiplier MUL, a phase detector 20, an amplifier 30, a low-pass filter 40, a voltage controlled oscillator (VCO) 50, a low-pass filter 60, and a capacitor C.₁And amplifiers 70, 80 and 90.
[0035]
A PLL circuit is constituted by the phase detector 20, the amplifier 30, the low-pass filter 40, and the voltage-controlled oscillator 50.
The multiplier 10 receives the input audio intermediate frequency signal SIF, generates a multiplied signal S10 multiplied by a preset multiplying factor N, and outputs it to the multiplier MUL.
[0036]
The multiplier MUL includes a multiplied signal S10 from the multiplier 10 and a video carrier VIF._CIn response to this, a multiplication process is performed using these signals, and the processing result is output through a low-pass filter (not shown) to the oscillation signal S._mTo the phase detector 20.
[0037]
The phase detector 20 receives the oscillation signal S from the multiplier MUL._mAnd receives the oscillation signal S50 from the voltage controlled oscillator 50, compares the phases of these signals, and outputs a phase difference signal S20 corresponding to the phase difference to the amplifier 30.
The phase difference signal S20 is amplified by the amplifier 30, and is output to the low-pass filter 40 as the amplified signal S30.
[0038]
The low-pass filter 40 removes high-frequency components included in the amplified signal S30 from the amplifier 30, generates and outputs signals S401 and S402 including only low-frequency components.
[0039]
Voltage-controlled oscillator 50 receives signal S402 from low-pass filter 40, and controls the frequency of oscillation signal S50 accordingly. The oscillation signal S50 is fed back to the phase detector 20.
[0040]
On the other hand, the signal S401 from the low-pass filter 40 further passes through the low-pass filter 60, where the audio signal component is removed, amplified by the amplifier 70, and the AFT signal V_AFTOutput terminal T_AFTIs output to
The signal S401 from the low-pass filter 40 is amplified via the amplifier 80,₁, A DC component and a frequency component close to DC, for example, a video carrier VIF_CThe low-frequency component corresponding to the change in the frequency is cut and amplified by the amplifier 90._MPXOutput terminal T_MPXIs output to
[0041]
In this embodiment, a PLL circuit including the phase detector 20, the amplifier 30, the low-pass filter, and the voltage controlled oscillator 50 is used for FM detection of the audio intermediate frequency signal.
[0042]
For example, the center frequency f of the voltage controlled oscillator 50_VCOIs the oscillation signal S from the multiplier MUL._mCarrier frequency. Thereby, the oscillation signal S from the multiplier MUL is obtained._mA signal S20 whose voltage fluctuates according to the phase change is generated, the signal S20 is amplified by the amplifier 30, the high-frequency component is removed by the low-pass filter 40, and the signals S401 and S402 including only the low-frequency component are output. You.
[0043]
The signal S401 from the low-pass filter 40 is input to the voltage controlled oscillator 50, and the frequency of the oscillation signal S50 generated by the voltage controlled oscillator 50 is controlled accordingly.
For example, the oscillation signal S from the multiplier MUL_mDoes not change, the output signal S20 from the phase detector 20 is maintained at a constant level, and the level of the output signal S402 of the low-pass filter 40 is also maintained at a constant level. Therefore, the frequency of the oscillation signal S50 generated by the voltage controlled oscillator 50 becomes the center frequency f_VCOIs held in.
[0044]
On the other hand, the oscillation signal S from the multiplier MUL_mWhen the phase changes, a signal corresponding to the phase change is generated, a signal indicating this phase change is amplified by the amplifier 30, and the high-frequency component is removed via the low-pass filter 40, leaving only the low-frequency component. It is. The signal S402 is input to the voltage controlled oscillator 50, and the voltage controlled oscillator 50 controls the frequency of the generated oscillation signal according to the signal.
[0045]
As described above, the output signal of the low-pass filter 40 includes the oscillation signal S from the multiplier MUL._mChanges in accordance with the phase change of. This phase change is, for example, an audio signal that is a modulation signal of the audio intermediate frequency signal SIF or the video carrier signal VIF input to the multiplier MUL._CFrom the output signal S401 of the low-pass filter 40, the audio signal V_MPXAnd AFT signal V_AFTCan be taken out.
[0046]
Hereinafter, the operation of the present embodiment will be described using mathematical expressions with reference to FIG.
The audio intermediate frequency signal SIF input to the multiplier 10 is an FM signal, and can be expressed by the following equation.
[0047]
(Equation 1)
SIF (t) = Acos ｛ω_SCt + φ₀+ M sin ρt… (1)
Where ω_SCDenotes the angular frequency of the carrier of the audio intermediate frequency signal SIF, ρ denotes the angular frequency of the audio modulation wave, and m denotes the modulation index.
Note that φ in equation (1)₀Is the initial value of the phase of the FM signal, where, for convenience, φ₀= 0. In this case, the above equation (1) can be simplified as the following equation.
[0048]
(Equation 2)
SIF (t) = Acos ｛ω_SCt + m sin ρt｝ (2)
[0049]
When the signal SIF (t) shown in the equation (2) is input to the multiplier 10 and multiplied by N, a multiplied signal S10 shown in the following equation is obtained.
[0050]
(Equation 3)
S10 (t) = Acos ｛Nω_SCt + Nm sin ρt｝ (3)
[0051]
Here, the video carrier VIF input to the multiplier MUL is used._CIs the carrier angular frequency ω as shown in the following equation._PCAn oscillation signal having
[0052]
(Equation 4)
VIF_C(T) = B cos ω_PCt ... (4)
[0053]
Video carrier VIF by multiplier MUL_CAnd a multiplication signal S10 to obtain a multiplication signal shown below.
[0054]
(Equation 5)

[0055]
Then, the result of the multiplication processing shown in Expression (5) passes through a low-pass filter not shown in FIG._SC+ Ω_PC) T + Nm sinρt｝ is attenuated, and the low frequency component cos ｛(Nω_SC−ω_PC) Only t + Nm sinρt} is output to the phase detector 20.
That is, the signal S input to the phase detector 20_mCan be expressed as:
[0056]
(Equation 6)
S_M(T) = C cos ｛(Nω_SC  −ω_PC) T + Nm sinρt｝ (6)
[0057]
Thereby, the signal S_mIs N times the modulation index of the original audio intermediate frequency signal SIF, and the video carrier VIF_CAnd the signal S_mCarrier frequency f_mIs (N ω_SC−ω_PC) T, and by setting the multiplication number N of the multiplier 10, the signal S_mIs the carrier frequency of the audio intermediate frequency signal SIF (f_SIF= Ω_SCt).
[0058]
For example, if the carrier frequency of the audio intermediate frequency signal SIF is 4.5 MHz, the carrier frequency of the video intermediate frequency signal is 58.75 MHz, and the multiplication number N of the multiplier 10 is 14, the phase detector 20 of the PLL circuit The carrier frequency of the input signal is 4.25 MHz.
[0059]
As described above, the audio intermediate frequency signal SIF has a modulation index N times higher by the above-described intermediate frequency processing circuit, and the frequency of the carrier of the audio intermediate frequency signal is converted to a low frequency band. It is possible to realize a low-pass SIF.
That is, the audio intermediate frequency signal SIF, which is a narrow-band FM modulation signal, can be broadened. Then, by demodulating the broadband FM modulated signal by, for example, an FM detection circuit constituted by a PLL circuit as in the present example, an audio signal having a high S / N ratio can be obtained.
[0060]
Next, referring to FIG. 1, the AFT signal V_AFTWill be described.
The multiplier MUL has a video carrier VIF_CIs input to the multiplier MUL together with the multiplied signal multiplied by N by the multiplier 10, and as a result of the multiplication process, the low-frequency conversion is performed. Then, the low-frequency converted signal S_mIs FM detected by the PLL circuit, and the signal S_mThe signal S401 corresponding to the phase change is output by the PLL circuit.
[0061]
The signal S401 is converted by the low-pass filter 60 into the audio signal V contained therein._MPXOf the image carrier VIF_C, Only the signal components corresponding to the frequency conversion are left. This signal is amplified by the amplifier 70, and the AFT signal V_AFTThe frequency of the intermediate frequency signal output from the tuner circuit is held constant by finely adjusting the oscillation frequency of the local oscillator of the tuner circuit.
[0062]
In the PLL circuit, the central angular frequency f of the voltage controlled oscillator 50_VCOIs (N ω_SC−ω_PC). Therefore, the signal S input to the phase detector 20_mWhen there is no phase conversion, the output signal S50 from the voltage controlled oscillator 50 is represented by the following equation.
[0063]
(Equation 7)
S50 (t) = V cos (Nω_SC  −ω_PC) T ... (7)
[0064]
Video carrier VIF input to multiplier MUL_C, There is a shift of Δω, the signal S input to the phase detector 20 is_mCan be expressed as
[0065]
(Equation 8)
S_M(T) = Ccos ｛(Nω_SC  −ω_PC  + Δω) t + Nm sinρt｝ (8)
[0066]
Signal S_mThe signal S401 output from the low-pass filter 40 by the FM detection by the PLL circuit includes the video carrier VIF_CAnd a voltage signal proportional to the audio signal component N m sinspt.
The audio signal component is removed by the low-pass filter 60 shown in FIG._C, Only the voltage signal proportional to the frequency shift Δω is left. This voltage signal is amplified by the amplifier 70, and the AFT signal V_AFTOutput terminal T_AFTIs output to
[0067]
AFT signal V_AFTIs output to the tuner circuit. For example, by finely adjusting the oscillation frequency of the local oscillator in the tuner circuit, the frequency of the intermediate frequency signal output from the tuner circuit is kept constant.
[0068]
Thus, the intermediate frequency processing circuit of the present invention allows the video carrier VIF_CAFT signal V that changes according to the amount of the frequency shift_AFTIs generated and fed back to the tuner circuit to stabilize the frequency of the intermediate frequency signal.
[0069]
Generally, video carrier VIF_CThe frequency of the reference signal for detecting the frequency shift of the video carrier VIF_CIs required to be equal to or higher than the required frequency accuracy.
In the present embodiment, the video carrier VIF_CIs converted to a low band by the multiplier MUL, and the center frequency f of the oscillation signal S50 of the voltage controlled oscillator 50 used as a reference signal for the phase comparison._VCOIs (N ω_SC−ω_PCTherefore, the precision ratio x required for the voltage-controlled oscillator 50 and the precision required for the conventional reference signal generator can be expressed by the following equation.
[0070]
(Equation 9)
x = ω_PC/ (N ω_SC−ω_PC…… (9)
[0071]
Here, in the present embodiment, assuming that the multiplier N of the multiplier is (N = 14), the center frequency f of the voltage controlled oscillator 50 is_VCOIs (f_VCO= 4.25 MHz). The precision ratio x shown in Expression (9) is about 13.8 times. Further, assuming that the multiplication number (N = 16), the center frequency f of the voltage controlled oscillator 50_VCOIs (f_VCO= 13.25 MHz), and the precision ratio x shown in Expression (9) is about 4.43 times.
[0072]
That is, in the present embodiment, the video carrier VIF_CIs converted to a low band by the multiplier MUL, the accuracy requirement for the voltage-controlled oscillator 50 for generating the reference signal is relaxed as compared with the reference signal generator of the conventional AFT signal generation circuit.
[0073]
As described above, according to the present embodiment, the audio intermediate frequency signal SIF is multiplied by N by the multiplier 10 to obtain the video carrier VIF._CAnd the signal S converted to the low frequency_mIs input to the PLL circuit. By the PLL circuit, the signal S_mIs FM detected, and the audio signal and the video carrier VIF are detected._CGenerates a signal S401 corresponding to the frequency shift of₁, The DC component is removed, and the audio signal V amplified by the amplifier 90_MPXIs output, and the audio signal component is removed by the low-pass filter 60._COf the AFT signal V_AFTAs a result, the S / N ratio of the audio signal can be improved, the requirement for the accuracy of the voltage controlled oscillator 50 for generating the reference signal for the phase comparison can be relaxed, and the audio signal can be reduced by one intermediate frequency processing circuit. Detection and AFT signal V_AFTCan be realized.
[0074]
Second embodiment
FIG. 2 is a circuit diagram showing a second embodiment of the intermediate frequency processing circuit according to the present invention. As shown, the intermediate frequency processing circuit of the present embodiment includes a multiplier 10, an oscillator 12, a multiplier MUL, a phase detector 20, an amplifier 30, a low-pass filter 40, a voltage-controlled oscillator 50, a low-pass filter 60, a capacitor C₁And amplifiers 80 and 90.
[0075]
It should be noted that the present embodiment is different from the first embodiment shown in FIG. 1 in that the video carrier VIF input to the multiplier MUL is_CThis embodiment differs from the first embodiment in that an oscillation signal S12 from the oscillator 12 is used.
The components constituting the PLL circuit are the same as those in the first embodiment, and these components are described using the same reference numerals as in FIG. The detailed description of the same components as those in FIG. 1 is omitted.
[0076]
As shown in FIG. 2, in this example, both a multiplied signal S10 obtained by multiplying the audio intermediate frequency signal SIF by N by the multiplier 10 and an oscillation signal S12 generated by the oscillator 12 are input to the multiplier MUL. A signal S obtained by removing the high-frequency component and leaving only the low-frequency component through a low-pass filter (not shown) on the result of the multiplication by the multiplier MUL._m1Is input to the phase detector 20 constituting the PLL circuit.
[0077]
Here, the output signal S12 of the oscillator 12 is, for example, a video carrier VIF._CAn oscillation signal having the same frequency as This oscillator can be constituted by, for example, a ceramic oscillator or the like.
As a result of the multiplication processing of the multiplied signal S10 and the oscillation signal S12, the modulation index of the audio intermediate frequency signal SIF becomes N times the number of times, and the carrier frequency of the audio intermediate frequency signal SIF, which is an FM signal, is converted to a lower frequency band. Therefore, the audio signal V having a high S / N ratio is obtained by the FM detection circuit constituted by the PLL circuit._MPXIs obtained.
[0078]
As described above, according to the present embodiment, the AFT signal V_AFTCannot be realized, but by multiplying the audio intermediate frequency signal SIF and multiplying the signal with the oscillation signal S12, the modulation index of the audio intermediate frequency signal SIF can be improved and the carrier frequency can be converted to a lower frequency band. An N-ratio audio signal is obtained.
[0079]
Third embodiment
FIG. 3 is a circuit diagram showing a third embodiment of the intermediate frequency processing circuit according to the present invention.
As shown, the intermediate frequency processing circuit of the present embodiment includes an oscillator 14, a multiplier MUL, a phase detector 20, an amplifier 30, a low-pass filter 40, a voltage controlled oscillator 50, and an amplifier 70.
[0080]
The present embodiment is different from the first embodiment shown in FIG. 1 in that the present embodiment uses an oscillation signal S14 from an oscillator 14 instead of the multiplied signal S10 input to the multiplier MUL. .
The components constituting the PLL circuit are the same as those in the first embodiment, and these components are described using the same reference numerals as in FIG. The detailed description of the same components as those in FIG. 1 is omitted.
[0081]
As shown in FIG. 3, in this example, the oscillation signal S14 from the oscillator 14 and the video carrier VIF_CAre input to the multiplier MUL. A signal S obtained by removing the high-frequency component and leaving only the low-frequency component through a low-pass filter (not shown) on the result of the multiplication by the multiplier MUL._m2Is input to the phase detector 20 constituting the PLL circuit.
[0082]
The signal S input to the PLL circuit_m2The frequency of the video carrier VIF_COf the video carrier VIF by the PLL circuit._C, A voltage signal S40 proportional to the frequency shift is output. The voltage signal S40 is amplified by the amplifier 70, and the AFT signal V_AFTThe frequency of the intermediate frequency signal output from the tuner circuit is kept constant by finely adjusting the oscillation frequency of the local oscillator of the tuner circuit.
[0083]
In this example, the oscillator 14 can be constituted by, for example, a ceramic oscillator or the like. The operating frequency of the oscillator 14 is set to, for example, substantially the same frequency as the frequency-multiplied signal S10 from the frequency multiplier 10 shown in FIG. Here, the angular frequency of the oscillation signal S14 from the oscillator 14 is ω_OSCThen, the signal S input to the phase detector 20_m2Is the difference (ω) between the angular frequencies of the two signals input to the multiplier MUL._PC−ω_OSC). In response to this, the center frequency f of the voltage-controlled oscillator 50 of the PLL circuit is_VCOIs (ω_PC−ω_OSC).
[0084]
Thus, the video carrier VIF_COf the AFT signal V_AFTThe oscillation signal S50 from the voltage controlled oscillator 50 is used as a reference signal for generating the signal. For this reason, the accuracy requirement for the voltage controlled oscillator 50 is relaxed as compared with the accuracy required for the conventional reference signal generator.
[0085]
As described above, according to the present embodiment, the oscillation signal S14 from the oscillator 14 and the video carrier VIF_CAnd the video carrier VIF_CIs converted to a low frequency band, and the video carrier VIF is_CDetects and outputs a voltage signal proportional to the frequency shift of the AFT signal V_AFTTo the tuner circuit, the video carrier VIF_CBy the low-frequency conversion of the frequency, the requirement for the accuracy of the voltage controlled oscillator 50 that generates the reference signal for the phase comparison can be relaxed, and the high-precision AFT signal V_AFTCan be generated.
[0086]
【The invention's effect】
As described above, according to the intermediate frequency processing circuit of the present invention, the S / N ratio of the demodulated audio signal can be improved, and the requirement for the accuracy of the reference signal generator for generating the AFT signal is reduced. There are advantages that can be done.
Further, according to the present invention, the demodulation of the audio signal and the generation of the AFT signal can be realized by one circuit, and the circuit configuration can be simplified.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of an intermediate frequency processing circuit according to the present invention.
FIG. 2 is a circuit diagram showing a second embodiment of the intermediate frequency processing circuit according to the present invention.
FIG. 3 is a circuit diagram showing a third embodiment of the intermediate frequency processing circuit according to the present invention.
FIG. 4 is a block diagram of an intermediate frequency processing circuit of an intercarrier system.
FIG. 5 is a block diagram of a pseudo split carrier type intermediate frequency processing circuit.
FIG. 6 is a block diagram illustrating an example of a conventional audio signal demodulation circuit.
FIG. 7 is a circuit diagram showing an example of a single tuning circuit used for an audio signal demodulation circuit.
FIG. 8 is a graph showing amplitude and phase characteristics of a single tuning circuit.
FIG. 9 is a block diagram illustrating an example of a conventional AFT circuit.
FIG. 10 is a circuit diagram illustrating an example of a π / 2 phase shifter.
FIG. 11 is a graph showing frequency characteristics of a π / 2 phase shifter.
FIG. 12 is a graph showing output characteristics of the AFT circuit.
[Explanation of symbols]
10 Multiplier, 12, 14 Oscillator, MUL Multiplier, 20 Phase detector, 30 Amplifier, 40 Low-pass filter, 50 Voltage-controlled oscillator, 60 Low-pass filter, C₁... capacitors, 70, 80, 90 ... amplifiers.

Claims (8)

An intermediate frequency processing circuit for demodulating and outputting an audio signal from an audio intermediate frequency signal,
Multiplying means for multiplying the audio intermediate frequency signal by a predetermined multiplication number N (N is an integer) and outputting a multiplied signal;
Frequency conversion means for multiplying the multiplied signal and the input signal having the frequency of the carrier of the video intermediate frequency signal, and removing high frequency components included in the multiplication result,
A demodulating means for receiving an output signal of the frequency converting means and demodulating an audio signal contained in the output signal. The input signal is an intermediate frequency processing circuit according to claim 1, wherein the oscillation signal from the oscillator. 2. The intermediate frequency processing circuit according to claim 1, wherein said frequency conversion means comprises a multiplier and a low-pass filter. 2. The intermediate frequency processing circuit according to claim 1, wherein said demodulation means is constituted by a PLL circuit. 2. The intermediate frequency processing circuit according to claim 1, wherein the input signal is a carrier of a video intermediate frequency signal from a tuning circuit. The input signal is a carrier of the video intermediate frequency signal from the tuning circuit,
A low-pass filter that receives an output signal from the demodulation unit and removes the audio signal included in the output signal;
2. The intermediate frequency processing circuit according to claim 1, further comprising: amplification means for amplifying an output of the low-pass filter and supplying the amplified signal to the tuning circuit as a frequency stabilization control signal. An intermediate frequency processing circuit that receives the video intermediate frequency signal from the tuning circuit, outputs a control signal corresponding to the frequency change of the carrier of the video intermediate frequency signal to the tuning circuit, and stabilizes the output frequency of the tuning circuit. hand,
Frequency conversion for removing a high frequency component contained in the multiplication result by multiplying the carrier of the video intermediate frequency signal by an input signal having a frequency obtained by multiplying the audio intermediate frequency signal by a predetermined multiple N (N is an integer). Means,
Receiving the output signal of the frequency conversion means, extracting a signal corresponding to the frequency change of the video intermediate frequency signal included in the output signal, outputting the extracted signal to the tuning circuit, And a demodulation means for controlling the output frequency of the intermediate frequency. The input signal is an intermediate frequency processing circuit according to claim 7, wherein the oscillation signal from the oscillator.

Images