JP3593021B2 - Synchronous acquisition system - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a synchronization acquisition system, and more particularly, to a memory accumulation type synchronization acquisition system suitable for use in a receiver using a direct sequence / spread spectrum (DS / SS) system. .
[0002]
[Prior art]
FIG. 4 is a block diagram showing a simple configuration of a memory storage type synchronization acquisition system in a conventional receiver using the DS / SS system.
[0003]
In FIG. 4, a received signal (IF signal) is first converted into a baseband signal by a frequency conversion circuit 401, and then written into a memory 402 once. Thereafter, the signal read from the designated address is despread and added by the correlator 403 to calculate a correlation value. If the correlation value exceeds a threshold value, the read address becomes the correct despread timing. Is determined, and if it does not exceed, the address to be read is shifted by one sample or several samples, and the calculation of the correlation value and the determination of the threshold value are similarly performed.
[0004]
This is repeated until a correlation value exceeding the threshold is detected, and the phase of the spread code generated by the spread code generator 404 is shifted from the despread timing thus obtained so as to match the real-time received signal. Generally, a spreading sequence used in the DS / SS system is a repetition of finite-length pseudo-noise. Therefore, if the period of the spreading code is counted from the time when the spreading code is written to the memory 402, the same timing as the signal in the memory 402 is known. be able to. More specifically, the spreading code generator 404 is reset at the same time as writing to the memory 402, and the timing of the spreading code generator 404 is deviated from the head address of the memory by the despreading timing obtained by the correlator 403. Just shift it.
[0005]
Thereafter, the received signal and the spreading code are multiplied by a multiplier 405, and a desired signal component is extracted by an LPF (Low Pass Filter) 406 to perform despreading, demodulation becomes possible, and at the same time, DLL (Delay Locked Loop) By operating 407, synchronization tracking is started.
[0006]
This synchronization acquisition method is required to realize a high-speed synchronization acquisition by making the reading speed faster than the writing speed, or to require a long integration time to obtain a correlation peak due to low SNR (Signal to Noise Ratio). It is used when it is difficult to acquire synchronization in real time from
[0007]
[Problems to be solved by the invention]
In the above method, since the despread timing obtained by the synchronization acquisition is for the received signal written in the memory 402, if this is reflected in the real-time received signal, the timing will be shifted. This is due to the mutual error included in the clocks on the transmitter side and the receiver side, and even if the clock error itself is very small, the deviation increases in proportion to the elapsed time. If it takes time, the range of the error included in the despreading timing to be reflected in real time cannot be ignored. As an example, if a DLL is used for synchronization tracking, timing correction is generally possible if the error is within about ± 1/2 chip. However, if the error exceeds that, synchronization tracking is disabled, and , Synchronization acquisition fails. Therefore, improvement in clock accuracy and high-speed processing of synchronization acquisition itself are indispensable, and an increase in circuit scale due to parallel processing and an increase in circuit load due to an increase in operating speed occur.
[0008]
Therefore, a technical problem to be solved by the present invention is to solve the above-mentioned problems of the prior art. The purpose of the present invention is to increase the speed and circuit scale more than necessary in the DS / SS system. It is an object of the present invention to realize a system capable of acquiring synchronization with high accuracy without causing the problem.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the synchronization acquisition system according to the present invention improves the accuracy of synchronization acquisition by performing synchronization acquisition again in a short time after the first synchronization acquisition.
[0010]
In general, in synchronization acquisition, a correlation value is detected for each despread timing for one cycle of a spreading code, and a point having a correlation peak exceeding a threshold value or the maximum value among all correlation values is obtained. By finding the points, the correct despread timing is obtained. At this time, the range of the error with respect to the real-time received signal included in the detected despread timing is obtained by determining the accuracy of the clock and the time taken to acquire the synchronization after writing the received signal into the memory. By writing the data into the memory and detecting the correlation value again for the timing within the obtained error range, the synchronization can be acquired in a much shorter time than the first time. Also, the range of the error of the despreading timing included becomes smaller, and the possibility of real-time demodulation and synchronization tracking becomes dramatically higher. If twice is not enough, the same operation may be repeated several times until the range of the timing error becomes sufficiently small.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0012]
FIG. 1 is a block diagram showing a configuration of a synchronization acquisition system in a receiver using the DS / SS system according to the first embodiment of the present invention. The synchronization acquisition system according to the present embodiment includes a frequency conversion circuit 101 for converting a reception signal into a baseband signal, a memory 102 for writing the reception signal at the time of synchronization acquisition, a correlator 103 for finding a correlation peak and establishing synchronization, and a clock number. Counter for counting the number of clocks based on the accuracy of the clock being used and the output of the clock counter 106, and counting the range of the timing deviation between the received signal in the memory and the real-time received signal. A counter 105, a switch 104 for judging from the error counter 105 whether the despread timing obtained from the correlator 103 is within the synchronization tracking range, and switching between starting demodulation or performing synchronization acquisition again, The spreading code generator 107, multiplier 108 and LPF 109 used And a DLL110 performing synchronization tracking.
[0013]
At the time of synchronization acquisition, first, the baseband signal converted by the frequency conversion circuit 101 is written into the memory 102. When the writing is completed, reading is performed, and a correlation value is detected by the correlator 103 for the read signal. At this time, if a high correlation value that exceeds the correlation peak threshold is obtained, it is determined that this is the correct despreading timing, synchronization acquisition is completed, and if a low correlation value that does not exceed the threshold is obtained, When it is determined that the timing is not correct despreading timing, reading is performed from a position shifted by one sample or several samples, and the calculation of the correlation value and the determination of the threshold value are similarly performed. This is repeated to find the timing of despreading.
[0014]
At this time, at the same time as writing to the memory 102, the clock counter 106 is operated, and counting is continued while the difference between the clocks is within one clock of the receiving side in consideration of the accuracy of the transmission and reception clocks. When the time exceeds one clock, the error counter 105 is counted by one, and at the same time, the clock counter 106 is reset and the same operation is repeated. Then, from the value of the error counter 105 at the time when the synchronization acquisition by the correlator 103 is completed, it is determined by the switch 104 whether or not the synchronization can be followed by the DLL 110. If the synchronization can be followed, the spread code generator 107 generates The phase of the spreading code to be corrected is corrected, multiplied by the received signal by the multiplication 108, and the desired signal component is extracted by the LPF 109, so that the despreading is performed, and at the same time, the DLL 110 is operated to start synchronization tracking.
[0015]
In addition, if it exceeds the range in which the synchronization can be followed, the error range indicated by the error counter 105 plus the received signal for the correlation value detection necessary is written into the memory 102 again, and at the same time, the clock counter 106 and the error counter 105 are reset and again. Similarly, the operation of synchronization acquisition is performed. At this time, the first synchronization acquisition has to search all timings of one cycle of the spreading code at the maximum, whereas the second synchronization acquisition has the error range within the first synchronization acquisition. Since only the limited timing needs to be searched, synchronization acquisition can be completed in a much shorter time than the first time, and the probability that synchronization acquisition can be completed before the error counter 105 exceeds the synchronization tracking range is greatly increased. Will be higher.
[0016]
If the synchronization cannot be followed even in the second synchronization acquisition, the synchronization acquisition can be completed in a shorter time by repeating the writing from the memory 102 in the same manner. Becomes sufficiently small, and can be captured within the synchronous followable range.
[0017]
As a specific example, FIG. 2 shows an operation flow when the accuracy of the receiving clock relative to the transmitting clock is 1 ppm and sampling is performed at 10 samples / chip.
[0018]
In FIG. 2, since the clock precision is 1 ppm, when the clock counter 106 counts 1 million clocks, the error counter 105 is counted by one and the clock counter 106 is reset. Furthermore, if the error range in which the DLL 110 can follow the synchronization is within ± １ ／ chip, the deviation within 5 samples from 10 samples / chip can be corrected. That is, the error counter 105 can be corrected when the correlator 103 completes the synchronization acquisition. Is less than 5, the demodulation is started by assuming that the error is in a range where synchronization can be followed. If the value is 5 or more, it is determined that the error may be in a range where synchronization cannot be followed, and the correlator 103 and the Synchronous acquisition is performed again using the value of the counter 105 as a parameter.
[0019]
Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration of a synchronization acquisition system in a receiver using the DS / SS scheme according to the second embodiment of the present invention. 3, reference numeral 301 denotes a frequency conversion circuit, 302 denotes a memory, 303 denotes a correlator, 304 denotes a loop counter, 305 denotes a spreading code generator, 306 denotes a multiplier, 307 denotes an LPF, and 308 denotes a DLL.
[0020]
In the configuration shown in FIG. 3, first, similarly to the first embodiment, the received signal converted into the baseband signal by the frequency conversion circuit 301 is written into the memory 302, and then read out as needed to find a correlation peak. At this time, the correlator 303 obtains a correlation with respect to all timings of one cycle of the spread code, and selects a maximum value from the correlations to find a correlation peak. It becomes. If the time required for synchronization acquisition is constant, the range of the error included in the obtained despread timing is also constant, so that the range can be known in advance from the accuracy of the clock and the time required for synchronization acquisition. Further, a correlation is obtained again for all the timings of the error range, and a correlation peak is found by selecting the maximum value as in the first time. Also at this time, the time required for the synchronization acquisition and the range of the error included in the despreading timing are known and constant, and are much smaller than the first time. It is possible to know how many iterations in advance will provide sufficient accuracy.
[0021]
Therefore, in order to obtain sufficient accuracy, the number of repetitions of synchronization acquisition is determined in advance from the accuracy of the clock, the length of the spreading code, the number of samples per chip, and the like, and the number of times is counted by the loop counter 304. The despreading timing is output to the spreading code generator 305 after the specified number of synchronization acquisitions are completed.
[0022]
After outputting the despreading timing to the spreading code generator 305, despreading and synchronization tracking are performed as in the first embodiment.
[0023]
【The invention's effect】
As described above, according to the first aspect of the present invention, the timing error can be corrected by using the same circuit as that of the synchronization acquisition section without increasing the speed more than necessary. This makes it possible to perform memory storage type synchronous capture without increasing the load or increasing the load. In addition, if the permissible time until the completion of the synchronization acquisition can be extended, the circuit scale can be reduced to some extent.
[0024]
Further, according to the second aspect of the present invention, it is possible to determine the timing error range with only a simple counter, and the algorithm for determining the error range in the first aspect can be easily realized.
[0025]
Further, according to the third aspect of the present invention, by using a correlator whose time required for detecting a correlation peak is substantially constant and known, the range of an error included in the obtained despread timing can be set in advance. Since it can be known, there is no need for a means for predicting the error range, and a simple algorithm that simply counts the number of times to repeat synchronization acquisition for error correction and counts Good synchronization acquisition can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a synchronization acquisition system in a receiver using a DS / SS system according to a first embodiment of the present invention.
FIG. 2 is a flowchart illustrating a specific synchronization acquisition algorithm according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a synchronization acquisition system in a receiver using the DS / SS system according to a second embodiment of the present invention.
FIG. 4 is a block diagram illustrating a configuration of a synchronization acquisition system in a receiver using the DS / SS method according to the related art.
[Explanation of symbols]
101, 301 Frequency conversion circuit 102, 302 Memory 103, 303 Correlator 104 Switch 105 Error counter 106 Clock counter 107, 305 Spread code generator 108, 306 Multiplier 109, 307 LPF
110, 308 DLL

Claims (3)

A frequency conversion circuit for converting a received IF signal into a baseband signal, a memory for temporarily storing the baseband signal, and calculating a correlation between a signal read from the memory and a target spreading code to find a correlation peak A correlator that detects the timing of despreading, a spreading code generator that generates a spreading code in accordance with the detected despreading timing, a multiplier that multiplies the spreading code by a real-time baseband signal, An LPF for extracting a desired signal component from the output signal of the multiplier, and a synchronization tracking circuit that performs a fine correction so that synchronization is not lost again after synchronization acquisition, a synchronization acquisition system for a receiver using a spread spectrum method,
Means for determining the range of deviation between the despread timing of the received signal at the time of writing to the memory generated due to the influence of the clock error of transmission and reception and the despread timing of the real-time received signal after the completion of synchronization acquisition,
Means for judging whether or not the range of this deviation is sufficiently within the range in which synchronization can be followed, and switching between outputting the despreading timing of the correlator to the spreading code generator side or the memory side. And
If the range of the deviation of the despreading timing does not fall within the range in which synchronization can be followed, a received signal having a length long enough to perform synchronization acquisition with respect to the deviation range is written into the memory, and the same circuit and A synchronization acquisition system characterized in that an error can be corrected by performing synchronization acquisition within an error range using an algorithm, and synchronization acquisition with set accuracy is realized. In claim 1,
As an algorithm for determining whether to output the despreading timing of the correlator to the spreading code generator side or the memory side,
A clock counter that counts clocks is operated at the same time as writing a received signal to the memory. At the same time as the reset, the value of the error counter is counted by one, and the process is repeated until the acquisition of the synchronization is completed. If the value of the error counter at the time of completion of the acquisition is within the range in which the synchronization can be followed, the demodulation and the tracking of the synchronization are started. And a synchronization acquisition system for writing to the memory and synchronizing once again at a timing within the error range indicated by the value of the error counter if the synchronization is out of the synchronization followable range. In claim 1,
Correlator having a known time spent for detection of a correlation peak, and means for counting the number of times of synchronization acquisition repeated for error correction of despreading timing,
By knowing in advance the transmission and reception clock errors and the range of errors included in the despread timing obtained from the correlation peak detection time, the number of repetitions of synchronization acquisition necessary to obtain sufficient accuracy is determined. A synchronization acquisition system characterized in that timing error correction can be realized with a simple algorithm and circuit by outputting the despread timing obtained by the correlator to the spreading code generator side after repeating synchronization acquisition for the number of times. .

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