JP3589988B2 - Clock skew improvement method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock skew improvement method, and more particularly to a clock skew improvement method suitable for skew improvement after laying out an LSI chip.
[0002]
[Prior art]
In the layout of an LSI chip, in order to reduce a phase shift (clock skew) of a clock signal supplied between a plurality of sequential circuits such as flip-flops (hereinafter abbreviated as F / F) scattered in the chip, Clock tree synthesis (hereinafter abbreviated as CTS), in which clock signal lines from a root buffer to an F / F are branched in a tree shape and arranged and wired to have equal lengths, is widely used.
[0003]
FIG. 11 is a flowchart of a layout design using CTS. In the cell placement step 11, basic circuit cells are placed according to the circuit connection information of the LSI. In the CTS wiring step 12, a clock signal is wired so that the route buffer and each F / F are adjusted to have the same length by referring to information on the capacitance value and the resistance value per unit length of the metal wiring. In the signal wiring step 13, wiring of signals other than the clock signal is executed in accordance with the circuit connection information. In the clock skew calculation step 14, the clock delay from the root buffer to the F / F is calculated for each signal path to the F / F. Then, a clock skew value is calculated from the maximum value and the minimum value of the clock delay. In the clock skew pass / fail determination step 15a, it is determined whether or not the calculated clock skew value is equal to or less than a preset target value. If the clock skew value is equal to or less than the target value, the layout design is completed and the process proceeds to the next design step, design verification. If the clock skew value exceeds the target value, the process returns to the CTS wiring step 12 and is executed again.
[0004]
FIG. 12A is a schematic diagram of the CTS wiring. The clock signal is supplied from the clock input pin CIN to the route buffer 1, and is supplied from the route buffer 1 to the plurality of F / Fs 2 by the clock wiring 3 having an equal length.
[0005]
The method of wiring the clock system using the CTS of FIG. 1 is very effective for a generation having relatively loose design rules, that is, a generation in which the area of the bottom surface of the metal wiring is much larger than the area of the side surface. And the clock skew value hardly exceeded the target value.
[0006]
However, in recent years, with the progress of miniaturization, the area of the side surface of the metal wiring has become equal to or larger than the area of the bottom surface, and therefore, as shown in FIG. In the situation where the coupling capacitance C2 to the adjacent signal wiring is becoming more dominant than the bottom capacitance C1, even if the CTS is executed to adjust the wiring length to the same length, the wiring is performed in the next signal wiring step 13. Depending on the magnitude of the coupling capacitance C2 between the adjacent signal wiring 7 and the clock wiring 3, the parasitic capacitance value of the clock wiring changes greatly. As a result, the clock skew value increases and the number of cases where the CTS needs to be re-executed after exceeding the target value is increasing. However, even if the CTS is re-executed, there is no guarantee that the CTS will be surely improved. In many cases, complicated corrections have to be performed manually, and in any case, there has been a problem that the design efficiency is reduced and the design period is extended.
[0007]
To solve this problem, Japanese Patent Application Laid-Open No. 10-135342 discloses a technique of providing a wiring layer dedicated to clock wiring. Wiring the clock wiring on a dedicated wiring layer makes it possible to eliminate adjacent signal wiring. However, when a dedicated wiring layer is provided as in the first conventional example, the number of manufacturing steps inevitably increases, and the manufacturing cost of the LSI increases, which is not preferable.
[0008]
As a second conventional example, Japanese Patent Application Laid-Open No. 9-283715 discloses that the delay of a clock signal is adjusted by adjusting the distance between each clock wiring and an adjacent signal wiring to increase or decrease the coupling capacitance after wiring is completed. A technique for improving a clock skew value is described. As shown in FIG. 13A, the delay value of the clock signal is adjusted by adjusting the interval between the clock wiring 3 and the adjacent signal wiring 70.
[0009]
The second conventional example is extremely effective when a wiring method in which a wiring grid is not set at the time of wiring is performed, because the interval between the clock wiring 3 and the adjacent signal wiring 70 can be finely adjusted.
[0010]
[Problems to be solved by the invention]
However, in many automatic placement and routing systems, a method of wiring on a preset wiring grid is adopted in order to improve the execution speed of the wiring processing, and compared with FIGS. 13B and 13C. As shown, when the wiring grid is set, the second conventional example has a problem that it is difficult to finely adjust the parasitic capacitance. That is, as shown in FIG. 13B, assuming that the clock wiring 3 and the adjacent signal wiring 70 are wired on the wiring grid of the wiring pitch Px, and both the wiring width and the wiring interval are D, FIG. In FIG. 13C in which the distance between the clock wiring 3 and the adjacent signal wiring 7 is D, the adjacent signal wiring 7 is moved by one wiring grid (one wiring pitch) in FIG. The distance from the signal wiring 70 is 3D. As described above, the clock delay value is increased at a triple interval, so that a fine adjustment of the clock delay value cannot be performed, and the skew cannot be easily improved.
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to make it possible to adjust clock signal delays to be equal without using a wiring layer dedicated to clock wiring, and to accurately adjust clock delay even when wiring is performed using a wiring grid, thereby achieving clock skew. The present invention relates to a clock skew improvement method that can be reduced.
[0012]
[Means for Solving the Problems]
Pattern clock skew improved method of the present invention, which stores the value of capacitance parasitic on the clock wire according to wiring block and wiring block name and an internal pattern that have a internal pattern consisting clock wiring patterns and the surrounding wiring pattern A clock skew improvement method for reducing skew between respective clock wirings from a route buffer laid out on an LSI chip to clock terminals of a plurality of sequential circuits using a table,
A first step of dividing a region along a wiring path into a plurality of unit blocks having the same outer shape as the wiring block for each clock wiring;
Referring to the pattern table, a clock signal delay value for each clock wiring is calculated, and a clock wiring having a smaller clock delay value than a value obtained by subtracting a target clock skew value from a maximum clock signal delay value is extracted. A second step of selecting as a clock wiring to be processed for skew improvement;
A third step of searching for a wiring block having the same internal pattern for each unit block for the processing target clock wiring, and replacing the internal pattern of the unit block with an internal pattern of a wiring block having a larger capacitance value than the searched wiring block ; the it has.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a layout design flowchart including a clock skew improvement process 16 according to an embodiment of the present invention.
[0014]
In FIG. 1, a cell layout step 11 to a clock skew calculation step 14 are the same as the conventional layout design flow shown in FIG. 11. In the cell layout step 11, basic circuit cells are arranged according to the circuit connection information of the LSI. In the CTS wiring step 12, a clock signal is wired so as to make the length between the route buffer and each F / F equal, and in the signal system wiring step 13, signals other than the clock signal are wired according to the circuit connection information. Is performed, and in a clock skew calculation step 14, a clock delay from the root buffer to the F / F is calculated for each signal path to the F / F, and a clock skew value is calculated from the maximum value and the minimum value of the clock delay.
[0015]
In a clock skew pass / fail determination step 15, it is determined whether or not the calculated clock skew value is equal to or less than a preset target value. If the clock skew value is equal to or less than the target value, the layout design is terminated and the next design step is performed. When the value exceeds the target value, the clock skew improvement processing step 16 is executed.
[0016]
In the clock skew improvement processing step 16, in the wiring block having a small capacitance value, a rectangular wiring block having an internal pattern including a clock wiring pattern and a surrounding wiring pattern is made to correspond to a capacitance value parasitic on the clock wiring according to the internal pattern. Skew between each clock wiring from the route buffer laid out on the LSI chip to the clock terminals of a plurality of sequential circuits such as F / Fs is reduced using the pattern table 10 recorded in the order from the largest wiring block to the largest wiring block. .
[0017]
The clock skew improvement processing step 16 includes, as lower processing steps, a wiring pattern division step 21, a target clock wiring selection step 22, a block replacement step 23, a skew value determination step 24, and a wiring correction step 25. ing.
[0018]
In the wiring pattern dividing step 21, a region along the wiring path is divided into a plurality of unit blocks having the same outer shape as the wiring blocks registered in the pattern table 10 for each clock wiring.
[0019]
In the target clock wiring selection step 22, the clock signal delay value for each clock wiring is calculated with reference to the pattern table, and the clock delay value is calculated by subtracting the target clock skew value from the maximum clock signal delay value. Is extracted and a clock wiring to be subjected to skew improvement is selected.
[0020]
In the block replacement step 23, a wiring block having the same internal pattern for each unit block is searched for the processing target clock wiring, and the internal pattern of the unit block is replaced with the internal pattern of the wiring block having a larger capacitance value than the searched wiring block. Replace.
[0021]
In the skew value determination step 24, a clock signal delay value for each clock wiring is calculated based on the capacitance value of the unit block after replacement, and a clock skew value is determined by comparing with the maximum clock signal delay value. It is determined whether the value is equal to or less than the value.
[0022]
In the wiring correction step 25, wiring correction around the clock wiring is performed based on the replacement result of the unit block.
[0023]
FIG. 2 is a configuration diagram of the clock skew improvement unit 31 that executes the clock skew improvement processing step 16. The clock skew improving unit 31 includes a CPU that executes logical operations and numerical operations necessary for the clock skew improving process, a wiring pattern dividing step 21, a target clock wiring selecting step 22, a block replacing step 23, a skew value determining step 24, It has a storage unit for storing a program for realizing the function of the wiring correction step 25 and data being processed, and inputs the LSI arrangement and wiring result 32 created by the layout design up to the clock skew pass / fail determination step 15. The clock skew improvement process from the wiring pattern division step 21 to the wiring correction step 25 is executed with reference to the pattern table 10, and a part of the wiring around the clock wiring is corrected so that the clock skew value is within the target value. The skew-improved placement and routing result 33 is output. It is possible to control the processing operation of the clock skew improvement unit 31, modify and change the processing data, display the processing result, etc. from the outside through the input / output / display unit 34.
[0024]
FIG. 3 is a diagram illustrating an example of registered contents of the pattern table 10. Inside the pattern table 10, a wiring block name, a wiring block 7 including the clock wiring pattern 3 and surrounding signal wiring patterns as internal patterns, and a capacitance value parasitic on the clock wiring pattern 3 are registered in correspondence with each other. They are arranged in order from an internal pattern having a small capacitance value to an internal pattern having a large capacitance value. The internal pattern of the wiring block 7 includes the wiring pattern in the wiring block 7 and the wiring pattern of the wiring whose center line coincides with the outer boundary of the wiring block 7.
[0025]
FIG. 4 is a detailed flowchart of the wiring pattern division step 21 and the target clock wiring selection step 22. FIG. 5 is a diagram schematically illustrating the processing of the wiring pattern division step 21.
[0026]
In the wiring pattern dividing step 21, as shown in the layout pattern diagram of FIG. 5A, for each of the clock wirings connecting the route buffer 1 and the F / F 2, an area along the wiring path of the clock wiring 3 is shown. As shown in FIG. 5B, the data is divided into a plurality of unit blocks 8 having the same outer shape as the wiring block 7 registered in the pattern table 10 and recorded in correspondence with each clock wiring. Similarly to the case of the wiring block 7, the internal pattern of the unit block 8 includes the wiring pattern included in the unit block 8 and the wiring pattern of the wiring whose center line coincides with the outer boundary of the unit block 8. In FIG. 5, reference numeral 4 denotes a metal wiring pattern, reference numeral 5 denotes an upper metal wiring pattern, and reference numeral 6 denotes a through hole pattern for connecting the metal wiring 4 and the upper metal wiring 5.
[0027]
Although the size of the wiring block 7 can be set arbitrarily, in the description after FIG. 5, two wiring grids in the X direction (that is, twice the wiring pitch Py of the Y direction wiring) and the Y direction are used. This is equivalent to two wiring grids (that is, twice the wiring pitch Px of the X-directional wiring). By using a small wiring block having two wiring grids in both the X direction and the Y direction, the types of wiring blocks registered in the pattern table 10 can be reduced. Can be executed.
[0028]
The target clock wiring selection step 22 includes sub-steps 40 to 44 as shown in FIG. In sub-step 40, it is determined whether or not the clock wirings have been ranked in ascending order of the delay value of the clock signal. If the clock wiring has been ranked, the process proceeds to sub-step 41.
[0029]
In the sub-step 41, as shown in FIG. 5B, the unit block and the internal pattern of all the unit blocks 8 corresponding to the clock wiring 3 match with reference to the pattern table 10 of FIG. A wiring block to be extracted is extracted, and its pattern number and capacitance value are stored in the storage unit of the clock skew improving unit 31 in association with the position information of the unit block, and as shown in FIG. Then, the capacitance values of all the unit blocks are added to calculate the capacitance value of the clock wiring.
[0030]
Next, in a sub-step 42, a clock signal delay value is calculated for each clock wiring based on the calculated capacitance value, and in a sub-step 43, the clock wiring is changed from the clock wiring with the smallest clock signal delay value to the maximum clock wiring. The order is determined according to the clock signal delay value and stored in the storage unit.
[0031]
After the processing in the sub-step 43 and when it is determined in the sub-step 40 that the clock wiring has been ranked, the processing proceeds to the sub-step 44, in which the clock wiring among the clock wirings whose processing up to the skew value determination step 24 has not been completed is The clock wiring with the smallest signal delay value is selected as the clock wiring to be processed, and the target clock wiring selection step 22 is completed.
[0032]
FIG. 6 is a detailed flowchart of the block replacement step 23. In order to improve the clock skew by increasing the clock delay time of the clock wiring to be processed, the sub-steps 51 to 55 are performed in the block replacement step 23. Each sub-step will be described with reference to FIG. 5 and FIG. 7, which is a diagram schematically showing the block replacement process.
[0033]
First, in the sub-step 51, of the unit blocks 8 related to the clock wiring to be processed shown in FIG. 5B, the replacement processing is not performed and is closest to the F / F2 in the distance along the path of the clock wiring 3. A unit block is selected as a processing target block.
[0034]
Next, in sub-step 52, the wiring pattern in the processing target block corresponds to an isolated clock pattern (see FIG. 10A) in which the wiring pattern is only clock wiring and there is no signal wiring pattern in a wiring grid adjacent to the processing target block. It is determined whether or not to perform the block replacement. If it is determined that the block replacement is performed, the block replacement step 23 ends. If it is determined that the condition is not satisfied, the process proceeds to sub-step 53.
[0035]
In a sub-step 53, a wiring block whose internal pattern matches the processing target block is searched. A wiring block having the same internal pattern as the processing target block registered in the pattern table may be newly extracted by executing a pattern matching process similar to the sub-step 41 of FIG. The wiring block name of the internal pattern corresponding to the unit block is stored in advance for each clock wiring based on the result, and the processing target block and the internal pattern match from the target clock wiring name and the position information of the unit block that is the processing target block. The name of the wiring block to be used may be searched.
[0036]
Next, in sub-step 54, it is determined whether or not a replacement wiring block having a larger capacitance value than the searched wiring block and being a wiring block that can be replaced and disposed with the processing target block exists in the pattern table 10. to decide. In the pattern table 10, the wiring blocks are registered in order from the one with the smallest parasitic capacitance of the clock wiring to the one with the largest parasitic capacitance. Therefore, the wiring blocks are sequentially taken out from the wiring block of the internal pattern corresponding to the processing target block as a base point. Even if the internal pattern and the internal pattern of the block to be processed are replaced, it is determined that replacement is possible when there is no violation such as a short circuit between wires having different net names. If it is determined that there is no replaceable replacement wiring block, the block replacement step 23 is ended. If it is determined that there is a replacement wiring block, the process proceeds to sub-step 55.
[0037]
In sub-step 55, the internal pattern of the block to be processed is cut out and replaced with the internal pattern of the replacement wiring block. FIG. 7A shows the result of applying the processing of the block replacement step 23 to the layout result of FIG. 5A with the unit block closest to F / F2 as the processing target block, and the wiring pattern WP1 is added. The parasitic capacitance of the clock wiring 3 has increased. When replacing the internal pattern, the wiring pattern having the same position and shape as the internal pattern of the processing target block before replacement and the internal pattern after replacement has the net name of the wiring to which each wiring pattern in the processing target block before replacement belongs. And a newly added wiring pattern is given a net name to be dealt with.
[0038]
FIG. 8 is a detailed flowchart of the skew value determination step 24 and the wiring correction step 25. In the skew value determination step 24, the processing of sub-steps 61 to 63 is performed.
[0039]
In sub-step 61, the parasitic capacitance value of the clock wiring to be processed is updated to the capacitance value corresponding to the internal pattern changed in block replacement step 23, and the clock signal delay value is calculated.
[0040]
Next, in sub-step 62, a skew value of the clock wiring to be processed is calculated from the delay value of the clock wiring to be processed calculated in sub-step 61 and the maximum clock signal delay value obtained in sub-step 42 of FIG. Is determined to be equal to or less than a predetermined skew target value. If it is determined that the skew target value is exceeded, the process returns to the sub-step 51 of the block replacement step 23. When it is determined that the skew value of the clock wiring to be processed has been reduced to the skew target value or less, the process proceeds to sub-step 63.
[0041]
In sub-step 63, it is determined whether or not the clock skew of all the clock wirings is equal to or less than a predetermined skew target value. If it is determined that there is a clock wiring exceeding the target value, the process returns to the sub-step 40 of the target clock wiring selection step 22. When it is determined that all the clock wirings are equal to or less than the target value, the skew value determination step 24 ends.
[0042]
In the state of FIG. 7A in which the block replacement step 23 is completed with the unit block closest to F / F2 in FIG. 5A as the processing target block, if the skew value does not become less than the target value, the sub-step From step 62, the process returns to the block replacement step 23, and in step 51, the unit block 8 second closest to the F / F 2 is selected as the processing target block, and the processing in steps 52 to 55 is executed. As shown in FIG. Then, the wiring pattern WP2 is added to the internal pattern of the processing target block to increase the parasitic capacitance of the clock wiring 3. In substep 61 of the skew value determination step 24, the clock signal delay value of the target clock wiring is calculated. If the skew value does not become equal to or smaller than the target value in substep 62, the process returns to substep 51 and returns from F / F2 The processing of sub-steps 52 to 55 is executed with the unit block closest to the third as a processing target block, and wiring patterns WP3 and WP4 are added to increase the parasitic capacitance of the clock wiring 3 as shown in FIG. .
[0043]
In this way, the block replacement is sequentially performed toward the unit block located far from the F / F2, and when the skew value becomes equal to or less than the target value in the sub-step 62, the improvement processing for the target clock wiring is terminated. If there is a clock line having a skew value exceeding the target value, the process returns to the target clock line selection step 22 and is selected as the next processing target clock line in the sub-step 44 to perform an improvement process.
[0044]
After the skew values of all the clock wirings have been improved to the predetermined skew target value or less, in a wiring correction step 25, wiring correction around the clock wiring is executed based on the replacement result of the unit block. At this time, the position of the wiring pattern is fixed with respect to the internal pattern of the unit block after the replacement processing, and after connecting the wiring patterns with the same net name to each wiring pattern, the signal wiring outside the unit block is connected. If there is no unnecessary wiring, the clock skew improvement processing 16 is terminated.
[0045]
FIG. 7D is a layout pattern diagram after the improvement processing in which the wiring correction step 25 has been completed. Compared with the layout pattern diagram before the improvement processing in FIG. 5A, the clock wiring 3 and the wiring patterns WP1 and WP2 are compared. , WP3, WP4, etc. are added. As is clear from the above description, since the parasitic capacitance can be increased in the unit block unit, the clock delay can be adjusted with high accuracy even when the wiring grid is used, and the clock skew can be reduced.
[0046]
FIG. 9 is a flowchart of the block replacement step 23a in the second embodiment of the present invention. In the block replacement step 23a, when the wiring pattern in the processing target block is only the clock wiring and corresponds to the isolated clock pattern having no signal wiring pattern in the wiring grid adjacent to the processing target block, the isolated clock wiring in FIG. The capacity of the target clock wiring is increased as shown in FIG. For this reason, a sub-step 56 is added to the block replacement step 23a of FIG. 9 in addition to the sub-steps 51 to 55 included in the block replacement step 23 of FIG. The sub-steps 51 to 55 are the same as the block replacement step 23 of FIG. 6, and can be replaced with the block replacement step 23 in the layout design flowchart of FIG.
[0047]
In the block replacement step 23a, there is no other signal wiring in the unit block 3 as in the clock wiring 3 of FIG. 10A in the sub-step 52, and the signal wiring is also provided on an external wiring grid adjacent to the unit block 3. If it corresponds to an isolated clock pattern that is not scattered, the process proceeds to sub-step 56, and as shown in FIG. 10B, the unit block 8 to be processed is provided with a power line pattern 9 or a ground line pattern Is replaced with the wiring block in which is arranged.
[0048]
With the addition of the sub-step 56, even when the clock wiring near the clock input terminal of the F / F2 is isolated, it can be replaced with a wiring block having a large parasitic capacitance, so that the clock delay time is adjusted. The advantage of a wider range arises. The power supply line pattern 9 or the ground line pattern is connected to the internal power supply line or the internal ground line of the F / F 2 as shown in FIG.
[0049]
【The invention's effect】
As described above, by applying the present invention, it is possible to adjust the delay of the clock signal to be equal without using a wiring layer dedicated to the clock wiring, and to control the clock even when wiring is performed using the wiring grid. Since the delay can be adjusted with high accuracy, when the clock skew needs to be improved after the placement and wiring of the LSI, the clock skew can be easily and reliably reduced without re-executing the placement and wiring of the entire LSI.
[Brief description of the drawings]
FIG. 1 is a layout design flowchart including a clock skew improvement process of the present invention.
FIG. 2 is a configuration diagram of a clock skew improvement unit.
FIG. 3 is a diagram showing an example of registered contents of a pattern table.
FIG. 4 is a detailed flowchart of a wiring pattern dividing step and a target clock wiring selecting step.
FIG. 5 is a diagram schematically illustrating processing of a wiring pattern division step.
FIG. 6 is a detailed flowchart of a block replacement step.
FIG. 7 is a diagram schematically illustrating a block replacement process. FIG. 8 is a detailed flowchart of a skew value determination step and a wiring correction step.
FIG. 9 is a flowchart of a block replacement step in the second embodiment of the present invention.
FIG. 10 is a diagram schematically illustrating processing for improving isolated clock wiring.
FIG. 11 is a flowchart of a layout design using CTS.
FIG. 12 is a schematic diagram of a CTS wiring and a diagram for explaining its problems.
FIG. 13 is a diagram illustrating a second conventional example and its problems.
[Explanation of symbols]
1 route buffer 2 F / F
3 Clock Wiring 7 Wiring Block 8 Unit Block 10 Pattern Table 11 Cell Arrangement Step 12 CTS Wiring Step 13 Signal System Wiring Step 14 Clock Skew Calculation Step 15, 15a Clock Skew Pass / Fail Judgment Step 16 Clock Skew Improvement Processing Step 21 Pattern Division Step 22 Target Clock wiring selection step 23, 23a Block replacement step 24 Skew value determination step 25 Wiring correction step

Claims (6)

Using a pattern table storing the value of capacitance parasitic on the clock wire according to wiring block and wiring block name and an internal pattern that have a internal pattern consisting clock wiring patterns and the surrounding wiring pattern, layout LSI chip A clock skew improvement method for reducing a skew between respective clock wirings from a route buffer to a clock terminal of a plurality of sequential circuits,
A first step of dividing a region along a wiring path into a plurality of unit blocks having the same outer shape as the wiring block for each clock wiring;
Referring to the pattern table, a clock signal delay value for each clock wiring is calculated, and a clock wiring having a smaller clock delay value than a value obtained by subtracting a target clock skew value from a maximum clock signal delay value is extracted. A second step of selecting as a clock wiring to be processed for skew improvement;
A third step of searching for a wiring block having the same internal pattern for each unit block for the processing target clock wiring, and replacing the internal pattern of the unit block with an internal pattern of a wiring block having a larger capacitance value than the searched wiring block ; clock skew improved method characterized by having a. A rectangular wiring block having an internal pattern composed of a clock wiring pattern and a surrounding wiring pattern, and a wiring block having a small capacitance value and a wiring block having a large capacitance value corresponding to the wiring block name and the parasitic capacitance of the clock wiring according to the internal pattern. A clock skew improvement method for reducing a skew between respective clock wirings from a route buffer laid out on an LSI chip to clock terminals of a plurality of sequential circuits using a pattern table recorded in the order of
A first step of dividing a region along a wiring path into a plurality of unit blocks having the same outer shape as the wiring block for each clock wiring;
Referring to the pattern table, a clock signal delay value for each clock wiring is calculated, and a clock wiring having a smaller clock delay value than a value obtained by subtracting a target clock skew value from a maximum clock signal delay value is extracted. A second step of selecting as a clock wiring to be processed for skew improvement;
A third step of searching for a wiring block having the same internal pattern for each unit block for the processing target clock wiring, and replacing the internal pattern of the unit block with an internal pattern of a wiring block having a larger capacitance value than the searched wiring block; ,
Calculate the clock signal delay value for each clock wiring based on the capacitance value of the unit block after replacement and compare it with the maximum clock signal delay value to determine the clock skew value and determine whether it is below a predetermined skew target value A fourth step,
A fifth step of performing a wiring correction around the clock wiring based on the replacement result of the unit block,
In the second step, for each clock wiring, a wiring block having the same internal pattern as the unit block is detected with reference to the pattern table for all corresponding unit blocks, and a capacitance value corresponding to the wiring block is determined. A first sub-step of extracting and adding and calculating the capacitance value of the clock wiring;
A second sub-step of calculating a clock signal delay value for each clock wiring based on the calculated capacitance value;
A third sub-step of ranking the clock wiring according to the clock signal delay value from the clock wiring having the smallest clock signal delay value to the clock wiring having the largest clock signal delay value;
Clock skew improved method characterized by having a fourth sub-step of the clock signal delay value of the clock routing processing incomplete until the fourth step is selected for processing clock wiring minimal clock routing . A rectangular wiring block having an internal pattern composed of a clock wiring pattern and a surrounding wiring pattern, and a wiring block having a small capacitance value and a wiring block having a large capacitance value corresponding to the wiring block name and the parasitic capacitance of the clock wiring according to the internal pattern. A clock skew improvement method for reducing a skew between respective clock wirings from a route buffer laid out on an LSI chip to clock terminals of a plurality of sequential circuits using a pattern table recorded in the order of
A first step of dividing a region along a wiring path into a plurality of unit blocks having the same outer shape as the wiring block for each clock wiring;
Referring to the pattern table, a clock signal delay value for each clock wiring is calculated, and a clock wiring having a smaller clock delay value than a value obtained by subtracting a target clock skew value from a maximum clock signal delay value is extracted. A second step of selecting as a clock wiring to be processed for skew improvement;
A third step of searching for a wiring block having the same internal pattern for each unit block for the processing target clock wiring, and replacing the internal pattern of the unit block with an internal pattern of a wiring block having a larger capacitance value than the searched wiring block; ,
Calculate the clock signal delay value for each clock wiring based on the capacitance value of the unit block after replacement and compare it with the maximum clock signal delay value to determine the clock skew value and determine whether it is below a predetermined skew target value A fourth step,
A fifth step of performing a wiring correction around the clock wiring based on the replacement result of the unit block,
The third step is a first step of selecting a unit block, which has not been subjected to the replacement process and is closest to the sequential circuit at a distance along a path of the clock wiring, from the unit blocks related to the processing target clock wiring as a processing target block. Sub-steps,
It is determined whether or not the wiring pattern in the processing target block corresponds to only the clock wiring and an isolated clock pattern in which there is no signal wiring pattern in the wiring grid adjacent to the processing target block. A second sub-step ending the step;
A third sub-step which proceeds when it is determined in the second sub-step that the pattern does not correspond to an isolated clock pattern, and searches for a wiring block whose internal pattern matches the processing target block;
It is determined whether or not a replacement wiring block having a larger capacitance value than the searched wiring block and capable of replacement placement exists in the pattern table. If it is determined that no replacement wiring block exists, the third step is terminated. Sub-steps,
A clock skew which proceeds when it is determined in the fourth sub-step that the internal pattern of the block to be processed is cut and replaced with an internal pattern of the replacement wiring block. How to improve. A rectangular wiring block having an internal pattern composed of a clock wiring pattern and a surrounding wiring pattern, and a wiring block having a small capacitance value and a wiring block having a large capacitance value corresponding to the wiring block name and the parasitic capacitance of the clock wiring according to the internal pattern. A clock skew improvement method for reducing a skew between respective clock wirings from a route buffer laid out on an LSI chip to clock terminals of a plurality of sequential circuits using a pattern table recorded in the order of
A first step of dividing a region along a wiring path into a plurality of unit blocks having the same outer shape as the wiring block for each clock wiring;
Referring to the pattern table, a clock signal delay value for each clock wiring is calculated, and a clock wiring having a smaller clock delay value than a value obtained by subtracting a target clock skew value from a maximum clock signal delay value is extracted. A second step of selecting as a clock wiring to be processed for skew improvement;
A third step of searching for a wiring block having the same internal pattern for each unit block for the processing target clock wiring, and replacing the internal pattern of the unit block with an internal pattern of a wiring block having a larger capacitance value than the searched wiring block; ,
Calculate the clock signal delay value for each clock wiring based on the capacitance value of the unit block after replacement and compare it with the maximum clock signal delay value to determine the clock skew value and determine whether it is below a predetermined skew target value A fourth step,
A fifth step of performing a wiring correction around the clock wiring based on the replacement result of the unit block,
The third step is a first step of selecting a unit block, which has not been subjected to the replacement process and is closest to the sequential circuit at a distance along a path of the clock wiring, from the unit blocks related to the processing target clock wiring as a processing target block. Sub-steps,
A second sub-step of determining whether or not the wiring pattern in the processing target block is a clock wiring only and corresponds to an isolated clock pattern having no signal wiring pattern in a wiring grid adjacent to the processing target block;
A third sub-step which proceeds when it is determined in the second sub-step that the pattern does not correspond to an isolated clock pattern, and searches for a wiring block whose internal pattern matches the processing target block;
It is determined whether or not a replacement wiring block having a larger capacitance value than the searched wiring block and capable of replacement placement exists in the pattern table. If it is determined that no replacement wiring block exists, the third step is terminated. Sub-steps,
A fifth sub-step of proceeding when it is determined in the fourth sub-step that the internal pattern of the processing target block is cut and replaced with an internal pattern of the replacement wiring block;
The process proceeds when it is determined in the second sub-step that the pattern corresponds to an isolated clock pattern, and the processing target block is replaced with a wiring block in which a power supply line pattern or a ground line pattern is arranged on both sides of a clock wiring pattern. clock skew improved method characterized by having a sixth sub-step of ending the third step. A rectangular wiring block having an internal pattern composed of a clock wiring pattern and a surrounding wiring pattern, and a wiring block having a small capacitance value and a wiring block having a large capacitance value corresponding to the wiring block name and the parasitic capacitance of the clock wiring according to the internal pattern. A clock skew improvement method for reducing a skew between respective clock wirings from a route buffer laid out on an LSI chip to clock terminals of a plurality of sequential circuits using a pattern table recorded in the order of
A first step of dividing a region along a wiring path into a plurality of unit blocks having the same outer shape as the wiring block for each clock wiring;
Referring to the pattern table, a clock signal delay value for each clock wiring is calculated, and a clock wiring having a smaller clock delay value than a value obtained by subtracting a target clock skew value from a maximum clock signal delay value is extracted. A second step of selecting as a clock wiring to be processed for skew improvement;
A third step of searching for a wiring block having the same internal pattern for each unit block for the processing target clock wiring, and replacing the internal pattern of the unit block with an internal pattern of a wiring block having a larger capacitance value than the searched wiring block; ,
Calculate the clock signal delay value for each clock wiring based on the capacitance value of the unit block after replacement and compare it with the maximum clock signal delay value to determine the clock skew value and determine whether it is below a predetermined skew target value A fourth step,
A fifth step of performing a wiring correction around the clock wiring based on the replacement result of the unit block,
A fourth sub-step in which the fourth step updates a capacitance value of the clock wiring to be processed and calculates a clock signal delay value;
The skew value of the clock line to be processed is calculated from the delay value of the clock line to be processed and the maximum delay value of the clock signal, and it is determined whether the skew value is equal to or less than a predetermined skew target value. A second sub-step, returning to step 3,
In the second sub-step, when it is determined that the clock skew is equal to or less than the target value, it is determined whether or not the clock skew of all clock wirings is equal to or less than the predetermined skew target value. there is when present back to the second step, the clock skew improved method characterized by having a third sub-step of terminating said fourth step when all clock lines is less than the target value . A rectangular wiring block having an internal pattern composed of a clock wiring pattern and a surrounding wiring pattern, and a wiring block having a small capacitance value and a wiring block having a large capacitance value corresponding to the wiring block name and the parasitic capacitance of the clock wiring according to the internal pattern. A clock skew improvement method for reducing a skew between respective clock wirings from a route buffer laid out on an LSI chip to clock terminals of a plurality of sequential circuits using a pattern table recorded in the order of
A first step of dividing a region along a wiring path into a plurality of unit blocks having the same outer shape as the wiring block for each clock wiring;
Referring to the pattern table, a clock signal delay value for each clock wiring is calculated, and a clock wiring having a smaller clock delay value than a value obtained by subtracting a target clock skew value from a maximum clock signal delay value is extracted. A second step of selecting as a clock wiring to be processed for skew improvement;
A third step of searching for a wiring block having the same internal pattern for each unit block for the processing target clock wiring, and replacing the internal pattern of the unit block with an internal pattern of a wiring block having a larger capacitance value than the searched wiring block; ,
Calculate the clock signal delay value for each clock wiring based on the capacitance value of the unit block after replacement and compare it with the maximum clock signal delay value to determine the clock skew value and determine whether it is below a predetermined skew target value A fourth step,
A fifth step of performing a wiring correction around the clock wiring based on the replacement result of the unit block,
Outer shape of the wiring block and the unit block, characterized in that it is a square having a side length of 2 wiring pitch to a right angle having a side length of 2 wiring pitch in the longitudinal direction of the wiring Clock skew improvement method.

Images