JP3584977B2 - PCI device, PCI bus system including the same, and data collection method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a PCI device connected to a PCI (Peripheral Component Interconnect) bus and a PCI system including the PCI device. Further, the present invention relates to a method for collecting data stored in the PCI device.
[0002]
[Prior art]
The PCI bus is one of computer bus architectures, and allows connection (addition) of various PCI devices such as a modem card and a video card. As an example of a PCI bus system having such a PCI bus, Japanese Patent Application Laid-Open No. H10-21152 discloses a LANP (LAN Processor) system that accommodates a large-capacity LAN line and exclusively performs data communication. I have. FIG. 10 is a block diagram showing a schematic configuration of the system.
[0003]
Referring to FIG. 10, in the LANP, a central processing unit (CPU) 200 and a main storage device (MEM) 201 are connected via a system bus 210, and a PCI bus control LSI (PCL) 202 is connected to the system bus 210. , A LAN line connection adapter (NIC) 203 and a host connection device (OLA) 204 are connected to a PCL 202 via a PCI bus 211.
[0004]
The LANP can be connected to the LAN line 222 via the NIC 203. In the LANP, the OLA 204 is connected to an external host computer 221 via the IO interface 212, and can transmit and receive data to and from the host computer 221. Here, the NIC 203 and the OLA 204 are PCI expansion cards (PCI devices) that control a communication protocol.
[0005]
FIG. 11 shows an example of a PCI expansion card. This PCI expansion card is the OLA 204 shown in FIG. 10 and has a microprocessor (MPU) 301 for controlling data transmission with the host computer 221 and an MPU 301 for controlling data transfer via the PCI bus 211. And a local memory (LM) 302 composed of a DRAM used for temporary storage of data and the like. The PBC 300 and the MPU 301 are each connected to the LM 302 via an internal bus, and each can access the LM 302 to read / write data. Further, the PBC 300 can transmit and receive data to and from the CPU 200 and the MEM 201 shown in FIG. 10 via the PCI bus 211.
[0006]
The PBC 300 includes a configuration space (CFG) 310 internally configured by an SRAM. The configuration space is a recording area for storing configuration information, and the configuration information is set when the system is set. The configuration information includes a defined header area and a device-dependent area, and generally has a PCI bus specification and has a total of 256 bytes. The defined header area is 64 bytes, and its layout is defined as a PCI bus standard. The device-dependent area has 192 bytes, and arbitrary information can usually be set for each PCI device. When the PBC 300 receives a PCI bus transaction via the PCI bus 211, the PBC 300 accesses the LM 302 to read / write data or transfer data via the PCI bus 211 according to the content of the received transaction. Or go. Control bits required for data transmission and information for causing the CPU 200 to recognize the PCI expansion card are set as configuration information.
[0007]
[Problems to be solved by the invention]
In a system in which a PCI expansion card (PCI device) is connected to a PCI bus as described above, when a failure occurs in a PCI device, data in the PCI device is stored in, for example, the LM 302 in FIG. For example, data is collected and the cause of the failure is analyzed. Also, at the time of debugging during development of the PCI device, data in the PCI device is collected.
[0008]
However, when a failure is detected in the PCI device or during debugging, the PCI bus-related setting information in the PCI device may be lost or not set correctly. In such a case, , The PCI device cannot receive a normal PCI bus transaction, and as a result, it becomes impossible to collect data in the PCI device.
[0009]
Further, when an IO transaction for information collection is issued from the operating system (OS) to the PCI device while the PCI device is in a state where the PCI device cannot accept the PCI transaction, the PCI device may generate a result of the IO transaction from the OS. The operation for the transaction issued on the PCI bus cannot be guaranteed. In such a case, an event occurs such that the PCI host (the PCL 202 in FIG. 10) detects a fatal error or the transaction on the PCI bus is lost. As a result, there has been a problem that the OS cannot continue to operate, and the entire system stops due to the data collection operation in the PCI device (the occurrence of a system error).
[0010]
An object of the present invention is to provide a PCI device and a data collection method that can solve the above-mentioned problem and reliably collect data.
[0011]
A further object of the present invention is to provide a PCI bus system using such a PCI device.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a PCI device of the present invention is a PCI device connected to a PCI bus and having a configuration space including a device-specific area in which registers can be arbitrarily set,
A register defined as the device-specific area is mounted, and upon receiving a data collection instruction, data collection control means for collecting data specified according to the contents of the register,
Upon receiving a configuration access to the device-specific area via the PCI bus, the device sends the data collection instruction to the data collection control unit, and the data collection control unit collects the data in response to the data collection instruction. Configuration access control means for transmitting data onto the PCI bus.
[0013]
A PCI bus system according to the present invention includes any one of the PCI devices described above and a PCI bus to which the PCI device is connected.
[0014]
The data collection method according to the present invention is a data collection method performed in a PCI bus system in which a PCI device having a configuration space including a device-specific area in which registers can be arbitrarily set is connected to a PCI bus.
Performing a configuration access to instruct the PCI device to collect data using the device-specific area;
Collecting the specified data in accordance with the configuration access, and transmitting the collected data to the PCI bus.
[0015]
In the present invention as described above, data stored in a PCI device is collected using configuration access on a PCI bus. In the configuration access on the PCI bus, even when nothing is set in the PCI device, the target PCI device can be specified and accessed by the IDESL signal defined in the PCI bus specifications. In addition, data in a PCI device can be collected not only when a failure occurs in a PCI device on the PCI bus but also when information relating to the operation of the PCI bus is not set normally due to a defect in software such as an OS or a device driver. is there. Therefore, according to the present invention, when a failure is detected in a PCI device or during debugging, even if the PCI bus-related setting information in the PCI device is lost or incorrectly set, Data in a PCI device can be collected.
[0016]
Conventionally, when collecting information at the time of failure, a PCI host detects a fatal error or a transaction on a PCI bus is lost, so that the OS cannot continue to operate. Although there is a problem of stopping (occurrence of a system error), in the present invention, as described above, the operation of collecting data in the PCI device at the time of a failure can be reliably performed. No error occurs.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings.
[0018]
The PCI device of the present invention is connected to a well-known PCI bus, and is attached to, for example, a motherboard of a computer as an expansion board (card). FIG. 1 shows a schematic configuration of a PCI card which is an embodiment of the PCI device of the present invention.
[0019]
The PCI card 102 according to the present embodiment is connected to a PCI bus 101, and includes a PCI bus interface control unit 103, a Config access control unit 104, a normal access control unit 105, a PCI bus tracer 106, and a Config. It comprises a register 107, an internal register 108, a data collection control unit 109, an internal bus tracer 110, an internal bus interface control unit 111, an internal bus 112, a local memory 113, and a microprocessor (MPU: Micro Processing Unit) 114.
[0020]
The PCI card 102 has a special 256-byte register called a configuration space. FIG. 2 shows an example of an address map of the configuration space in the PCI bus specification. The first 64 bytes are a header area (defined header area), which must be provided for each PCI device. The remaining 192 bytes are a device-specific area (device-dependent area), and its use is free for each PCI device. The register defined as the header area is implemented in the Config register 107, and the register defined as the device-specific area is implemented in the data collection control unit 109. The configuration access for instructing data collection to the data collection control unit 109, which will be described later, is executed using the device unique area of the configuration space shown in FIG.
[0021]
FIG. 3 shows the definition of the address phase of an AD (address / data) line in the configuration access of the PCI bus specification. Bits 0-1 define "type", bits 7-2 define "register number", bits 10-8 define "function number", and bits 31-11 define "reservation". Which address in the configuration space is accessed is determined by the register number defined by bits 7-2. Since the 6-bit register number is specified in units of double words (32 bits), a value of, for example, 10h to 3Fh ("** h" indicates hexadecimal notation) indicates a device-specific area. ing.
[0022]
The PCI bus interface control unit 103 is connected to the PCI bus 101, and when receiving a configuration access via the PCI bus 101, executes a process according to the configuration access to the Config access control unit 104. When a PCI bus transaction other than the configuration access, such as a memory read or a memory write, is accepted, the normal access control unit 105 is instructed to execute a process corresponding to the PCI bus transaction.
[0023]
The Config access control unit 104 executes access to the Config register 107 according to the content of the received configuration access, and performs data collection to the data collection control unit 109 in accordance with an instruction from the PCI bus interface control unit 103. Or give instructions. For example, if the register number defined by bits 7 to 2 of the configuration cycle shown in FIG. 3 is “00h” to “0Fh”, the Config access control unit 104 may set the header of the configuration space shown in FIG. Since the area is an area, access to the Config register 107 is performed. If the register number is “10h” to “3Fh”, the data collection control unit 109 is an area specific to the device in the configuration space shown in FIG. To collect data.
[0024]
The normal access control unit 105 accesses the internal register 108 or connects to the internal bus 112 via the internal bus interface control unit 111 in accordance with the content of the accepted PCI bus transaction in accordance with the instruction from the PCI bus interface control unit 103. Then, the access to the local memory 113 and the MPU 114 is finally executed.
[0025]
The PCI bus tracer 106 stores, through the PCI bus interface control unit 103, trace data of a transaction executed on the PCI bus 101. Similarly, the internal bus tracer 110 stores trace data of transactions executed on the internal bus 114.
[0026]
When receiving the data collection instruction from the Config access control unit 104 by the configuration access to the device unique area, the data collection control unit 109 performs the collection of the specified data according to the instruction. For example, in the case of a data collection instruction relating to the PCI bus tracer 106, the data collection control unit 109 reads data from the PCI bus tracer 106 and passes the read data to the Config access control unit 104. If the instruction is a data collection instruction related to the local memory 113, the data collection control unit 109 issues an instruction to the local memory 113 via the internal bus 112 to read the dump data in the local memory 113, and reads the dump data to the Config access control unit 104. Hand over the dump data. If the instruction is a data collection instruction related to the MPU 114, the data collection control unit 109 issues an instruction to the MPU 114 via the internal bus 112 to read the dump data of the MPU 114, and passes the read dump data to the Config access control unit 104. If the instruction is a data collection instruction related to the internal bus tracer 110, the data collection control unit 109 reads the data from the internal bus tracer 110 and passes the read data to the Config access control unit 104. If the instruction is a data collection instruction for the internal register 108, the data collection control unit 109 reads the data from the internal register 108 and passes the read data to the Config access control unit 104. The data collected from each is output to the PCI bus 101 via the PCI bus interface control unit 103.
[0027]
Next, the operation of the PCI card 102 of the present embodiment will be specifically described. FIG. 4 is a schematic diagram showing an example of an address space mapped in the PCI card 102 of FIG. In this example, addresses “00000000h to 000003FFh” are internal register areas, addresses “0000400h to 000FFFFFh” are unused, addresses “00100000h to 001FFFFFh” are PCI bus tracer areas, and addresses “00200000h to 002FFFFFh” are internal bus tracer areas. “00300000h to 012FFFFFh” is a local memory area, “0130000000h to FFFFFDFFh” is unused, and “FFFFFE00h to FFFFFFFFh” is an MPU area.
[0028]
When the configuration cycle shown in FIG. 3 is executed in the address phase on the PCI bus 101, the PCI card 102 is connected to the PCI host, which is the bus master, by an IDSEL (initializing device) connected one-to-one instead of a bus connection. When the (select) signal is asserted (active state), it recognizes that the configuration cycle being executed is a configuration cycle targeting the PCI card 102 itself. In other words, since the target PCI device is specified by the IDSEL signal in the configuration cycle, it is possible to access the PCI device side, in this case, the PCI card 102 side without any setting. In a normal memory read / write transaction or the like, access is impossible only after the setting of an address space and the like on the PCI device side is completed.
[0029]
When a configuration access to the PCI card 102 is received from the PCI bus 101, the PCI bus interface control unit 103 notifies the Config access control unit 104 of the function number and the register number in FIG. The Config access control unit 104 determines an access destination based on the function number and the register number received from the PCI bus interface control unit 103. Here, assuming that the PCI card 102 is a single function device, the function number is fixed to 0. In this case, the access destination is determined by the register number, and the 6-bit register number indicates the configuration register in units of double words (32 bits), which indicates which register in the 256-byte area shown in FIG. Show.
[0030]
Since the register number is assigned in units of double words, if the register number is multiplied by four, it becomes the register address in FIG. For example, if the register number indicates “02h”, the address is “08h”, which is a header area within 64 bytes from the beginning, so the Config access control unit accesses the Config register 107. The configuration register in the Config register 107 is determined by the PCI bus specification, and the register at the address “08h” stores the class code and the revision number. If the register number is “10h” or more, it indicates a device unique area, and the Config access control unit 104 issues a data collection instruction to the data collection control unit 109. That is, the header area in FIG. 2 is implemented in the Config register 107, and the device unique area is implemented in the data collection control unit 109.
[0031]
In order for the data collection control unit 109 to perform data collection, it is necessary to execute two configuration accesses. Here, the device unique area in FIG. 2 uses only the 32-bit register from the address “40h”. That is, the register number in the configuration access uses only “10h”.
[0032]
In the first configuration access, a configuration write is executed for the register number “10h”. The data to be written is an address at which data is collected, and the address mapping in the PCI card 102 is as shown in FIG. For example, if the address is “00000000h”, the data collection control unit 109 collects the data of the first register of the internal register 108. In addition, the data collection control unit 109 collects data from the PCI bus tracer 106 when the address specified by the configuration write is “00100000h to 001FFFFFh”, and collects data from the internal bus tracer 110 when the address is “00200000h to 002FFFFFh”. Data is collected. If “00300000h to 012FFFFFh”, data is collected from the local memory 113, and if “FFFFFE00h to FFFFFFFFh”, data is collected from the MPU 114. These collected data are stored in the register with the register number “10h”.
[0033]
In the second configuration access, a configuration read is executed for the register number “10h”. In this read, the data collection control unit 109 replies the data collected by the first configuration write to the Config access control unit 104. The Config access control unit 104 outputs the collected data to the PCI bus 101 via the PCI bus interface control unit 103.
[0034]
On the other hand, if the transaction received from the PCI bus 101 is a normal transaction, for example, a memory read, the PCI bus interface control unit 103 transfers control to the normal access control unit 105, and the normal access control unit 105 receives the transaction in the memory read transaction. Based on the address and the base address set as the PCI card 102, it is determined which area in the PCI card 102 is to be accessed. The address mapping in the PCI card 102 is as shown in FIG. For example, if the memory read is an access to the internal register area, the normal access control unit 105 accesses the internal register 108. If the memory read is an access to the local memory area, the normal access control unit 105 sends an instruction to the internal bus interface control unit 111. An instruction is issued to access the local memory 113 via the internal bus 112.
[0035]
In the address mapping shown in FIG. 4, even if the inside of the PCI card 102 is not actually mapped, the address mapping is virtually performed as shown in FIG. It is also possible to operate according to the address mapping.
[0036]
Next, a PCI bus system including the above-described PCI card will be described. FIG. 5 is a block diagram illustrating a configuration example of a PCI bus system including the PCI card illustrated in FIG. In this PCI bus system, a CPU 1, a memory 2, and a PCI host (bridge) 4 are connected to a local bus 3, and a PCI card 102 is connected to the PCI host (bridge) 4 via a PCI bus 101. . Here, a plurality of PCI cards 102 may be provided.
[0037]
The CPU 1 controls the operation of the entire system, and the control is performed in accordance with various programs stored in the memory 2 in advance. The memory 2 is provided with a program for controlling the PCI card 102, ie, a device driver, as one of the programs. The device driver performs the original operation of the PCI card 102 and the data at the time of failure as described later. The collection operation is controlled.
[0038]
FIG. 6 is a flowchart illustrating an example of a data collection operation when a failure occurs in the PCI card 102 in the PCI bus system in FIG. Hereinafter, the data collection operation when a failure occurs will be described with reference to FIG.
[0039]
First, when a failure is detected in the PCI card 102 (step S10), the PCI card 102 notifies the device driver of the occurrence of the failure by a method of generating an interrupt to the PCI bus 101 (step S11). Upon receiving the notification of the occurrence of the failure from the failed PCI card 102 (step S12), the device driver collects data in the PCI card 102 in order to collect failure information for the failed PCI card 102. At the same time as instructing (step S13), at the time of the instructing, an address for data collection is notified by a configuration write (step S14). On the side of the PCI card 102 where the failure has occurred, the data collection control unit 109 collects the data of the specified address (step S15). Next, the device driver executes a configuration read (Step S16). On the PCI card 102 side in which the failure has occurred, the data collected by the data collection control unit 109 is sent out onto the PCI bus 101 via the PCI bus interface control unit 103 in response to the configuration read (step S17). . The device driver stores the data transmitted on the PCI bus 101 as failure information, for example, in the memory 2 (step S18).
[0040]
When performing further data collection, the device driver notifies the address at which data collection is to be performed again by the configuration write, and the above-described processing in steps S14 to S18 is repeated. When all necessary data has been collected, the data collection operation is completed (step S19).
[0041]
As described above, in the PCI device of the present embodiment, when the Config access control unit 104 receives a configuration access for instructing data collection from the PCI bus 101 to the PCI card 102 via the PCI bus interface control unit 103, the configuration access control unit 104 follows the instruction. The data stored in the PCI bus tracer 106 and the local memory 113 is collected, and the collected data is output to the PCI bus 101. With this operation, even if a failure such as the MPU 114 in the PCI card 102 being hung up and stopped has occurred, the PCI card 102 is accessed by the configuration access, which is the most reliable and safe PCI bus transaction. It is possible to collect data within.
[0042]
The configuration access on the PCI bus 101 is performed by specifying the target PCI device by the IDESL signal defined in the PCI bus specification even when the PCI device is not set. Even if the information on the PCI bus operation is not set properly due to not only the failure of the above PCI card 102 but also the malfunction of the software such as the OS and the driver, the data in the PCI card 102 is similarly collected. It becomes possible.
[0043]
Using the above configuration access does not render the OS inoperable. This is because the configuration access is originally used as a resource check means for confirming whether a PCI device is connected when the PCI bus is initialized, and the configuration access is performed for a resource for which it is unknown whether the PCI device is connected. If the PCI device does not respond to the configuration access and the PCI host forcibly aborts the configuration access, a fatal error will occur. Because it must not be. Therefore, in this embodiment, even when the information related to the PCI bus is not set, the data in the PCI device can be collected as it is. Also, even if the PCI bus interface control unit 103 fails to respond to a PCI transaction due to a failure, the data can be reliably transmitted from the PCI device without causing a serious problem to stop the system. It is possible to collect.
[0044]
(Other Embodiment 1)
In the above embodiment, the device unique area of the PCI configuration space used in the data collection control unit 109 is only the register at the address “40h”. Therefore, every time data of 32 bits (that is, 4 bytes) is collected, address setting (notification of an address at which data collection is performed by a device driver) is required. That is, two configuration accesses are required to collect 4 bytes of data.
[0045]
FIG. 7 is a schematic diagram illustrating an example of a register structure of a device unique area in a PCI configuration space used in the data acquisition control unit 109. In this example, the address "43h to 40h" of the device-specific area is an address setting register for setting the head of the address for data collection, and 64 bytes of data are collected from the address set by this address setting register. The collected data is stored in the data collection register group of “44h to 83h”. By sequentially reading the configuration of the 16 registers from the address “44h to 83h”, data of 64 bytes can be collectively collected.
[0046]
In the example shown in FIG. 1 described above, 32 configuration accesses are required to collect 64 bytes of data. However, the register structure shown in FIG. 64 bytes of data can be collected by configuration access.
[0047]
In the example of FIG. 7, the data length collectively collected is 64 bytes, but the data length can be any size from 4 bytes to 192 bytes. However, when the data length is 192 bytes, it is necessary to store the collected data in the address setting register as in the above-described embodiment.
[0048]
(Other Embodiment 2)
In the example of FIG. 7 described above, it is necessary to fix the size of the data collection register group storing the collected data to a predetermined size. In that case, it is not possible to collect only the necessary data. In the present embodiment, the following register structure of the device-specific area is adopted in order to collect data of a required size.
[0049]
FIG. 8 is a schematic diagram showing an example of a register structure of a device unique area of a PCI configuration space used in the data collection control unit 109. In this example, the address "43h to 40h" of the device unique area is an address setting register for setting the head of the address for data collection, and the address "47h to 44h" is a collection for setting the size of data to be collected. The data length setting register is used to collect data of the size set in the collected data length setting register from the address set in the address setting register and store the collected data in a data collection register group from address "48h to XXh". Is stored. With this configuration, it is possible to collect data of a size as required.
[0050]
(Other Embodiment 3)
In the example of FIG. 8 described above, the size of the data to be collected is indicated by providing the collection data length setting register. However, the size of the data is also indicated by using the function number in FIG. Can be.
[0051]
FIG. 9 is a schematic diagram illustrating an example of a register structure in the data collection control unit 109. In this example, a function number holding register is provided in addition to a register as a device unique area in the PCI configuration space. The address "43h to 40h" of the device-specific area is an address setting register for setting the head of the address at which data is collected, and is specified by the data stored in the function number holding register from the head address set in the address setting register. Data of the size is collected, and the collected data is stored in a data collection register group of addresses “44h to XXh”.
[0052]
In the case of this embodiment, first, a configuration write for setting an address for performing data collection in the address setting register is executed, and the function number of the address phase at this time is stored in the function number holding register. . Data written in the data phase is stored in the address setting register.
[0053]
The function number is 3 bits, and thus the function number holding register stores 3-bit data. That is, it is possible to indicate the data length of eight patterns with 3-bit data. For example, data lengths of 4, 8, 16, 32, 64, 96, 128, and 192 bytes can be set. As a result, it is possible to freely set the collection data length using the function number, and to collect data of a required size.
[0054]
【The invention's effect】
As described above, according to the present invention, data in a PCI device can be reliably collected without causing a system error regardless of the state of the PCI device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a PCI card which is one embodiment of a PCI device of the present invention.
FIG. 2 is a schematic diagram showing an example of an address map of a configuration space in a PCI bus specification applied to the present invention.
FIG. 3 is a schematic diagram showing a definition of an address phase of an AD (address / data) line in a configuration access conforming to a PCI bus specification applied to the present invention.
FIG. 4 is a schematic diagram showing an example of an address space mapped in the PCI card shown in FIG. 1;
5 is a block diagram illustrating a configuration example of a PCI bus system including the PCI card illustrated in FIG.
6 is a flowchart showing an example of a data collection operation in the PCI bus system shown in FIG.
FIG. 7 is a schematic diagram showing an example of a register structure of a device unique area of a PCI configuration space used in the data acquisition control unit shown in FIG.
FIG. 8 is a schematic diagram showing an example of a register structure of a device unique area in a PCI configuration space used in the data acquisition control unit shown in FIG.
FIG. 9 is a schematic diagram showing an example of a register structure in the data collection control unit 109 shown in FIG.
FIG. 10 is a block diagram showing a schematic configuration of a LANP system described in Japanese Patent Application Laid-Open No. 10-21152.
FIG. 11 is a block diagram showing an example of a PCI expansion card shown in FIG.
[Explanation of symbols]
1,200 CPU
2 memory
3 Local bus
4 PCI host
101, 211 PCI bus
102 PCI card
103 PCI bus interface control unit
104 Config access control unit
105 Normal access control unit
106 PCI Bus Tracer
107 Config register
108 Internal register
109 Data collection control unit
110 Internal bus tracer
111 Internal bus interface control unit
112 internal bus
113 Local memory
114,301 MPU
201 MEM
202 PCL
203 NIC
204 OLA
210 System bus
212 IO interface
220 LANP
221 Host computer
222 LAN line
300 PBC
302 LM
310 CFG

Claims (13)

A PCI device connected to a PCI bus and having a configuration space including a device-specific area in which registers can be arbitrarily set,
A register defined as the device-specific area is mounted, and upon receiving a data collection instruction, data collection control means for collecting data specified according to the contents of the register,
Upon receiving a configuration access to the device-specific area via the PCI bus, the device sends the data collection instruction to the data collection control unit, and the data collection control unit collects the data in response to the data collection instruction. A configuration access control means for transmitting data onto the PCI bus. Configuration access consists of two accesses: configuration write and configuration read.
In the data collection means, the configuration write writes an address to perform data collection to a register of a predetermined number of bits from a predetermined address of the device-specific area, and collects data according to the written address. The collected data is stored in the register of the predetermined number of bits, and the data stored in the register of the predetermined number of bits is transmitted to the configuration access control means by the configuration read. The PCI device according to claim 1, wherein Configuration access consists of two accesses: configuration write and configuration read.
The data collection means writes, by the configuration write, a head address of an address at which data collection is to be performed to an address setting register of a predetermined address in the device unique area, and data of a predetermined byte from the written head address is written. Collected, the collected data is stored in a register group extending over a plurality of addresses of the device-specific area, and the configuration read is performed by sequentially reading out the data stored in the register group by the configuration read. The PCI device according to claim 1, wherein the PCI device is configured to be transmitted to the PCI device. The data collection means has a size specification register for specifying the size of the collected data at a predetermined address of the device-specific area, and the size specified by the size specification register from the head address written in the set address of the register 4. The PCI device according to claim 3, wherein data of a data size is collected and stored in a register group. The data collection means has a function number holding register in which a function number defined by a predetermined bit of a configuration cycle, which is an operation performed on the configuration space, is stored. 4. The PCI device according to claim 3, wherein data of a data size specified by data stored in the function number holding register is collected from an address and stored in a register group. . A configuration register that implements a register defined as a header area of the configuration space,
2. The PCI according to claim 1, wherein the configuration access control means is configured to access the configuration register when receiving a configuration access to the header area via a PCI bus. device. PCI bus interface control means for controlling data transmission via a PCI bus;
Normal access control means for controlling a predetermined normal access operation,
When the PCI bus interface control means receives a configuration access via the PCI bus, the PCI bus interface control means instructs the configuration access means to execute an operation according to the content of the configuration access, and sets the PCI bus to When a PCI bus transaction other than the configuration access is received via the CPU, the normal access control means is instructed to execute a normal access operation according to the content of the PCI bus transaction. The PCI device according to claim 1, wherein A PCI bus system comprising: the PCI device according to claim 1; and a PCI bus to which the PCI device is connected. A data collection method performed in a PCI bus system in which a PCI device having a configuration space including a device-specific area in which registers can be arbitrarily set is connected to a PCI bus,
Performing a configuration access to instruct the PCI device to collect data using the device-specific area;
A step of the PCI device collecting specified data according to the configuration access, and transmitting the collected data to the PCI bus. Configuration access consists of two accesses, configuration write and configuration read,
Writing, by the configuration write, an address at which data collection is to be performed to a register having a predetermined number of bits from a predetermined address in a device-specific area mounted in the PCI device;
The PCI device collecting data according to the address at which the written data is to be collected, and storing the collected data in the register having the predetermined number of bits;
10. The data collection method according to claim 9, further comprising: reading data stored in the register having the predetermined number of bits by the configuration read. Configuration access consists of two accesses, configuration write and configuration read,
Writing, by the configuration write, a head address of an address at which data collection is to be performed to an address setting register of a predetermined address in a device unique area mounted in the PCI device;
The PCI device collecting data according to a head address written in the address setting register, and storing the collected data in a register group extending over a plurality of addresses in the device-specific area;
10. The data collection method according to claim 9, further comprising: reading out data stored in the register group by the configuration read. Setting a register at a predetermined address of the device-specific area as a size designation register, and setting a size of data to be collected in the size designation register;
The step of collecting data by the PCI device is a step of collecting data of a data size specified by the size specifying register from a head address written in a setting address of the register, and storing the collected data in a register group. The data collection method according to claim 11, wherein: Storing a function number defined by a predetermined bit of a configuration cycle, which is an operation performed on the configuration space, in a function number holding register implemented in the PCI device;
The step of collecting data by the PCI device collects data of a data size specified by the data stored in the function number holding register from a head address written in a setting address of the register, and transfers the collected data to the device. 12. The data collection method according to claim 11, wherein the data is stored in a register group covering a plurality of addresses of the unique area.

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