JP3582974B2 - Semiconductor memory device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a circuit configuration of a semiconductor memory device having a plurality of memory cells, and particularly to a read-only semiconductor memory device such as a mask ROM or an EPROM.
[0002]
[Prior art]
A ROM (Read Only Memory) for writing data during a manufacturing process of a memory IC is generally called a mask ROM. Some mask ROMs are called virtual ground type mask ROMs.
[0003]
FIG. 9 is a part of a circuit diagram showing the internal configuration of the virtual ground mask ROM. The mask ROM shown in FIG. 9 includes a cell block 1 composed of a plurality of memory cells arranged between word lines WL0 to WL31, a column line CLn and a bit line BLn, and memory cells selected by logic of select lines SL1 to SL3. , A column selector 3 for selecting a bit line BLn, and a sense amplifier 4 for amplifying data read from a memory cell.
[0004]
9 are provided for each bit, and each sense amplifier 4 amplifies the cell data read from the corresponding cell block 1. Each sense amplifier 4 includes a load circuit including a transistor Q1, an output control circuit 41, and a differential amplifier 42. The load circuit Q1 outputs a voltage OUT according to cell data, and the differential amplifier 42 The difference voltage between the output OUT of the circuit Q1 and the reference voltage VREF is amplified.
[0005]
Selection of a memory cell in each cell block 1 is performed by a column selector 3 and a cell selection circuit 2 provided above and below the memory cell. The data stored in the selected memory cell passes through the cell selection circuit 2 and the column selector 3 and is then input to the sense amplifier 4 through the bit line BL.
[0006]
For example, when reading the data of the memory cell m1 in FIG. 9, the block selection lines SL1 to SL3 in FIG. 9 are set to the high level, the column line CLn is set to the low level, and the word connected to the memory cell m1 is read. The line WL0 is set to a high level. As a result, data read from the memory cell m1 is input to the sense amplifier 4 through the cell selection circuit 2 and the column selector 3. The sense amplifier 4 amplifies a difference voltage between data from a memory cell and a reference voltage VREF. As described above, since the reading of the memory cell is performed with the column line set to the ground level, the circuit of FIG. 9 is called a virtual ground type.
[0007]
[Problems to be solved by the invention]
By the way, there are three typical data write methods for the mask ROM: (1) a diffusion layer program method, (2) an ion implantation program method, and (3) a contact hole program method.
[0008]
FIG. 10 is a plan view of a mask ROM of the ion implantation program system. In the mask ROM shown in FIG. ⁺ A polysilicon layer 102 is formed in a direction substantially orthogonal to the layer 101, and data is written by implanting impurity ions into a channel region 103 indicated by a dotted line in FIG. In a state where ions are not implanted, the memory cell is of an enhancement type, and the threshold voltage is increased by ion implantation. The state where no ion implantation is performed corresponds to data “0”, and the state where ion implantation is performed corresponds to data “1”.
[0009]
In order to shorten the time until the memory IC is supplied from the producer to the end user (turn-around time), it is desirable to write data at a later stage of the manufacturing process. For this reason, in a mask ROM of the ion implantation program system, after the gate electrode is formed, it is general that ions are implanted into the channel region using the gate electrode as a mask.
[0010]
However, a part of the implanted impurity ions penetrate deeply into the substrate other than the channel region 103, damaging the silicon atom crystal constituting the substrate, and as a result, leak current flows to the memory cell. It has been pointed out before. Therefore, it is impossible to increase the acceleration voltage at the time of ion implantation to a certain level or more, and it is also impossible to increase the threshold voltage VTH of the memory cell to a certain level or more. For example, in the case of a mask ROM having a power supply voltage of 5 V, the threshold voltage VTH can be increased only to about 5 V. At the time of data reading, since the power supply voltage is applied to the selected word line, the threshold voltage VTH of the memory cell into which the ions are implanted and changed to the “1” state is temporarily set to 5 V, and the power supply voltage is set to 5 V or more. Then, a current corresponding to the power supply voltage flows through the “1” memory cell, and the bit line potential does not rise linearly with respect to the power supply voltage. That is, when the power supply voltage is increased, the operation margin on the high level side of the sense amplifier is lost.
[0011]
FIG. 11 is a diagram showing a change in the input voltage of the differential amplifier 42 in the sense amplifier 4 when the power supply voltage is changed. The horizontal axis represents the power supply voltage Vcc, and the vertical axis represents the input voltage level of the differential amplifier 42. Is represented. A curve A in FIG. 11 indicates an input voltage level of the differential amplifier 42 at a high level, a curve B indicates an input voltage level at a low level, and a curve C indicates a voltage level of the reference voltage VREF input to the differential amplifier 42. I have.
[0012]
As shown, when the power supply voltage Vcc exceeds 5 V, the input voltage level of the differential amplifier 42 at the time of the high level starts to gradually decrease, and when the power supply voltage Vcc is further increased, it becomes lower than the reference voltage VREF. . The differential amplifier 42 amplifies the voltage difference between the voltage input via the bit line BL and the reference voltage VREF, so that the input voltage from the bit line BL intersects with the reference voltage VREF as shown in FIG. Then, a normal sense operation cannot be performed.
[0013]
As described above, the conventional mask ROM of the ion implantation program system has a problem that the operation when the power supply voltage Vcc is increased becomes unstable because the threshold voltage cannot be increased to a certain degree or more.
[0014]
Such a problem is not a problem peculiar to the mask ROM of the ion implantation program system. For example, even in an EPROM or EEPROM in which data is written by injecting electrons into the floating gate, the threshold voltage cannot be made too high due to reliability problems.
[0015]
On the other hand, with the advance of microfabrication technology, various memories including a mask ROM tend to be reduced in size and increased in capacity. Along with this, the wiring width and the wiring interval in the memory chip become narrower, and the memory chip becomes more susceptible to coupling noise, and the voltage level of the bit line BL at the time of changing the column address is more likely to decrease.
[0016]
FIG. 12 is a diagram showing how the voltage level of the bit line BL decreases in accordance with a change in the voltage of the column line CLn in the virtual ground type mask ROM as shown in FIG. The horizontal axis represents time, the vertical axis represents voltage level, curve P represents a bit line voltage waveform, curve Q represents a column line voltage waveform, and curve R represents an input voltage waveform of the sense amplifier 4. .
[0017]
When the column address changes, the voltage of the column line changes accordingly as shown by the curve Q in FIG. 12. At this time, the voltage of the bit line BL is temporarily dragged by the voltage change of the column line due to coupling noise. Will change significantly. After the voltage of the bit line BL once drops, it returns to the original voltage level. However, the load resistance in the sense amplifier 4 is formed by the transistor Q1 having a size corresponding to the current flowing through the memory cell. Is considerably large, and it takes a considerable time for the voltage of the bit line BL to return to the original level, which results in preventing high-speed operation.
[0018]
The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor memory device capable of preventing a voltage drop when a memory cell outputs a high level. It is another object of the present invention to provide a semiconductor memory device capable of performing a high-speed operation by quickly compensating for a voltage drop of a sense amplifier output due to coupling noise.
[0019]
In order to solve the above-described problem, the present invention provides a cell block including a plurality of memory cells, a cell selection unit that controls reading of a memory cell in the cell block, and an output voltage of the cell selection unit. In a semiconductor memory device having a sense amplifier for amplifying, a dummy cell block including one or more memory cells, and a dummy cell selection for controlling to read data of a memory cell selected from the dummy cell block to a dummy bit line. And a dummy sense amplifier that controls an input voltage of the sense amplifier by flowing a current proportional to a current flowing from the power supply voltage terminal to the dummy bit line to the input side of the sense amplifier.
[0020]
The invention of claim 1 will be described with reference to FIG. 1, for example. A "cell block" is a cell block 1, a "cell selection unit" is a cell selection circuit 2 and a column selector 3, and a "sense amplifier" is a sense amplifier. 4, the “dummy cell block” corresponds to the dummy cell block 21, the “dummy cell selection unit” corresponds to the dummy cell selection circuit 22 and the dummy column selector 23, and the “dummy sense amplifier” corresponds to the dummy sense amplifier 24.
[0021]
The present invention further includes a cell block including a plurality of memory cells, a cell selection unit that controls reading of the memory cells in the cell block, and a sense amplifier that amplifies an output voltage of the cell selection unit. A plurality of dummy cell blocks each including one or more memory cells, and any one of the plurality of dummy cell blocks according to a change in a column address designating a read address of the memory cell. A dummy cell block selecting unit, a dummy cell selecting unit for controlling to read data of a memory cell selected from the dummy cell block selected by the dummy cell block selecting unit to a dummy bit line, and a dummy bit line from a power supply voltage terminal. A current proportional to the current flowing to the input side of the sense amplifier, A dummy sense amplifier for controlling an input voltage of a sense amplifier, wherein the dummy cell block, the dummy cell block selecting unit, the dummy cell selecting unit, and the dummy sense amplifier are provided corresponding to one or more of the sense amplifiers. The dummy sense amplifier performs control to increase the output voltage of the corresponding sense amplifier according to the amount of change in the input voltage of the dummy sense amplifier when the column address changes.
[0022]
The invention of claim 3 will be described with reference to, for example, FIG. 4. "Cell block" corresponds to cell block 1, "cell selection section" corresponds to cell selection circuit 2 and column selector 3, and "sense amplifier" corresponds to sense amplifier. 4, the "dummy cell block" is in the dummy cell block 21, the "dummy cell block selector" is in the transistors Q4 and Q5, the "dummy cell selector" is in the dummy cell selector 22 and the dummy column selector 23, and the "dummy sense amplifier" is Each corresponds to the sense amplifier 24.
[0023]
The invention according to claim 5 will be described with reference to FIGS. 1 and 4, for example. The "first transistor" corresponds to the transistor Q2, and the "second transistor" corresponds to the transistor Q3.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor memory device to which the present invention is applied will be specifically described with reference to the drawings.
[0025]
[First Embodiment]
In the first embodiment, the operation margin at the time of high-level output of a mask ROM, EPROM, or the like is expanded.
[0026]
FIG. 1 is a circuit diagram of a first embodiment of a semiconductor memory device according to the present invention, and shows a part of an internal configuration of a mask ROM. In FIG. 1, the same components as those of the conventional mask ROM shown in FIG. 9 are denoted by the same reference numerals, and the following description will focus on the differences.
[0027]
The mask ROM of FIG. 1 includes a main cell circuit 11 and a dummy circuit 12. The cell circuit 11 actually functions as a memory, and is provided for each bit. On the other hand, the dummy circuit 12 controls the output voltage of the sense amplifier 4 in the cell circuit 11.
[0028]
Similar to the conventional mask ROM shown in FIG. 9, the present cell circuit 11 includes a cell block 1 composed of a plurality of memory cells, a cell selection circuit 2 for selecting a memory cell in the cell block 1, and a cell block 1 A column selector 3 for selecting one of the column lines CL1 to CLn, and a sense amplifier 4.
[0029]
The sense amplifier 4 in the cell circuit 11 includes an output control circuit 41, a load circuit including a transistor Q1, and a differential amplifier 42, like the sense amplifier 4 in FIG. The output control circuit 41 supplies the cell data that has passed through the column selector 3 to the load circuit Q1 only at the time of data reading in accordance with the logic of the signal PD synchronized with the chip enable. The differential amplifier amplifies a difference voltage between the output OUT of the load circuit Q1 and the reference voltage VREF.
[0030]
On the other hand, the dummy circuit 12 shown in FIG. 1 is composed of substantially the same circuit as the present cell circuit 11, and includes a dummy cell block 21 composed of one or more memory cells and a dummy cell selection circuit 22 for selecting a memory cell in the dummy cell block 21. And a dummy column selector 23 for selecting the column lines DCL1 to DCLn in the dummy cell block 21, and a dummy sense amplifier 24.
[0031]
All the memory cells in the dummy cell block 21 are ion-implanted in advance, and each memory cell is set to a state in which data has been written (a state with a high threshold value corresponding to data "1"). Also, the transistors in the dummy cell selection circuit 22 and the dummy column selector 23 are always on so that the bit line DBL in the dummy circuit 12 is always at a high level, that is, data "1" is always read. Is set to
[0032]
The dummy sense amplifier 24 in FIG. 1 has an output control circuit 43 and a load circuit Q2 having the same configurations as the output control circuit 41 and the load circuit Q1 in the sense amplifier 4, and includes a PMOS transistor Q3 instead of a differential amplifier. Have. The output OUTD of the load circuit Q2 is applied to the gate terminal of the transistor Q3, the source terminal is connected to the power supply terminal Vcc, and the drain terminal is connected to the output terminal OUT of the load circuit Q1 in the cell circuit 11. .
[0033]
The transistors Q2 and Q3 in the dummy sense amplifier 24 form a current mirror circuit. When the gate widths of the transistors Q1 to Q3 are W1 to W3 and the gate lengths are L1 to L3, respectively, the following ( If the condition of the expression 1) is satisfied, the drain currents flowing through the transistors Q2 and Q3 become equal to each other.
[0034]
W1 / L1 = W2 / L2 = W3 / L3 (1)
By the way, the present embodiment aims at compensating for a drop in the output voltage of the sense amplifier 4 at the time of high-level output by the dummy circuit 12. It must be accurately detected in the circuit 12. For this reason, it is desirable that the number of transistors connected between the power supply terminal Vcc and the ground terminal be the same in the cell circuit 11 and the dummy circuit 12. However, it is not necessary to make the total number of memory cells coincide with each other, and from the viewpoint of reducing the element area, the number of memory cells in the dummy cell block 21 may be reduced.
[0035]
FIG. 2 is a diagram showing how the input voltage of the differential amplifier 42 in the sense amplifier 4 changes according to the power supply voltage Vcc, and shows an example in which the threshold value is set to 5V. In the figure, a solid line A 'is an input voltage waveform of the differential amplifier 42 at a high level, a solid line B' is an input voltage waveform of the differential amplifier 42 at a low level, and a solid line C is a voltage waveform of a reference voltage VREF. Are the input voltage waveforms of the conventional differential amplifier 42 having no dummy circuit 12.
[0036]
Hereinafter, the operation of the mask ROM of the first embodiment will be described with reference to FIGS. Since the output of the dummy cell block 21 in the dummy circuit 12 provided for each sense amplifier 4 is always at a high level, and all the transistors in the dummy column selector 23 and the dummy cell selection circuit 22 are always on, the dummy sense A high level signal is always input to the amplifier 24. Since the power supply voltage Vcc is applied to one end of the load circuit Q2 in the dummy sense amplifier 24 and the output of the column selector 23 is applied to the other end, a current I1 according to the voltage difference between both ends flows through the load circuit Q2.
[0037]
When the power supply voltage Vcc becomes higher than the threshold voltage, the voltage of the bit line BL in the present cell circuit 11 starts to decrease, and accordingly, the bit in the dummy circuit 12 constituted by a circuit similar to the present cell circuit 11 The voltage on line DBL also begins to drop.
[0038]
When the voltage of the bit line DBL in the dummy circuit 12 decreases, the current I1 flowing through the transistor Q2 constituting the load circuit increases, and the current I2 flowing through the transistor Q3 increases accordingly. Here, if the gate width and gate length of each of the transistors Q1 to Q3 are set so as to satisfy the relationship of the above equation (1), the currents I1 and I2 flowing through the transistors Q2 and Q3 become equal to each other, and the dummy circuit 12 The input voltage of the cell amplifier 4 in the present cell circuit 11 rises by the amount of the voltage drop. As a result, as shown by the solid line A 'in FIG. 2, even when the power supply voltage exceeds 5 V, the input voltage of the differential amplifier 42 does not decrease, and the output voltage of the differential amplifier 42 is higher than that of the conventional circuit (solid line A in FIG. 2). Operating margin is increased.
[0039]
According to the present embodiment, as shown by the solid line B 'in FIG. 2, the input voltage of the differential amplifier 42 at the time of low level output slightly increases, but the voltage-current characteristic of the transistor Q1 has a square curve. Therefore, the voltage rise on the high level side is much larger than the voltage rise on the low level side, and the voltage rise on the low level side poses almost no problem in practical use.
[0040]
If the ratios of the gate widths and the gate lengths of the transistors Q2 and Q3, W2 / L2 and W3 / L3, are appropriately set, the currents I1 and I2 corresponding to the ratios flow. In addition, a desired margin can be provided on the low level side.
[0041]
In the above, a mask ROM in which data is written by ion implantation has been described as an example. However, the present invention can be applied to various types of semiconductor memories in which the threshold voltage cannot be set too high due to limitations in the manufacturing process.
[0042]
For example, FIG. 3 shows an example in which the present invention is applied to an EPROM, and shows a circuit inside the EPROM. The EPROM of FIG. 3 includes the present cell circuit 11a and a dummy circuit 12a, similarly to FIG. 1, and the configuration of the dummy circuit 12a is substantially the same as that of FIG. Data is written in advance to all the memory cells constituting the dummy cell block 21a in the dummy circuit 12a. Data writing to the EPROM is performed by applying a high voltage to the control gate and injecting electrons in the channel region into the floating gate.
[0043]
Also in the EPROM of FIG. 3, when the power supply voltage Vcc becomes higher than the threshold value and the voltage of the bit line BL in the cell circuit 11a starts to decrease, the current I1 flowing through the load circuit Q2 in the dummy cell circuit 12a is reduced. Since the current I2 flowing through the transistor Q3 increases accordingly, the input voltage of the differential amplifier 42 in the cell circuit 11a is increased.
[0044]
[Second embodiment]
The second embodiment is to shorten the voltage drop period of the bit line when the column address changes.
[0045]
FIG. 4 is a circuit diagram of a second embodiment of the semiconductor memory device according to the present invention, and shows a part of the internal configuration of the mask ROM.
[0046]
The mask ROM of FIG. 4 includes the present cell circuit 11 and a dummy circuit 12 '. The present cell circuit 11 is configured by a circuit similar to that of FIG. 1 and is provided for each sense amplifier 4. On the other hand, the dummy circuit 12 'is provided corresponding to the main cell circuit 11, and has a dummy cell block 21, a dummy cell selection circuit 22', a dummy column selector 23, and a dummy sense amplifier 24 in common with FIG. However, this is different from FIG. 1 in that two dummy cell blocks 21 are provided.
[0047]
Each dummy cell block 21 includes one or more memory cells, but does not necessarily need to include the same number of memory cells as the cell blocks 1 in the cell circuit 11.
[0048]
In the dummy cell selection circuit 22 ', a transistor Q4 for selecting whether to supply the output of the dummy cell block 21 arranged on the left side of FIG. 4 to the dummy column selector 23, and a dummy cell block 21 arranged on the right side And a transistor Q5 for selecting whether to supply an output to the dummy column selector 23 or not. The LS signal and the RS signal are applied to the gate terminals of the transistors Q4 and Q5, respectively, as described later.
[0049]
The dummy sense amplifier 24 includes an output control circuit 43, a transistor Q2 forming a load circuit, and a PMOS transistor Q3, as in FIG. 1, and the output OUTD of the load circuit Q2 is applied to the gate terminal of the transistor Q3. 1 in that the power supply voltage Vcc is applied to the source terminal of the transistor Q3, and the output terminal OUT of the load circuit Q1 is connected to the drain terminal.
[0050]
FIG. 5 is a block diagram of the control signal output circuit 51 that outputs the above-described LS signal and RS signal. The control signal output circuit 51 of FIG. 5 is provided in a mask ROM, and includes an ATD signal generation circuit 52 and a counter circuit 53.
[0051]
FIG. 6 is a circuit diagram showing the internal configuration of the ATD signal generation circuit 52. The circuit of FIG. 6 includes a pulse generator 61 for detecting a logical change of each address terminal, a NOR gate G1, and an inverter INV1. The pulse generator 61 is provided for each of the address terminals A1 to An constituting a column address, and outputs a pulse for a predetermined period when the logic of the address terminal changes when the signal PD synchronized with the enable signal is at a high level. I do. The inverter INV1 outputs a high-level pulse (hereinafter, referred to as an ATD signal) for a predetermined period when any one of the address terminals A1 to An constituting the column address changes logic.
[0052]
FIG. 7 is a circuit diagram showing the internal configuration of the counter circuit 53. The circuit shown in FIG. 7 includes transfer gates TG1 to TG4 and inverters INV2 to INV9, and outputs an LS signal and an RS signal whose logics are inverted from each other.
[0053]
In the circuit of FIG. 7, for example, when the LS signal is at a low level and the ATD signal is at a low level, the transfer gates TG1 and TG4 of FIG. 7 are turned on, and points a and e shown in FIG. Goes high. When the ATD signal goes high in this state, the transfer gates TG1 and TG4 are turned off, and the transfer gates TG2 and TG3 are turned on instead. As a result, the points b and c shown in the figure change to low level and the point e changes to high level, and accordingly, the LS signal changes to high level and the RS signal changes to low level.
[0054]
Next, when the ATD signal becomes low level, the transfer gates TG2 and TG3 are turned off, the transfer gates TG1 and TG4 are turned on, and the logic of the LS signal and the RS signal does not change, but the points a and b become high level. Become. Next, when the ATD signal goes high again, the transfer gates TG2 and TG3 turn off, the transfer gates TG1 and TG4 turn on, the LS signal changes to low level, and the RS signal changes to high level.
[0055]
FIG. 8 is an operation timing chart of the mask ROM of FIG. Hereinafter, the operation of the mask ROM of FIG. 4 will be described with reference to FIG. When the column address changes at time T1 in FIG. 8, the ATD signal output from the ATD signal generation circuit 52 in FIG. 6 goes high for a predetermined period. In response, the logic of the LS signal and the RS signal output from the counter circuit 53 in FIG. 7 is inverted.
[0056]
As a result, one of the transistors in the dummy cell selection circuit 22 turns on. For example, between times T1 and T2 in FIG. 8, the LS signal is at a high level, so that the transistor Q4 in FIG. 4 to which the LS signal is applied turns on, and the output of the dummy cell block 21 connected to the transistor Q4 is It is supplied to the bit line DBL.
[0057]
Since the dummy circuit 12 'is constituted by a circuit substantially similar to the present cell circuit 11, when the voltage of the bit line BL of the present cell circuit 11 decreases due to a change in the column address, the dummy circuit 12' , The voltage of the bit line DBL also drops. When the voltage of the bit line DBL in the dummy circuit 12 'decreases, the current I1 flowing through the transistor Q2 increases, and accordingly, the current I2 flowing through the transistor Q3 forming a current mirror circuit with the transistor Q2 also increases. Then, the output level of the load circuit Q1 in the cell circuit 11 increases.
[0058]
Next, at time T2 in FIG. 8, when the column address changes again, the ATD signal output from the ATD signal generation circuit 52 in FIG. 6 becomes high level for a predetermined period, and accordingly, the counter circuit 53 in FIG. , LS signal and RS signal are inverted and output. Therefore, the transistor Q5 in the dummy circuit 12 'in FIG. 4 is turned on, and the output of the dummy cell block 21 connected to the transistor Q5 is supplied to the dummy sense amplifier 24. Then, when the voltage of the bit line DBL decreases due to a change in the column address, the current I1 flowing through the transistor Q2 increases accordingly, and control is performed to increase the output of the transistor Q2 in the cell circuit 11.
[0059]
As described above, in the second embodiment, the dummy circuit 12 having substantially the same configuration as the present cell circuit 11 is provided, and two sets of dummy cell blocks which are alternately selected each time the column address changes are provided in the dummy circuit 12 '. When the voltage of the bit line BL in the cell circuit 11 is reduced due to the change in the column address, the voltage of the bit line DBL in the dummy circuit 12 'is also reduced by substantially the same amount. Further, control is performed to increase the output level of the load circuit Q1 in the cell circuit 11 by the voltage drop of the bit line DBL in the dummy circuit 12 '. Even if the voltage of the BL decreases, the voltage can be quickly returned to the original level, and the mask ROM can operate at high speed.
[0060]
In the above-described second embodiment, the mask ROM has been described as an example. However, as other read-only memories such as an EPROM and an EEPROM become smaller, the voltage drop of the bit line BL due to the coupling noise may become a problem as the memory becomes smaller. Therefore, by providing a dummy circuit 12 'similar to that shown in FIG. 4, a voltage drop of the bit line BL can be quickly compensated.
[0061]
Further, in the above-described second embodiment, an example has been described in which two sets of dummy cell blocks 21 are provided in the dummy circuit 12 ′. Each dummy cell block 21 may be selected in order.
[0062]
The dummy cell blocks 21 in the dummy circuits 12, 12a and 12 'shown in FIGS. 1, 3 and 4 may be formed integrally with the cell block 1 in the present cell circuit 11, or It may be formed separately from one.
[0063]
【The invention's effect】
As described above in detail, according to the first aspect of the present invention, the output voltage of the sense amplifier is adjusted according to the output voltage level of the dummy cell selection unit, and the output voltage level of the sense amplifier is increased even when the power supply voltage is increased. , The operation margin at the time of high-level output can be given a margin, and the power supply voltage range in which stable operation can be performed can be expanded.
[0064]
According to the third aspect of the present invention, a decrease in the input voltage of the sense amplifier when the column address changes is detected based on the output voltage level of the dummy cell selection unit, and the output voltage of the sense amplifier is determined in accordance with the output voltage level. , The period during which the output voltage of the sense amplifier drops when the column address changes can be shortened, and the memory can operate at high speed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment of a semiconductor memory device.
FIG. 2 is a diagram illustrating a state in which an input voltage of a differential amplifier changes according to a power supply voltage.
FIG. 3 is a circuit diagram showing an internal configuration of an EPROM.
FIG. 4 is a circuit diagram of a second embodiment of the semiconductor memory device.
FIG. 5 is a block diagram of a control signal output circuit that outputs an LS signal and an RS signal.
FIG. 6 is a circuit diagram showing an internal configuration of the ATD signal generation circuit shown in FIG. 5;
FIG. 7 is a circuit diagram showing an internal configuration of the counter circuit shown in FIG. 5;
FIG. 8 is an operation timing chart of the mask ROM of FIG. 4;
FIG. 9 is a circuit diagram showing an internal configuration of a virtual ground type mask ROM.
FIG. 10 is a plan view of an ion implantation type mask ROM.
FIG. 11 is a diagram showing a change in an input voltage of a differential amplifier when a power supply voltage is changed.
FIG. 12 is a diagram showing a state where a voltage level of a bit line is reduced.
[Explanation of symbols]
1 cell block
2 cell selection circuit
3 Column selector
4 Sense amplifier
11. The cell circuit
12, 12a, 12 'dummy circuit
21 Dummy cell block
22 Dummy cell selection circuit
23 Dummy column selector
24 Dummy sense amplifier

Claims (5)

A cell block composed of a plurality of memory cells;
A cell selection unit that controls reading of memory cells in the cell block;
A sense amplifier for amplifying the output voltage of the cell selection unit,
A dummy cell block composed of one or more memory cells;
A dummy cell selection unit that performs control to read data of a memory cell selected from the dummy cell block to a dummy bit line;
A semiconductor memory device, comprising: a dummy sense amplifier for flowing a current proportional to a current flowing from a power supply voltage terminal to a dummy bit line to an input side of the sense amplifier to control an input voltage of the sense amplifier. The dummy cell block, the dummy cell selection unit, and the dummy sense amplifier are configured such that the input voltage of the dummy sense amplifier decreases by an amount substantially equal to the amount of decrease in the input voltage of the sense amplifier at the time of high level output. The semiconductor memory device according to claim 1, wherein: A cell block composed of a plurality of memory cells;
A cell selection unit that controls reading of memory cells in the cell block;
A sense amplifier for amplifying the output voltage of the cell selection unit,
A plurality of dummy cell blocks each including one or more memory cells;
A dummy cell block selecting unit that selects any one of the plurality of dummy cell blocks according to a change in a column address that specifies a read address of the memory cell;
A dummy cell selection unit that performs control to read data of a memory cell selected from the dummy cell block selected by the dummy cell block selection unit to a dummy bit line;
A dummy sense amplifier that controls the input voltage of the sense amplifier by flowing a current proportional to a current flowing from the power supply voltage terminal to the dummy bit line to the input side of the sense amplifier,
The dummy cell block, the dummy cell block selection unit, the dummy cell selection unit, and the dummy sense amplifier are provided corresponding to one or more of the sense amplifiers,
The semiconductor memory device, wherein the dummy sense amplifier performs control to increase an output voltage of the corresponding sense amplifier according to a change amount of an input voltage of the dummy sense amplifier when a column address changes. The same predetermined data is written to all the memory cells in the dummy cell block,
4. The semiconductor memory device according to claim 1, wherein said dummy cell selector always supplies a high level signal to said dummy sense amplifier. A first mirror and a second transistor forming a current mirror circuit;
The first transistor is connected on a current path from a power supply voltage terminal in the dummy sense amplifier to a dummy bit line,
5. The semiconductor memory device according to claim 1, wherein said second transistor is connected on a current path from a power supply voltage terminal to an input terminal of said sense amplifier.

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