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JP3578011B2 - Semiconductor device mounting structure - Google Patents

Semiconductor device mounting structure Download PDF

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Publication number
JP3578011B2
JP3578011B2 JP27487299A JP27487299A JP3578011B2 JP 3578011 B2 JP3578011 B2 JP 3578011B2 JP 27487299 A JP27487299 A JP 27487299A JP 27487299 A JP27487299 A JP 27487299A JP 3578011 B2 JP3578011 B2 JP 3578011B2
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JP
Japan
Prior art keywords
substrate
conductive film
anisotropic conductive
semiconductor device
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27487299A
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Japanese (ja)
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JP2001102410A (en
Inventor
勝利 古畑
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Seiko Epson Corp
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Seiko Epson Corp
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Publication date
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Priority to JP27487299A priority Critical patent/JP3578011B2/en
Publication of JP2001102410A publication Critical patent/JP2001102410A/en
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Wire Bonding (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置を異方性導電膜を用い基板に実装する半導体装置の実装構造に関する。
【0002】
【従来の技術】
従来からの公知の技術として、半導体装置の電極上に設けられた突起状の電極であるバンプと、基板上に配置されたパターンとを電気機械的に接続する構造として、異方性導電膜を利用する構造が知られている。この実装構造の従来技術を実装工程順に図5を用いて説明する。
【0003】
図5は、従来技術を示す断面図である。図5(a)において半導体装置であるところのベアチップIC1が実装される基板2の部品実装面3には複数の配線パターン4が導電材料にて形成されており、各配線パターン4の先端の表面には金メッキがなさた電極5が形成されている。また、各配線パターン4には、電極5の部分を除いてソルダーレジスト6で覆われている。
【0004】
ベアチップIC1は、所定の面7にアルミ等の導電材料で形成された複数の電極が基板の電極に対応させて配置され、各電極の表面にはバンプ8が形成されている。バンプ8はAu又はSn−Pb合金等の金属材料で形成されている。
【0005】
図5(b)は、異方性導電膜を仮圧着する工程の断面図を示す。ベアチップIC1の実装のために用いられる異方性導電膜20は絶縁性樹脂21に導電粒子22を分散させて形成されている。この異方性導電膜20はベアチップIC1の所定の面7の幅よりも大きな幅を有するテープ状に形成され、保護用テープで覆われた状態でリールに巻かれている。
【0006】
ベアチップIC1の実装に際しては、まずリールに巻かれた異方性導電膜20を保護用テープ23と共に必要な長さに切断し、基板2の部品実装面3に載せる。次に異方性導電膜20を保護用テープ23側から加熱、加圧ツール24で加熱(80度C、2秒程度)、加圧して異方性導電膜20の仮圧着を行う。この場合に、異方性導電膜20は基板2の配線パターン4や電極5を覆うようにしてベアチップIC1実装箇所に接着されるが、基板2に対する異方性導電膜20の位置ズレ等を考慮し、異方性導電膜20の面積はベアチップIC1の所定の面7の面積より大きめにするのが望ましい。また、異方性導電膜20の厚みは、バンプ8の高さより10μm程度厚いものを用いるのが望ましい。
【0007】
次に、図5(c)は半導体装置を実装している断面図を示す。基板2に接着された異方性導電膜20の保護用テープ23を剥がし、ベアチップIC1の所定の面7が異方性導電膜20に向くように設定して異方性導電膜20上にベアICチップ1を載せ、ベアチップIC1を介し異方性導電膜20を加圧(180度C、20秒程度)、加熱してベアチップIC1の実装を行う。加熱することにより、異方性導電膜20の絶縁性樹脂21が軟化し、加圧することにより押し広げられ、ベアチップIC1の所定の面7と基板2の部品実装面3の間を充填する。また、余った絶縁性樹脂21は、矢印a方向に押し出され、ベアチップIC1の側面を充填し保護する。この状態を図5(d)に示す。
【0008】
これで、基板2の部品実装面3とベアチップIC1の所定の面7とは異方性導電膜20の絶縁性樹脂21を介して接合される。また、異方性導電膜20に混在する導電粒子22はバンプ8により基板2の電極5に押圧されるので基板2とベアチップIC1とは電気的にも接続される。
【0009】
【発明が解決しようとする課題】
電子機器の多機能化に伴い、複数の半導体装置を1枚の基板に高密度に実装する、マルチチップモジュールが多く用いられているが、下記欠点を有していた。
【0010】
複数の半導体装置を1枚の基板に実装する場合、それぞれの半導体装置の実装される部分に異方性導電膜を半導体装置の数だけ貼りつけなくてはならず、生産性が著しく悪くなっていた。また、生産設備も複雑で大掛かりなものが必要となっていた。
【0011】
一方、簡略化の為に、異方性導電膜を各半導体装置の実装部分に、それぞれ貼るのではなく、一括して異方性導電膜を貼る構造もある。この場合、複数の半導体装置の間隔が充分に離れていれば問題はないが、コンパクト化、高密度化が要求される場合は、前記半導体装置を隣接して配置せざるをえない。
【0012】
この場合、まず一方の半導体装置を加熱・加圧して実装する。この時、実装時の熱が基板や基板表面に配置した配線パターンを伝導し、他方の半導体装置をこれから実装する部分に既に仮圧着されている異方性導電膜を構成する絶縁性樹脂の熱硬化を進めてしまい、他方の半導体装置を実装する際に、加熱・加圧しても絶縁性樹脂が充分軟化せず、基板と半導体装置の保持が不十分となり、バンプと基板の電極との電気的導通が確保できなくなるという、電子機器としては致命的な欠陥となるという問題がある。
【0013】
そこで、一方の半導体装置を実装する際の加熱・加圧により絶縁性樹脂の熱硬化が進まない距離までそれぞれの半導体装置を離さなくてはならず、高密度実装化の大きな妨げになっていた。
【0014】
もちろん、複数の半導体装置ごとに異方性導電膜を個別に貼りつける方法もある。つまり、まず一方の半導体装置を実装するための異方性導電膜を貼りつけた後、半導体装置を実装する。その後、他方の半導体装置を実装するための異方性導電膜を貼りつけ他方の半導体装置を実装する。この場合は、全く熱硬化の心配はないが、同一工程を繰り返すことになり、生産性が著しく損なわれることが容易に考えられる。
【0015】
つまり、異方性導電膜を一括して貼りつけ、しかも複数の半導体装置を短間隔で配置できる実装構造が求められている。
【0016】
【課題を解決するための手段】
以上のような問題を解決するために、本発明は、複数の半導体装置を一体の異方性導電膜を介在して基板に設けられた複数の部品実装面に実装する半導体装置の実装構造において、前記複数の部品実装面の内の隣り合う実装面の間の前記基板にはスリットが設けられていることを特徴とする。
また本発明は、複数の半導体装置を一体の異方性導電膜を介在して基板に設けられた複数の部品実装面に実装する半導体装置の実装構造において、前記複数の部品実装面の内の隣り合う実装面の間の前記基板には複数のスルーホールが設けられていることを特徴とする。
また本発明は、前記複数のスルーホールには前記基板よりも熱伝導率が低い物質が充填されていることを特徴とする。
また本発明は、前記物質は炭素であることを特徴とする。
更に本発明は、複数の半導体装置を一体の異方性導電膜を介在して基板に設けられた複数の部品実装面に実装する半導体装置の実装構造において、前記複数の部品実装面の内の隣り合う実装面の間に位置する前記異方性導電膜にはスリットが設けられていることを特徴とする。
【0017】
【発明の実施の形態】
(1)第一実施形態
以下図面により本発明の実施形態を詳述する。図1は本発明の複数の半導体装置を1枚の基板に高密度に実装する、マルチチップモジュールの図面を示す。
【0018】
図1(a)は、基板に異方性導電膜が仮圧着され、一方の半導体装置を実装する直前の状態を示す断面図である。
【0019】
図1(b)は、異方性胴電膜を除いた状態の、図1(a)の平面図である。
【0020】
図1(c)は、一方の半導体装置を実装した状態を示す断面図である。
【0021】
図1(d)は、他方の半導体装置も実装した状態を示す断面図である。
【0022】
図1(a)において、基板2の部品実装面3上に、異方性導電膜20が仮圧着され、保護用テープは既にはがされている状態を示す。25及び27は半導体装置を示す。ここで、図中のh1,h2は各々の半導体装置のパンプ高さを示している。異方性導電膜20の厚みは、ベアチップIC25の所定の面26と基板2の部品実装面3との間の充填性を考慮し、バンプ高さh1より10μm程度厚いものを用いる。29は、ベアチップIC25とベアチップIC27の間の設けられた、基板のスリット部を示す。
【0023】
まず、図1(a)において、ベアチップIC25を加熱・加圧して異方性導電膜を介し実装する。図1(b)はベアチップIC25が実装される直前の状態を示す平面図である。本図では、基板2に設けたスリット部29が分かり易いよう、異方性導電膜20を除いた状態の平面図である。図1(c)において、加熱・加圧ツール24がベアチップIC25を実装することにより実装時の熱が異方性導電膜20、配線パターン4、基板2を介し矢印a,矢印b方向に伝導する。しかし、もっとも熱容量が大きな基板2にスリット29が設けられているため、熱の大部分は矢印a方向に伝わり、ベアチップIC27が実装される部分の異方性導電膜に熱は伝導せず、熱硬化は進まない。
【0024】
つまり、ベアチップIC25とベアチップIC27の間の基板2にスリット29を設けることにより、ベアチップIC間隔を短くでき、より高密度な実装が可能な構造を実現できる。
【0025】
本実施形態では、一枚の基板に二個の半導体装置が実装される例を述べたが、更に多くの半導体装置が実装される場合では、より多くの効果が得られるのは言うまでもない。
【0026】
(2)第二実施形態
本実施形態は、第一実施形態の変形例である。本変形例は、複数の半導体装置の間の基板に設けるスリットを、基板表面と裏面に配置された配線パターンの電気的導通を確保する為のスルーホールで代用したことを特徴とする。
【0027】
図2は、基板2のベアチップIC25とベアチップIC27が実装される部分の間に、基板2の表面の配線パターンと裏面の配線パターンの電気的導通を行うための、スルーホール31がほぼ直線状に設けられている様子を示す平面図である。本実施形態は第一実施形態に比較するとベアチップIC25の実装時の熱は多く伝わるものの、前記スルーホール31の間に配線パターン4を配置でき、基板設計の自由度が大きくなる。
【0028】
(3)第三実施形態
本実施形態は、第二実施形態の変形例である。本実施形態では、基板2のベアチップIC25とベアチップIC27が実装される部分の間に、設けられたスルーホール31の内部を熱伝導の低い物質で充填させた例である。
【0029】
図3は、本実施形態を示す断面図である。
【0030】
前記スルーホール31内には、基板2の材質である例えばガラスエポキシの熱伝導率に対し熱伝導率が低い炭素32を充填している。このことにより、ベアチップIC25実装時の熱は、ベアチップIC27の実装する部分の異方性導電膜への熱伝導は大幅に削減され、安定した実装品質を得ることができる。
【0031】
(4)第四実施形態
本実施形態は、第一実施形態の変形例である。本実施形態では、基板2のベアチップIC25とベアチップIC27が実装される部分の間のスリットを基板に設けるのではなく、異方性導電膜20に設けたことを特徴としている。
【0032】
図面4(a)は、本実施形態の断面図を示し、図面4(b)は平面図を示す。
【0033】
図面4(b)において、30は異方性導電膜20に設けられたスリット部を示す。図面4(a)において、スリット部30の直下の基板2には、何もスリットや穴を設けていないため、配線パターン4を自由に配置でき、設計上の配線自由度を全く損なわずに、熱伝導を防止することができる。
【0034】
【発明の効果】
請求項1記載の発明によれば、複数のベアチップICを一枚の基板に実装するいわゆるマルチチップモジュールの場合、一方のベアチップICを実装する際の熱が基板を伝わり、他方のベアチップICを実装する為にあらかじめ貼られている異方性導電膜に伝わり、熱硬化を進めてしまい、安定した実装品質を得られなくなってしまうという問題を防ぐことができる。
【0035】
一方のベアチップICと他方のベアチップICの間の基板の部分にスリットを設けることにより、熱硬化を防ぎ複数のベアチップICを近接して配置することが可能となり、小型でコンパクトな実装構造を得ることができる。
【0036】
請求項2記載の発明によれば、一方のベアチップICと他方のベアチップICの間の基板の部分にスルーホールを配置することにより、一方のベアチップICを実装する際の熱が基板を伝わり、他方のベアチップICを実装する為にあらかじめ貼られている異方性導電膜に伝わり、熱硬化を進めるという問題を防ぐと同時に、各スルーホール間に配線パターンを配置でき、より配線設計の自由度をも向上させた実装構造が実現できる。
【0037】
請求項3記載の発明によれば、熱伝導を防ぐ為に配置されたスルーホールの内部に熱伝導の低い物質を充填させることにより、さらに熱伝導を下げることが可能となり、より複数のベアチップICを近接して配置が可能となる。
【0038】
請求項4記載の発明によれば、一括して貼りつけられた異方性導電膜の、複数のベアチップICを実装する間の部分の前記異方性導電膜にスリットを設けることにより、熱硬化を防ぎ、基板には何もスリットやスルーホールを配置しないため、配線自由度が最も高くすることが可能となる。
【図面の簡単な説明】
【図1】本発明の第一実施形態を示す実装構造の断面図を示す。
【図2】本発明の第二実施形態を示す実装構造の平面図を示す。
【図3】本発明の第三実施形態を示す実装構造の断面図を示す。
【図4】本発明の第四実施形態を示す実装構造の図面を示す。
【図5】本発明の従来例を示す実装構造を示す。
【符号の説明】
1、25,27…ベアチップIC
2…基板
3…部品実装面
4…配線パターン
5…電極
6…ソルダーレジスト
7、26、28…所定の面
8…バンプ
20…異方性導電膜
21…絶縁性樹脂
22…導電粒子
23…保護用テープ
24…加熱、加圧ツール
29…基板のスリット部
30…異方性導電膜のスリット部
31…スルーホール
32…炭素
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device mounting structure in which a semiconductor device is mounted on a substrate using an anisotropic conductive film.
[0002]
[Prior art]
As a conventionally known technique, an anisotropic conductive film is used as a structure for electrically and mechanically connecting a bump which is a protruding electrode provided on an electrode of a semiconductor device and a pattern arranged on a substrate. The structures used are known. The prior art of this mounting structure will be described in the order of mounting steps with reference to FIG.
[0003]
FIG. 5 is a cross-sectional view showing a conventional technique. In FIG. 5A, a plurality of wiring patterns 4 are formed of a conductive material on a component mounting surface 3 of a substrate 2 on which a bare chip IC 1, which is a semiconductor device, is mounted. Is provided with a gold-plated electrode 5. Each wiring pattern 4 is covered with a solder resist 6 except for the electrode 5.
[0004]
The bare chip IC1 has a plurality of electrodes formed of a conductive material such as aluminum on a predetermined surface 7 corresponding to the electrodes of the substrate, and bumps 8 are formed on the surface of each electrode. The bump 8 is formed of a metal material such as Au or Sn-Pb alloy.
[0005]
FIG. 5B is a cross-sectional view of a step of temporarily pressing the anisotropic conductive film. The anisotropic conductive film 20 used for mounting the bare chip IC 1 is formed by dispersing conductive particles 22 in an insulating resin 21. The anisotropic conductive film 20 is formed in a tape shape having a width larger than the width of the predetermined surface 7 of the bare chip IC1, and is wound around a reel while being covered with a protective tape.
[0006]
When mounting the bare chip IC 1, first, the anisotropic conductive film 20 wound on a reel is cut into a required length together with the protective tape 23, and mounted on the component mounting surface 3 of the substrate 2. Next, the anisotropic conductive film 20 is heated from the side of the protective tape 23 and heated (80 ° C. for about 2 seconds) and pressed by the pressing tool 24 to temporarily press the anisotropic conductive film 20. In this case, the anisotropic conductive film 20 is bonded to the mounting position of the bare chip IC 1 so as to cover the wiring pattern 4 and the electrode 5 of the substrate 2. Preferably, the area of the anisotropic conductive film 20 is larger than the area of the predetermined surface 7 of the bare chip IC1. The thickness of the anisotropic conductive film 20 is preferably about 10 μm thicker than the height of the bump 8.
[0007]
Next, FIG. 5C shows a cross-sectional view in which the semiconductor device is mounted. The protective tape 23 of the anisotropic conductive film 20 adhered to the substrate 2 is peeled off, and a predetermined surface 7 of the bare chip IC 1 is set so as to face the anisotropic conductive film 20, and the bare chip IC 1 is placed on the anisotropic conductive film 20. The IC chip 1 is mounted, and the anisotropic conductive film 20 is pressed (at 180 ° C. for about 20 seconds) and heated via the bare chip IC 1 to mount the bare chip IC 1. By heating, the insulating resin 21 of the anisotropic conductive film 20 is softened and expanded by applying pressure, so that the space between the predetermined surface 7 of the bare chip IC 1 and the component mounting surface 3 of the substrate 2 is filled. The surplus insulating resin 21 is pushed out in the direction of arrow a to fill and protect the side surface of the bare chip IC1. This state is shown in FIG.
[0008]
Thus, the component mounting surface 3 of the substrate 2 and the predetermined surface 7 of the bare chip IC 1 are joined via the insulating resin 21 of the anisotropic conductive film 20. In addition, since the conductive particles 22 mixed in the anisotropic conductive film 20 are pressed by the bumps 8 against the electrodes 5 of the substrate 2, the substrate 2 and the bare chip IC 1 are also electrically connected.
[0009]
[Problems to be solved by the invention]
Along with the multi-functionality of electronic devices, multi-chip modules for mounting a plurality of semiconductor devices on a single substrate at high density have been widely used, but have the following disadvantages.
[0010]
In the case where a plurality of semiconductor devices are mounted on one substrate, anisotropic conductive films must be adhered to the portions where the respective semiconductor devices are mounted, as many as the number of the semiconductor devices, which significantly reduces productivity. Was. In addition, the production equipment required complicated and large-scale equipment.
[0011]
On the other hand, for the sake of simplicity, there is also a structure in which an anisotropic conductive film is collectively attached to a mounting portion of each semiconductor device, instead of being attached to each mounting portion of each semiconductor device. In this case, there is no problem if a plurality of semiconductor devices are sufficiently separated from each other, but when compactness and high density are required, the semiconductor devices have to be arranged adjacent to each other.
[0012]
In this case, first, one semiconductor device is mounted by heating and pressing. At this time, heat at the time of mounting conducts through the board and the wiring pattern arranged on the surface of the board, and heat of the insulating resin constituting the anisotropic conductive film which has been temporarily crimped to the portion where the other semiconductor device is to be mounted. The curing progresses, and when mounting the other semiconductor device, the insulating resin does not sufficiently soften even when heated and pressed, and the holding of the substrate and the semiconductor device becomes insufficient. There is a problem in that electrical conduction cannot be ensured, which is a fatal defect for electronic equipment.
[0013]
Therefore, each semiconductor device must be separated by a distance that does not allow thermal curing of the insulating resin to proceed by heating and pressing when mounting one of the semiconductor devices, which has been a great hindrance to high-density mounting. .
[0014]
Of course, there is also a method of individually attaching an anisotropic conductive film to each of a plurality of semiconductor devices. That is, an anisotropic conductive film for mounting one semiconductor device is first attached, and then the semiconductor device is mounted. After that, an anisotropic conductive film for mounting the other semiconductor device is attached and the other semiconductor device is mounted. In this case, there is no concern about heat curing, but the same process is repeated, and it is easily considered that productivity is significantly impaired.
[0015]
In other words, there is a demand for a mounting structure in which anisotropic conductive films can be attached together and a plurality of semiconductor devices can be arranged at short intervals.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the present invention relates to a semiconductor device mounting structure in which a plurality of semiconductor devices are mounted on a plurality of component mounting surfaces provided on a substrate with an integrated anisotropic conductive film interposed therebetween. A slit is provided on the substrate between adjacent mounting surfaces of the plurality of component mounting surfaces.
The present invention also provides a semiconductor device mounting structure in which a plurality of semiconductor devices are mounted on a plurality of component mounting surfaces provided on a substrate with an integrated anisotropic conductive film interposed therebetween, wherein A plurality of through holes are provided in the substrate between adjacent mounting surfaces.
Further, according to the present invention, the plurality of through holes are filled with a substance having a lower thermal conductivity than the substrate.
Further, the present invention is characterized in that the substance is carbon.
Further, the present invention provides a semiconductor device mounting structure in which a plurality of semiconductor devices are mounted on a plurality of component mounting surfaces provided on a substrate with an integrated anisotropic conductive film interposed therebetween, wherein: A slit is provided in the anisotropic conductive film located between adjacent mounting surfaces.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
(1) First Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a drawing of a multichip module in which a plurality of semiconductor devices of the present invention are mounted on a single substrate at a high density.
[0018]
FIG. 1A is a cross-sectional view showing a state in which an anisotropic conductive film is temporarily pressed on a substrate and immediately before one semiconductor device is mounted.
[0019]
1 (b) is a state except for the anisotropic cylinder conductive film is a plan view of FIG. 1 (a).
[0020]
FIG. 1C is a cross-sectional view showing a state where one semiconductor device is mounted.
[0021]
FIG. 1D is a cross-sectional view showing a state where the other semiconductor device is also mounted.
[0022]
FIG. 1A shows a state in which an anisotropic conductive film 20 is temporarily pressure-bonded on a component mounting surface 3 of a substrate 2 and a protective tape has already been removed. Reference numerals 25 and 27 indicate semiconductor devices. Here, h1 and h2 in the figure indicate the pump height of each semiconductor device. The thickness of the anisotropic conductive film 20 is about 10 μm thicker than the bump height h1 in consideration of the filling property between the predetermined surface 26 of the bare chip IC 25 and the component mounting surface 3 of the substrate 2. Reference numeral 29 denotes a slit portion of the substrate provided between the bare chip IC 25 and the bare chip IC 27.
[0023]
First, in FIG. 1A, the bare chip IC 25 is heated and pressurized and mounted via an anisotropic conductive film. FIG. 1B is a plan view showing a state immediately before the bare chip IC 25 is mounted. FIG. 3 is a plan view showing a state where the anisotropic conductive film 20 is removed so that the slit portion 29 provided on the substrate 2 can be easily understood. In FIG. 1C, the heating / pressing tool 24 mounts the bare chip IC 25, and the heat at the time of mounting is conducted in the directions of arrows a and b through the anisotropic conductive film 20, the wiring pattern 4, and the substrate 2. . However, since the slit 29 is provided on the substrate 2 having the largest heat capacity, most of the heat is transmitted in the direction of arrow a, and the heat is not conducted to the anisotropic conductive film where the bare chip IC 27 is mounted. Curing does not proceed.
[0024]
That is, by providing the slit 29 in the substrate 2 between the bare chip IC 25 and the bare chip IC 27, the interval between the bare chip ICs can be shortened, and a structure capable of higher-density mounting can be realized.
[0025]
In the present embodiment, an example in which two semiconductor devices are mounted on one substrate has been described, but it goes without saying that more effects can be obtained when more semiconductor devices are mounted.
[0026]
(2) Second Embodiment This embodiment is a modification of the first embodiment. The present modification is characterized in that a slit provided in a substrate between a plurality of semiconductor devices is replaced with a through hole for ensuring electrical continuity between wiring patterns arranged on the front and back surfaces of the substrate.
[0027]
FIG. 2 shows that a through hole 31 is formed in a substantially straight line between the portion of the substrate 2 where the bare chip IC 25 and the bare chip IC 27 are mounted, for electrically connecting the wiring pattern on the front surface and the wiring pattern on the back surface of the substrate 2. It is a top view showing a mode provided. In this embodiment, compared to the first embodiment, although the heat at the time of mounting the bare chip IC 25 is transmitted more, the wiring pattern 4 can be arranged between the through holes 31 and the degree of freedom in designing the board is increased.
[0028]
(3) Third Embodiment This embodiment is a modification of the second embodiment. The present embodiment is an example in which the inside of the through hole 31 provided between the portion where the bare chip IC 25 and the bare chip IC 27 of the substrate 2 are mounted is filled with a substance having low thermal conductivity.
[0029]
FIG. 3 is a sectional view showing the present embodiment.
[0030]
The inside of the through hole 31 is filled with carbon 32 whose thermal conductivity is lower than that of the material of the substrate 2 such as glass epoxy. As a result, as for the heat at the time of mounting the bare chip IC 25, the heat conduction to the anisotropic conductive film in the portion where the bare chip IC 27 is mounted is greatly reduced, and stable mounting quality can be obtained.
[0031]
(4) Fourth Embodiment This embodiment is a modification of the first embodiment. The present embodiment is characterized in that a slit between a portion where the bare chip IC 25 and the bare chip IC 27 of the substrate 2 are mounted is not provided on the substrate but is provided on the anisotropic conductive film 20.
[0032]
Drawing 4 (a) shows a sectional view of this embodiment, and drawing 4 (b) shows a top view.
[0033]
In FIG. 4B, reference numeral 30 denotes a slit provided in the anisotropic conductive film 20. In FIG. 4 (a), since no slits or holes are provided in the substrate 2 immediately below the slit portion 30, the wiring pattern 4 can be arranged freely, without impairing the degree of freedom of wiring in design at all. Heat conduction can be prevented.
[0034]
【The invention's effect】
According to the first aspect of the present invention, in the case of a so-called multi-chip module in which a plurality of bare chip ICs are mounted on one substrate, heat when mounting one bare chip IC is transmitted to the substrate and the other bare chip IC is mounted. Therefore, it is possible to prevent the problem that the heat is transmitted to the anisotropic conductive film that has been pasted in advance and heat curing is advanced, so that stable mounting quality cannot be obtained.
[0035]
By providing a slit in a portion of the substrate between one bare chip IC and the other bare chip IC, it is possible to prevent thermal curing and to arrange a plurality of bare chip ICs in close proximity to obtain a small and compact mounting structure. Can be.
[0036]
According to the second aspect of the present invention, by arranging a through hole in a portion of the substrate between one bare chip IC and the other bare chip IC, heat at the time of mounting one bare chip IC is transmitted to the substrate, and To the anisotropic conductive film that has been applied in advance to mount the bare chip IC, and prevent the problem of advancing the thermosetting, and at the same time, it is possible to arrange the wiring pattern between each through-hole, thus increasing the freedom of wiring design. Thus, a mounting structure that is improved can be realized.
[0037]
According to the third aspect of the present invention, it is possible to further reduce the heat conduction by filling the inside of the through hole arranged to prevent the heat conduction with a substance having a low heat conduction, thereby further reducing a plurality of bare chip ICs. Can be arranged close to each other.
[0038]
According to the fourth aspect of the present invention, the anisotropic conductive film bonded together is provided with a slit in the portion of the anisotropic conductive film between the mounting of a plurality of bare chip ICs, thereby providing thermosetting. Since no slits or through holes are arranged on the substrate, the degree of freedom in wiring can be maximized.
[Brief description of the drawings]
FIG. 1 is a sectional view of a mounting structure showing a first embodiment of the present invention.
FIG. 2 is a plan view of a mounting structure according to a second embodiment of the present invention.
FIG. 3 is a sectional view of a mounting structure showing a third embodiment of the present invention.
FIG. 4 is a drawing of a mounting structure showing a fourth embodiment of the present invention.
FIG. 5 shows a mounting structure showing a conventional example of the present invention.
[Explanation of symbols]
1, 25, 27 ... bare chip IC
2 ... board 3 ... component mounting surface 4 ... wiring pattern 5 ... electrode 6 ... solder resist 7, 26, 28 ... predetermined surface 8 ... bump 20 ... anisotropic conductive film 21 ... insulating resin 22 ... conductive particles 23 ... protection Tape 24: Heating and pressing tool 29: Slit portion 30 of substrate: Slit portion 31 of anisotropic conductive film: Through hole 32: Carbon

Claims (5)

複数の半導体装置を一体の異方性導電膜を介在して基板に設けられた複数の部品実装面に実装する半導体装置の実装構造において、
前記複数の部品実装面の内の隣り合う実装面の間の前記基板にはスリットが設けられていることを特徴とする半導体装置の実装構造。
In a semiconductor device mounting structure in which a plurality of semiconductor devices are mounted on a plurality of component mounting surfaces provided on a substrate with an integrated anisotropic conductive film interposed therebetween,
A mounting structure for a semiconductor device, wherein a slit is provided in the substrate between adjacent mounting surfaces among the plurality of component mounting surfaces.
複数の半導体装置を一体の異方性導電膜を介在して基板に設けられた複数の部品実装面に実装する半導体装置の実装構造において、
前記複数の部品実装面の内の隣り合う実装面の間の前記基板には複数のスルーホールが設けられていることを特徴とする半導体装置の実装構造。
In a semiconductor device mounting structure in which a plurality of semiconductor devices are mounted on a plurality of component mounting surfaces provided on a substrate with an integrated anisotropic conductive film interposed therebetween,
A mounting structure for a semiconductor device, wherein a plurality of through holes are provided in the substrate between adjacent mounting surfaces of the plurality of component mounting surfaces.
請求項2において、
前記複数のスルーホールには前記基板よりも熱伝導率が低い物質が充填されていることを特徴とする半導体装置の実装構造。
In claim 2,
The semiconductor device mounting structure, wherein the plurality of through holes are filled with a substance having a lower thermal conductivity than the substrate.
請求項3において、
前記物質は炭素であることを特徴とする半導体装置の実装構造。
In claim 3,
The mounting structure of a semiconductor device, wherein the substance is carbon.
複数の半導体装置を一体の異方性導電膜を介在して基板に設けられた複数の部品実装面に実装する半導体装置の実装構造において、
前記複数の部品実装面の内の隣り合う実装面の間に位置する前記異方性導電膜にはスリットが設けられていることを特徴とする半導体装置の実装構造。
In a semiconductor device mounting structure in which a plurality of semiconductor devices are mounted on a plurality of component mounting surfaces provided on a substrate with an integrated anisotropic conductive film interposed therebetween,
A mounting structure for a semiconductor device, wherein a slit is provided in the anisotropic conductive film located between adjacent mounting surfaces of the plurality of component mounting surfaces.
JP27487299A 1999-09-28 1999-09-28 Semiconductor device mounting structure Expired - Fee Related JP3578011B2 (en)

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