JP3576978B2 - Memory port, storage device, information processing system - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to failure detection of a storage device, and more particularly, to collecting information for RAM (Ramdom Access Memory) failure analysis on hardware and generating a pseudo request based on the information, thereby detecting a RAM failure in the storage device. The present invention relates to a storage device capable of specifying a transmission range.
[0002]
[Prior art]
2. Description of the Related Art In recent years, large-capacity storage devices using a RAM (Random Access Memory) or the like have been required to have large capacity and high speed, and at the same time, high reliability has been required. For this reason, the storage device is provided with an ECC circuit for performing data correction and uncorrectable error detection, thereby preventing data corruption and sending expected read data to a higher-level device to improve reliability. However, due to the large capacity, high speed, and complicated control of the RAM, the tendency of the RAM failure to depend on the access pattern is increasing. Therefore, it takes time to analyze an access pattern at the time of occurrence of a failure and to reflect it in creating a test program.
[0003]
Japanese Patent Application Laid-Open No. Hei 4-297933 discloses a "failure analysis support apparatus" in which, when a program interrupt occurs, hardware control information for temporarily suspending the update of the stage tracer is set, a test program is started, and an instruction to be tested is executed. A failure analysis support apparatus is disclosed in which, when a program interrupt occurs during execution of a column, a validity test of various data and registers is performed by the program interrupt, and when it is determined to be defective, trace information is logged and the test is continued. .
[0004]
[Problems to be solved by the invention]
In the past, RAM failures could be detected to some extent by a RAM unit test. However, recent large capacity, high speed, and complicated control have made it difficult to detect RAM failures, depending on the unit test test pattern. However, it is not easy to make a test pattern that covers everything. Therefore, if the test pattern does not cover everything, the unit test passes.However, in the case of operating as a system after manufacturing, if an access pattern that was missing in the test pattern occurs, an uncorrectable error is detected and the system goes down in few cases. Absent. It is necessary to analyze the cause of the uncorrectable error quickly and efficiently.
[0005]
Japanese Unexamined Patent Application Publication No. 4-297933 "failure analysis support apparatus" cannot generate and trace a pseudo request.
[0006]
An object of the present invention is to solve such a conventional problem. Before and after the moment when an uncorrectable error occurs, a plurality of stages are collected by a stage tracer, and the collected trace information is generated as a request by the storage device itself, and a failure is generated. An object of the present invention is to provide a storage device capable of specifying a RAM failure spread range by performing a RAM access to a port other than a port.
[0007]
[Means for Solving the Problems]
The present invention first storage device is a storage device having a plurality of memory ports and pseudo request generating unit and the fault port selecting unit, said memory port, a request from the request and the pseudo request generating unit from the host apparatus And a request selecting unit for selecting a write operation condition, a read operation condition, or a refresh operation condition and an address to the storage control unit according to an operation instruction command, and a write data control in the case of the write operation condition. A request receiving unit that outputs write data to a unit, a storage control unit that outputs a control signal to a storage unit according to the operation condition, a check bit generated from the write data, and the write data and the check bit are stored in the storage unit. A write data control unit for outputting, and read data from the storage unit A read data control unit for detecting an error of the serial read data, and the tracer unit for rewriting by storing requests the contents of the trace register to the memory port, the rewriting of the trace register when certain conditions occur A trigger condition section for stopping , wherein when the error is detected in the memory port, the pseudo request generation section reads out the operation condition in the tracer section to generate a pseudo request, and the failure port selecting section outputs the pseudo request. A request is issued to the predetermined memory port.
[0008]
The present invention second storage device is a storage device having a plurality of memory ports and pseudo request generating unit and the fault port selecting unit, said memory port, a request from the request and the pseudo request generating unit from the host apparatus And a request selecting unit for selecting a write operation condition, a read operation condition, or a refresh operation condition and an address to the storage control unit according to an operation instruction command, and a write data control in the case of the write operation condition. A request receiving unit that outputs write data to a unit, a storage control unit that outputs a control signal to a storage unit according to the operation condition, a check bit generated from the write data, and the write data and the check bit are stored in the storage unit. A write data control unit for outputting, and read data from the storage unit A read data control unit for detecting an error of the serial read data, and the tracer unit for rewriting by storing requests the contents of the trace register to the memory port, the rewriting of the trace register when certain conditions occur A trigger condition unit for stopping , wherein the storage device is connected to a diagnostic device, and in accordance with an instruction from the diagnostic device, the pseudo request generation unit performs the operation in the tracer unit when an error is detected in the memory port The condition is read, a pseudo request is generated, and the fault port selecting unit issues the pseudo request to the predetermined memory port in accordance with an instruction from the diagnostic device.
[0009]
The present invention third storage device, the tracer portion comprising a first storage device the present invention, the said address before and after the said error is detected write operating conditions, the read operation conditions or the refresh operation, A condition is traced to the tracer unit by a trigger signal from the trigger condition unit.
[0010]
The fourth storage device of the present invention is the first or second storage device of the present invention , wherein the trigger condition section generates a logical sum of an uncorrectable error signal, a correctable error signal, and an error signal in the storage device as a trigger signal. I do.
[0012]
In the information processing system of the present invention, an arithmetic processing unit, an input / output processing unit, and the first, second, third or fourth storage device of the present invention are connected by a network.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a storage device according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a storage device according to the present invention. In the storage device 1 according to the embodiment of the present invention, the request input terminal 101, the request receiving unit 114, the storage control unit 116, the write data control unit 117, the storage unit 118, the read data control unit 119, the reply In the storage device 1 having the data output terminal 102, a pseudo request generation unit 12, a failure port selection unit 10 common to all the memory ports 11, and a request selection unit 112, a trigger condition unit 113, and a tracer unit 115 for each memory port 11 are provided. .
[0014]
That is, the storage device 1 basically includes the request input terminal 101, the request receiving unit 114, the storage control unit 116, the write data control unit 117, the storage unit 118, the read data control unit 119, and the reply data output terminal 102 in each memory port 11. A pseudo request generation unit 12 common to all memory ports 11 for generating and testing a request pattern based on trace information in the tracer unit 115 of each memory port 11 in which an uncorrectable error has occurred, and a failure port selection unit 10 The feature is that a request selecting unit 112, a trigger condition unit 113, and a tracer unit 115 are provided for each memory port 11.
[0015]
Next, the position in the system of the storage device according to the embodiment of the present invention in the above configuration will be described. FIG. 2 is a block diagram illustrating a configuration of an information processing system including the storage device 1 according to the embodiment of the present invention. The storage device 1 is connected to the diagnostic device 2 and is disconnected from the system when a failure occurs or when a diagnosis is made, and receives an instruction and generates a pseudo failure request. In addition, the storage device 1 is connected to the arithmetic processing device 3 and the input / output device 5 via the network 4 during normal operation, exchanges commands and data, and executes information processing.
[0016]
The diagnostic device 2 generates a request pattern based on the trace information in the tracer unit 115 and performs a pseudo request generation unit 12 common to all the memory ports 11, a failure port selection unit 10, and a request selection for each memory port 11. The control unit 112 controls the trigger condition unit 113 and the tracer unit 115.
[0017]
Next, the operation of the storage device 1 according to the embodiment of the present invention in the above configuration will be described. The request selection unit 112 of each memory port 11 receives a request corresponding to each memory port 11 via the network 4 from the arithmetic processing device 3 or the input / output device 5 which is an upper device in system operation. Requests such as these operation instruction commands, addresses, and write data are input to the request receiving unit 114 from the request input terminal 101 side.
[0018]
The request receiving unit 114 outputs a write operation condition, a read operation condition, or a refresh operation condition and an address necessary for each operation to the storage control unit 116 in accordance with the operation instruction command, and in the case of the write operation condition, the write data control unit 117. Output the write data. The operation condition indicates an operation of the storage device 1 such as a block read and a partial write. The storage control unit 116 outputs a control signal to the storage unit 118 in accordance with the received operating conditions, and the write data control unit 117 generates a check bit from the received write data in accordance with the ECC code. Output data and check bits. In the case of a read operation, read data is output from the storage unit 118, and after input to the read data control unit 119, if expected data is not read due to a RAM failure or the like, the read data control unit 119 The data is corrected or an uncorrectable error is detected by the ECC circuit, and the reply data is output from the reply data output terminal 102. During system operation, the above operations are mainly performed.
[0019]
Next, request tracing will be described. During operation of the information processing system, for example, when an uncorrectable error is detected by the ECC circuit in the read data control unit 119 when the read data control unit 119 of the memory port 013 receives read data, an uncorrectable error signal is output. The trigger condition unit 113 of the memory port 013 outputs the trigger signal 1153 to the tracer unit 115 of the memory port 013.
[0020]
FIG. 3 is a block diagram illustrating a stage configuration of the selector 1152 and the tracer unit 115 connected to the upper part of each register 1151 of the tracer unit 115 in the storage device according to the embodiment of the present invention. In the tracer unit 115, various operation conditions (address, write condition, read condition, refresh condition, etc.) received from the request receiving unit 114 are received by the register 1151 of the stage 0, and the stage 1 → the stage is synchronized with the clock cycle in the storage device 1. 2 and the contents of the register 1151 move, and the register 1151 of the stage n is overwritten by the following various operation condition signals. In the storage device 1, the tracer 115 section shows that the stage 0 has the latest various operation conditions. In stage n, various operating conditions before the latest various operating condition signals by n stages are always stored.
[0021]
The selector 1152 connected to the upper part of each register 1151 normally selects the register 1151 of the previous stage. Only when the trigger condition is satisfied, various operation conditions (address, write condition, read condition, refresh condition, etc.) before and after the occurrence of an error are held by selecting its own register 1151 by the trigger signal 1153.
[0022]
When the trigger signal 1153 is received by the tracer unit 115, the selector 1152 connected to the upper part of each register 1151 selects its own register 1151 by the trigger signal 1153, and holds various operating conditions before and after the occurrence of the uncorrectable error in the register 1151. Various operation conditions in the register 1151 of each stage are connected to the pseudo request generation unit 12.
[0023]
The above operations are performed only on the memory port 013 where the failure has occurred, and the operations of the trigger condition unit 113 and the tracer unit 115 of the other memory ports 11 are not performed. The system goes down due to the detection of an uncorrectable error. The diagnostic device 2 recognizes from the diagnostic device input / output terminal 109 in which memory port 11 an error has occurred, reads out various operating conditions that are trace information of each stage, and performs feedback to a test pattern.
[0024]
Next, generation of a pseudo request will be described. After the system goes down, the diagnostic device 2 disconnects the storage device 1 from the system, issues a signal for selecting the memory port 013 from the outside to the failure port selection unit 10, and outputs the signal to the tracer unit 115 in the memory port 013. Each stage information is input to the pseudo request generation unit 12. After that, the diagnostic device 2 instructs the pseudo request generation unit 12 to issue a pseudo request issuing instruction, and from the nth stage various operating conditions of the tracer unit 115, every clock cycle, from the (n-1) th stage to the (n-2) th stage,. In accordance with the oldest request history received in the storage device 1, a pseudo request converted into the same format as the request input into the storage device 1 during system operation is issued to the storage device 1.
[0025]
At this time, the pseudo request issuance command inputs the pseudo request to the request receiving unit 114 of each memory port 11 in order to simultaneously select the request selecting unit 112 on the pseudo request generating unit 12 side. Is masked by a signal for selecting the memory port 013 from the outside to the fault port selecting unit 10, and the request selecting unit 112 in the memory port 013 keeps selecting the same request input terminal 101 as in the system operation, and the memory port 013 has No pseudo request is input. A pseudo request is accepted by each of the memory ports 11 other than the memory port 013, and a test is performed to determine whether an uncorrectable error occurs. Here, the memory port 013 has been described as an example, but the same operation is performed even when an uncorrectable error is detected in the other memory ports 11.
[0026]
The case where the uncorrectable error is used as the trigger signal 1153 has been described above. However, as another function, the trigger condition unit 113 uses the OR of the uncorrectable error signal, the correctable error signal, and the error signal in the storage device 1 as the trigger signal 1153. Therefore, the access range in which a correctable error has occurred, the data collection of an access pattern in the case where an error has occurred in the storage device 1 due to a logical error, or the issue of a pseudo request according to the access pattern specifies the range of the failure propagation. Becomes possible.
[0027]
【The invention's effect】
As described above, since the access pattern when an uncorrectable error occurs can be used as a test pattern as it is, the range of the defective RAM can be efficiently specified, and the efficiency of the failure analysis can be realized from the access pattern. . In a storage device with multiple ports, the access pattern when an uncorrectable error occurs can be used as a test pattern as it is, so it is possible to efficiently specify the range of the defective RAM and to improve the efficiency of failure analysis from the access pattern. Can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a storage device according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of an information processing system having a storage device according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a selector 1152 connected to an upper portion of each register 1151 of the tracer unit 115 and a stage configuration of the tracer unit 115 in the storage device according to the embodiment of the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 storage device 2 diagnostic device 3 arithmetic processing device 4 network 5 input / output device 10 fault port selector 11 memory port 12 pseudo request generator 13 memory port 0
101 Request input terminal 102 Reply data output terminal 109 Diagnostic device input / output terminal 112 Request selection unit 113 Trigger condition unit 114 Request reception unit 115 Tracer unit 116 Storage control unit 117 Write data control unit 118 Storage unit 119 Read data control unit 1152 Selector 1151 Register 1153 Trigger signal

Claims (5)

A storage device having a plurality of memory ports, a pseudo request generation unit, and a failure port selection unit,
The memory port, a request selecting unit that selects a request from the request and the pseudo request generating unit from the host device receives the request, the operation instruction command in accordance with a write operating conditions in the storage control unit, the read operating conditions, or A request receiving unit that outputs a refresh operation condition and an address and outputs write data to a write data control unit in the case of the write operation condition; a storage control unit that outputs a control signal to a storage unit according to the operation condition; A write data control unit that generates a check bit from the storage unit and outputs the write data and the check bit to the storage unit, a read data control unit that reads read data from the storage unit and detects an error in the read data, Requests the contents of the trace register to the memory port Has a tracer unit for rewriting by storing the door, the trigger condition section for stopping the rewrite of the trace register when certain conditions occur,
When an error is detected in the memory port, the pseudo request generation unit reads the operating condition in the tracer unit to generate a pseudo request, and the failure port selection unit sends the pseudo request to a predetermined memory port. A storage device to be issued. A storage device having a plurality of memory ports, a pseudo request generation unit, and a failure port selection unit,
The memory port, a request selecting unit that selects a request from the request and the pseudo request generating unit from the host device receives the request, the operation instruction command in accordance with a write operating conditions in the storage control unit, the read operating conditions, or A request receiving unit that outputs a refresh operation condition and an address and outputs write data to a write data control unit in the case of the write operation condition; a storage control unit that outputs a control signal to a storage unit according to the operation condition; A write data control unit that generates a check bit from the storage unit and outputs the write data and the check bit to the storage unit, a read data control unit that reads read data from the storage unit and detects an error in the read data, Requests the contents of the trace register to the memory port Has a tracer unit for rewriting by storing the door, the trigger condition section for stopping the rewrite of the trace register when certain conditions occur,
The storage device is connected to a diagnostic device, and according to an instruction of the diagnostic device, the pseudo request generation unit reads the operating conditions in the tracer unit when an error is detected in the memory port, and generates a pseudo request. The storage device according to claim 1, wherein the failure port selector issues the pseudo request to a predetermined memory port in response to an instruction from the diagnostic device. The tracer unit, the write operation condition and the address of before and after the error is detected, the read operation condition or to trace to the tracer unit by a trigger signal of the refresh operation condition from the trigger condition section, The storage device according to claim 1, wherein: 3. The storage device according to claim 1, wherein the trigger condition unit generates a logical sum of an uncorrectable error signal, a correctable error signal, and an error signal in the storage device as a trigger signal. 5. An information processing system, wherein an arithmetic processing unit, an input / output processing unit, and the storage device according to claim 1, 2, 3, or 4 are connected by a network.

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