JP3569338B2 - Parallel processor - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a parallel processor that processes a plurality of basic instructions in parallel as one instruction.
[0002]
In computer systems, multiple instructions are processed in parallel by pipeline processing or the like to achieve higher speed.
Conventionally, long instructions have been used to combine multiple instructions into one fixed-length instruction and process the instructions in parallel. However, since the instructions are not variable in length, they are stored in cache memory when the number of basic instructions is small. This caused the hit rate to drop. Although parallel processing is also performed according to the degree of instruction parallelism using a superscalar method or the like, the number of registers needs to be increased as the degree of parallelism increases.
[0003]
The present invention provides a parallel processor capable of recognizing a series of basic instructions capable of parallel processing and treating them as one variable-length instruction so that the instructions can be efficiently processed in parallel.
[0004]
[Prior art]
FIG. 7 shows a conventional long-form instruction word execution method.
In FIG.
An instruction word 200 is a fixed-length, long-form instruction word having M N-bit basic instructions, and shows a case where M = 6. FIG. 7 includes basic instructions 1, 2, and 3 that are processed in parallel at one timing, and has NOP1, NOP2, and NOP3 (NOP is a no-operation instruction indicating that no processing is performed) and is fixed. It is a long long instruction word.
[0005]
A decoder 201 has a decoder 1, a decoder 2, a decoder 3, a decoder 4, a decoder 5, and a decoder 6. It is provided corresponding to each basic instruction word of the instruction word 200, and decodes each basic instruction word.
[0006]
An arithmetic unit 202 has arithmetic units 1, arithmetic units 2, arithmetic units 3, arithmetic units 4, arithmetic units 5, arithmetic units 5, and arithmetic units 6, and has a decoder 1, a decoder 2, a decoder 3, a decoder 4, a decoder 4, and a decoder 5, respectively. This is for processing the instruction decoded by the decoder 6.
[0007]
Reference numeral 203 denotes a register, which has a register 1, a register 2, a register 3, a register 4, a register 5, and a register 6, and has a computing unit 1, a computing unit 2, a computing unit 3, a computing unit 4, a computing unit 5, and a computing unit, respectively. 6 is held. Each register includes a plurality of individual registers and forms a register space. For example, one register space is constituted by the register 1 and 64 individual registers of 128 bits are provided.
[0008]
The operation of the configuration of FIG. 7 will be described.
The N-bit basic instruction 1, basic instruction 2, basic instruction 3, NOP1, NOP2, and NOP3 of the instruction word 200 are input to the decoder 1, decoder 2, decoder 3, decoder 4, decoder 5, decoder 5, and decoder 6 in parallel at the same timing. Then, they are input to the arithmetic unit 1, the arithmetic unit 2, the arithmetic unit 3, the arithmetic unit 4, the arithmetic unit 5, and the arithmetic unit 6, respectively.
[0009]
The basic instruction 1, the basic instruction 2, and the basic instruction 3 are processed by the respective arithmetic units, and the calculation results are held in the registers 1, 2, and 3, respectively. NOP1, NOP2, and NOP3 are instructions that do not perform processing, and are not calculated.
[0010]
FIG. 8 is an explanatory diagram of a conventional long-form instruction word generation method.
In FIG.
An instruction word generation program 210 is a program that generates a fixed-length long-length instruction word of eight basic instruction words.
[0011]
Reference numeral 221 denotes a command generated by the description on the first line of the command generation program 210.
Reference numeral 222 denotes a command generated by the description on the second line of the command generation program 210.
[0012]
Reference numeral 223 denotes a command generated by the description on the third line of the command generation program 210.
Reference numeral 224 denotes a command generated by the description on the fourth line of the command generation program 210.
[0013]
Reference numeral 225 denotes a command generated by the description on the fifth line of the command generation program 210.
Reference numeral 226 denotes a command generated by the description on the sixth line of the command generation program 210.
[0014]
Reference numeral 227 denotes a command generated by the description on the seventh line of the command generation program 210.
According to the description “add & sub” on the first line of the instruction word generation program 210, the first basic instruction word is “add”, the second basic instruction word is “sub”, and the third to eighth eighth instruction words are “sub”. A long form command 221 is generated as the second basic command is NOP (no operation command).
[0015]
Similarly, according to the description “load & store” on the second line of the instruction word generation program 210, the first basic instruction word is “load”, the second basic instruction word is “store”, and the third basic instruction word is “store”. The long-form command 222 is generated as the eighth basic command is NOP (no operation command).
[0016]
Even in the case where six basic instruction words are continued only by the "load" instruction like the instruction word 223, the instruction word generation program 210 repeatedly describes the "load" instruction as shown in the third line.
[0017]
Similarly, long-form command words 224, 225, 226, and 227 are generated based on the descriptions in the fifth, sixth, and seventh lines of the command word generation program 210.
[0018]
[Problems to be solved by the invention]
Since the conventional parallel processing method for a plurality of instructions using long-form instruction words has a fixed length, if the number of basic instructions to be processed in parallel does not reach a predetermined number, a predetermined length is added by adding a NOP instruction. Needed. Therefore, for a program with a low degree of instruction parallelism, the NOP increases, thereby deteriorating the memory use efficiency, reducing the hit rate of the cache memory, and increasing the load of the instruction fetch mechanism.
[0019]
On the other hand, in the superscalar method, the length of instructions executed at the same time is arbitrarily changed according to the degree of parallelism at the time of instruction execution, so there is no decrease in efficiency. However, the number of registers required according to the degree of parallelism How to increase the number is a major issue.
[0020]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a parallel processor and a parallel execution method capable of processing a long-form instruction word as a variable length and efficiently performing parallel processing with a limited number of registers.
[0021]
[Means for Solving the Problems]
The present invention relates to a parallel processing processor for processing a plurality of basic instructions in parallel as one instruction word, wherein the basic instructions are provided with an instruction continuation designation bit for specifying whether or not the basic instructions can be processed at the same timing. An instruction buffer for storing instructions for each basic instruction, arithmetic units for calculating the basic instructions of the instruction buffer, a register for storing the arithmetic result of each arithmetic unit, and a value of the instruction continuation designation bit are determined. An instruction suppressing unit for suppressing the input of the basic instruction which is not to be processed at the same timing among the basic instructions to the operation unit; and the instruction suppressing unit is instructed not to perform the processing at the same timing. The input of the basic instruction after the basic instruction to the operation unit is suppressed, and the subsequent basic instructions that can be operated at the same timing before that are regarded as one instruction word, and Is intended to parallel processing by input to the arithmetic unit in timing,
Assuming that the one instruction word includes the M basic instructions, an instruction extension control register consisting of M bits and a mask pattern indicating a position of a valid basic instruction among the M basic instructions are stored in the instruction extension control register. An instruction word generation unit for setting an instruction basic control register to generate an instruction word with reference to the instruction extension control register; An instruction word having M basic instructions is generated by setting the basic instruction at a position corresponding to the pattern and giving no operation instruction or no instruction at a position corresponding to the mask pattern indicating that the instruction is invalid. Has a configuration.
[0022]
FIG. 1 shows the basic configuration of the present invention.
In FIG. 1 (a),
1 is a parallel processing processor.
[0023]
Reference numeral 2 denotes an instruction word, which includes a plurality of basic instructions. FIG. 1 illustrates an example in which six basic instructions constitute one instruction.
2 'is an instruction buffer for inputting and holding each basic instruction of the instruction word 2.
Reference numeral 3 denotes an instruction suppressing unit having an inhibitor 1, an inhibitor 2, an inhibitor 3, an inhibitor 4, an inhibitor 5, an inhibitor 6,... Each suppressor inputs a basic instruction at a position corresponding to each of the instruction words 2 from the instruction buffer 2 ′, and according to the instruction continuation designation bits of each basic instruction of the instruction word, the basic instructions that cannot be executed at the same timing. Execution is deterred. For example, if the instruction continuation designation bit is 0, it is executed at the same timing, and 1 indicates the end of a series of basic instructions that can be executed at the same timing.
[0024]
Reference numeral 4 denotes a decoder unit having decoders 1, 2 and 3, decoder 4, decoder 5, decoder 6,..., And decoder M corresponding to each of the suppressors, and a determination result of the corresponding suppressor. Is to decode the basic instruction of the instruction word 2 input according to.
[0025]
Reference numeral 5 denotes an operation unit, which has an operation unit 1, an operation unit 2, an operation unit 3, an operation unit 4, an operation unit 5, an operation unit 6, ..., an operation unit M, and each operation unit corresponds to each operation unit. This is for inputting the operation result of the decoder.
[0026]
Reference numeral 6 denotes a register section, which has a register space 1, a register space 2, a register space 3, a register space 4, a register space 5, a register space 6, ..., a register space M, and each register space corresponds to each. It holds the operation result of the operation unit.
[0027]
In command word 2,
10 and 11 are instruction continuation designation bits.
[0028]
[Action]
The operation of FIG. 1A will be described.
Each of the suppressors (1 to M) of the command suppressing unit 3 inputs a basic command at a corresponding position. Each inhibitor determines the value of the instruction continuation inhibition bit of each input basic instruction. For example, if the value is 0, it is assumed that the instructions are processed in parallel at the same timing. If the value is 1, the subsequent basic instruction inhibits the input to the decoder (up to the basic instruction having an instruction continuation inhibition bit value of 1). Input to the decoder).
[0029]
Therefore, the decoder unit 4 decodes the basic instructions input to the respective decoders and inputs the basic instructions to the arithmetic units (1 to M) connected to the respective decoders. The operation unit 5 performs an operation process on the instruction input in each of the operation units (1 to M). The register unit 6 stores the operation results of the operation units connected to the respective registers in the corresponding registers.
[0030]
FIG. 1B is a diagram illustrating the relationship between the number of basic instructions and the number of register spaces that can be processed in parallel at the same timing as the length of instruction words to be processed in parallel in the present invention.
FIG. 1B assumes that the number of register spaces is M. It is also assumed that the length of the basic instruction word included in the instruction word is N bits, and the number of basic instructions included in the instruction word is P.
[0031]
A basic instruction sequence followed by an instruction continuation bit having a value of 0 and a basic instruction having an instruction continuation bit having a value of 1 appearing after the series of instruction continuation bits are regarded as one instruction word, and a maximum of M (P = 1, 2,. , M) can be processed at the same timing. That is, the length of one instruction word that can be parallelized is M in the case of P = 1, 2,..., M.
[0032]
FIG. 2 is an operation example of the present invention.
FIG. 2A is an operation example, and FIG. 2B is an explanatory diagram of a register space.
In FIG. 2 (a),
An instruction word 21 has a basic instruction 1, a basic instruction 2, a basic instruction 3, a basic instruction 4, and a basic instruction 5. The instruction continuation bit of the basic instruction 1 is 0, and the instruction continuation bit of the basic instruction 2 is 1, and the basic instructions 1 and 2 have been processed last time.
[0033]
Reference numeral 22 denotes an instruction word 2, which is an instruction following the instruction word 1, and has a basic instruction 1, a basic instruction 2, a basic instruction 3, a basic instruction 4, a basic instruction 5, and a basic instruction 6.
The instruction continuation bit from the basic instruction 1 to the basic instruction 5 of the instruction word 1 (21) and the basic instruction 1 to the basic instruction 4 of the instruction word 2 (22) is 0. Since the continuation bit becomes 1, the processing from the basic instruction 3 of the instruction word 1 (21) to the basic instruction 5 of the basic instruction 2 (22) is subjected to the current processing. The instruction after the basic instruction 6 of the instruction word 2 (22) is processed next time.
[0034]
Reference numeral 29 denotes an instruction buffer for inputting and holding a basic instruction of an instruction word.
Reference numeral 30 denotes an instruction suppressing unit, which includes the suppressors 1 to 8.
[0035]
A decoder unit 31 includes decoders 1 to 8.
Reference numeral 32 denotes an operation unit, which includes operation units 1 to 8.
A register unit 33 includes register spaces 1 to 8.
[0036]
In FIG. 2A, up to the basic instruction 2 of the instruction word 1 (21) is processed at the previous timing. At this timing, each suppressor of the command suppressing unit 30 inputs a corresponding basic command. The suppressor 1 is the basic instruction of the instruction word 1 (21) 3, the suppressor 2 is the basic instruction 4, the suppressor 3 is the basic instruction word 5, and the suppressor 4 is the basic instruction 1 of the next instruction word 2 (22). , The suppressor 5 receives the basic instruction 2, the suppressor 6 receives the basic instruction 3, the suppressor 7 receives the basic instruction 4, and the suppressor 8 receives the basic instruction 5. Therefore, each suppressor determines the instruction continuation bit, and does not suppress the basic instruction up to the basic instruction 6 of the instruction word 2 (22) where the instruction continuation bit is 0 and the subsequent basic instruction and the instruction continuation bit is 1. Transfer to the decoder connected to each. In FIG. 2A, the number of uninhibited basic instructions and the number of register spaces are the same. For example, if the instruction continuation bit of the basic instruction 4 of the instruction word 2 (22) is 1, up to the basic instruction 4 Is transferred to the decoder.
[0037]
Each decoder of the decoder unit 31 decodes a basic instruction input thereto, each arithmetic unit of the arithmetic unit 32 performs an arithmetic operation on each instruction, and the register space of the register unit 33 stores the arithmetic operations of the arithmetic units connected to the respective units. Hold the result.
[0038]
FIG. 2B is an explanatory diagram of the register space.
Reference numeral 40 denotes a register space 1, which has a plurality of (for example, 64) individual registers 45.
[0039]
41 is a register space 2.
42 is a register space M.
An individual register 45 is, for example, a 128-bit register.
[0040]
FIG. 2B shows that one register space has 64 individual registers of, for example, 128 bits.
In the above description, if all the instruction continuation bits in the instruction buffer are 0, an exception of the instruction format is detected, and the start address of the instruction is notified to the operating system. The operating system divides this "long instruction word exceeding the allowable range of hardware" into an appropriate length and re-executes it. Alternatively, each basic instruction word is executed by sequentially simulating the basic instructions held in the instruction buffer.
[0041]
According to the present invention, a fixed-length long instruction word can be handled as a variable-length instruction word. When there are few basic instructions that can be processed in parallel at the same timing, the basic instructions that can be processed at the same timing with the next instruction word can be processed in parallel. Therefore, the execution speed of the parallel processing is increased, and the number of NOP instructions and the like added to make the instruction words have a fixed length is reduced, so that the memory use efficiency can be improved.
[0042]
【Example】
FIG. 3 shows an embodiment of the present invention.
In FIG.
51 is the current instruction word.
[0043]
A0 is a basic instruction whose instruction continuation designation bit is 0.
A1 is a basic instruction whose instruction continuation designation bit is 0.
A2 is a basic instruction whose instruction continuation designation bit is 0.
[0044]
A3 is a basic instruction whose instruction continuation designation bit is 0.
A4 is a basic instruction whose instruction continuation designation bit is 0.
A5 is a basic instruction whose instruction continuation designation bit is 1.
[0045]
52 is a next instruction word.
B0 is a basic instruction whose instruction continuation designation bit is 0.
B1 is a basic instruction whose instruction continuation designation bit is 0.
[0046]
55 is a parallel processing processor.
An instruction buffer 58 has eight buffers (60, 61, 62, 63, 64, 65, 66, 67). FIG. 3 shows a basic instruction (A0), a basic instruction (A1), a basic instruction (A2), a basic instruction (A3), a basic instruction (A4), a basic instruction (A5), a basic instruction (B0), This shows a state where the basic instruction (B1) is stored.
[0047]
Reference numeral 71 denotes an instruction continuation designation bit detector which inputs the instruction continuation designation bit (0) of the basic instruction (A0) in the buffer 60 and detects its value.
Reference numeral 72 denotes an instruction continuation designation bit detector which inputs the instruction continuation designation bits of the basic instructions (A0, A1) of the buffers 61 and 62 and detects the value thereof.
[0048]
An instruction continuation designation bit detector 73 inputs the instruction continuation designation bits of the basic instructions (A0, A1, A2) of the buffers 60, 61, and 62 and detects the value.
[0049]
An instruction continuation designation bit detector 74 inputs the instruction continuation designation bits of the basic instructions (A0, A1, A2, A3) of the buffers 60, 61, 62, and 63 and detects the value thereof. .
[0050]
Reference numeral 75 denotes an instruction continuation designation bit detector, which inputs the instruction continuation designation bits of the basic instructions (A0, A1, A2, A3, A4) of the buffers 60, 61, 62, 63, and 64 and detects the value thereof. Is what you do.
[0051]
Reference numeral 76 denotes an instruction continuation designation bit detector, which inputs instruction continuation designation bits of the basic instructions (A0, A1, A2, A3, A4, A5) of the buffers 60, 61, 62, 63, 64, and 65. That value is detected.
[0052]
Reference numeral 77 denotes an instruction continuation designation bit detector which detects the instruction continuation designation bits of the basic instructions (A0, A1, A2, A3, A4, A5, B0) of the buffers 60, 61, 62, 63, 64, 65, 66. Input and detect the value.
[0053]
Reference numeral 80 denotes an instruction suppression unit which includes inhibitors 81 to 87, and passes or inhibits a basic instruction input according to the detection value of each instruction continuation designation bit detector (71 to 77).
[0054]
Reference numeral 81 denotes a suppressor 1, which receives the basic instruction (A1) of the buffer 61 and passes or suppresses the input basic instruction (A1) according to the detection value of the instruction continuation designation bit detector 71. .
[0055]
Reference numeral 82 denotes a suppressor 2, which inputs the basic instruction (A2) of the buffer 62 and passes or suppresses the input basic instruction (A2) according to the detection value of the instruction continuation designation bit detector 72. .
[0056]
Reference numeral 83 denotes a suppressor 3, which inputs the basic instruction (A3) of the buffer 63 and passes or inhibits the input basic instruction (A3) according to the detection value of the instruction continuation designation bit detector 73. .
[0057]
Reference numeral 84 denotes the suppressor 4, which inputs the basic instruction (A4) of the buffer 64 and passes or inhibits the input basic instruction (A4) according to the detection value of the instruction continuation designation bit detector 74. .
[0058]
Reference numeral 85 denotes a suppressor 5, which inputs the basic instruction (A5) of the buffer 65 and passes or inhibits the input basic instruction (A5) according to the detection value of the instruction continuation designation bit detector 75. .
[0059]
Reference numeral 86 denotes the suppressor 6, which inputs the basic instruction (B0) of the buffer 66 and passes or inhibits the input basic instruction (B0) according to the detection value of the instruction continuation designation bit detector 76. .
[0060]
Reference numeral 87 denotes a suppressor 7, which inputs the basic instruction (B1) of the buffer 67 and passes or inhibits the input basic instruction (B1) according to the detection value of the instruction continuation designation bit detector 77. .
[0061]
Reference numeral 90 denotes a decoder unit which includes a decoder 1, a decoder 2, a decoder 3, a decoder 4, a decoder 5, a decoder 6, a decoder 7, and a decoder 8.
An operation unit 100 includes an operation unit 1, an operation unit 2, an operation unit 3, an operation unit 4, an operation unit 5, an operation unit 6, an operation unit 7, and an operation unit 8.
[0062]
Reference numeral 110 denotes a register unit having a register space 1, a register space 2, a register space 3, a register space 4, a register space 5, a register space 6, a register space 7, and a register space 8.
[0063]
The operation of the configuration of FIG. 3 will be described.
Each buffer (60, 61, 62, 63, 64, 65, 66, 67) of the instruction buffer 58 inputs a basic instruction A0, A1, A2, A3, A4, A5, B0, B1.
[0064]
The basic instruction A0 is directly input to the decoder 1.
The instruction continuation designation bit detector 71 receives the instruction continuation designation bit (0) of the basic instruction A0. Then, the suppressor inputs the detection result of the instruction continuation designation bit detector 71 and the basic instruction A1. Since the instruction continuation designation bit is 0, the suppressor 81 passes the basic instruction A1 and inputs it to the decoder 2.
[0065]
The instruction continuation designation bit detector 72 inputs the instruction continuation designation bit (0) of the basic instructions A0 and A1. Then, the suppressor 82 receives the detection result of the basic instruction A2 and the instruction continuation designation bit detector 72. Since the instruction continuation designation bits are all 0, the suppressor 82 passes the basic instruction A2 and inputs it to the decoder 3.
[0066]
The instruction continuation designation bit detector 73 inputs the instruction continuation designation bit (0) of the basic instructions A0, A1, A2. Then, the suppressor 83 inputs the detection result of the basic instruction A3 and the instruction continuation designation bit detector 73. Since the instruction continuation designation bits are all 0, the instruction is passed to the decoder 4 through the basic instruction A3.
[0067]
The instruction continuation designation bit detector 74 inputs the instruction continuation designation bit (0) of the basic instructions A0, A1, A2, A3. Then, the suppressor 84 inputs the detection result of the basic instruction A4 and the instruction continuation designation bit detector 74. The suppressor 84 passes the basic instruction A4 and inputs it to the decoder 5 because the instruction continuation designation bit is all 0s.
[0068]
The instruction continuation designation bit detector 75 inputs the instruction continuation designation bit (0) of the basic instructions A0, A1, A2, A3, and A4. Then, the suppressor 85 inputs the detection result of the basic instruction A5 and the instruction continuation designation bit detector 75. The suppressor 85 passes the basic instruction A5 and inputs the instruction to the decoder 6 because the instruction continuation designation bit is all 0s.
[0069]
The instruction continuation designation bit detector 76 receives the instruction continuation designation bit (0) of the basic instructions A0, A1, A2, A3, and A4 and the instruction continuation designation bit (1) of the basic instruction A5. Then, the suppressor 86 inputs the detection result of the basic instruction B0 and the instruction continuation designation bit detector 76. The suppressor 86 suppresses the passage of the basic instruction B0 because the instruction continuation designation bit has "1".
[0070]
The instruction continuation designation bit detector 77 includes an instruction continuation designation bit (0) for the basic instructions A0, A1, A2, A3, and A4, an instruction continuation designation bit (1) for the basic instruction A5, and an instruction continuation designation bit (0) for the basic instruction B0. ). Then, the suppressor 87 inputs the detection result of the basic instruction B1 and the instruction continuation designation bit detector 77. The suppressor 87 suppresses the passage of the basic instruction B1 because the instruction continuation designation bit has 1 in it.
[0071]
The decoder 1, decoder 2, decoder 3, decoder 4, decoder 5, and decoder 6 decode the basic instructions (A0, A1, A2, A3, A4, A5) respectively input. The basic instructions decoded by the respective decoders are input to arithmetic units connected to the respective instructions and operated. Then, the operation results are held in register spaces (1 to 6) connected to the respective operation units (1 to 6).
[0072]
FIG. 4 shows a first embodiment of the present invention, in which data is transferred between registers.
In FIG.
Reference numeral 120 denotes a long format instruction word, which is composed of P basic instruction words 121 of N bits (P = 1, 2,..., M (maximum number of register spaces)), each of which has an instruction continuation designation bit. With
[0073]
121 is a basic instruction word.
Reference numeral 130 denotes a decoder unit, which includes a decoder 1, a decoder 2, a decoder 3, a decoder 4, a decoder 5, and a decoder 6.
[0074]
Reference numeral 131 denotes an operation unit, which includes an operation unit 1, an operation unit 2, an operation unit 3, an operation unit 4, an operation unit 5, and an operation unit 6.
Reference numeral 132 denotes a register unit, which includes a register space 1, a register space 2, a register space 3, a register space 4, a register space 5, and a register space 6.
[0075]
Reference numeral 133 denotes a buffer register which copies and holds the data in the buffer register in the register space of the preceding stage, and inputs the data to the register space 1 according to an instruction from the arithmetic unit 1.
[0076]
Reference numeral 134 denotes a buffer register which receives and holds data in the register space 1 according to an instruction from the arithmetic unit 1.
Reference numeral 135 denotes a buffer register for copying and holding data in the buffer register 134 and inputting the data to the register space 2 according to an instruction from the arithmetic unit 2.
[0077]
A buffer register 136 receives and holds data in the register space 2 according to an instruction from the arithmetic unit 2.
A buffer register 137 copies and holds the data in the buffer register 136, and inputs the data to the register space 3 according to an instruction from the arithmetic unit 3.
[0078]
A buffer register 138 receives and holds data in the register space 3 in accordance with an instruction from the arithmetic unit 3.
Reference numeral 139 denotes a buffer register which copies and holds the data in the buffer register 138 and inputs the data to the register space 4 according to an instruction from the arithmetic unit 4.
[0079]
Reference numeral 140 denotes a buffer register which receives and holds data in the register space 4 according to an instruction from the arithmetic unit 4.
141 is a buffer register for copying and holding data in the buffer register 140 and inputting it to the register space 5 according to an instruction from the arithmetic unit 5.
[0080]
Reference numeral 142 denotes a buffer register which receives and holds data in the register space 5 according to an instruction from the arithmetic unit 5.
A buffer register 143 copies and holds the data in the buffer register 142 and inputs the data to the register space 6 according to an instruction from the arithmetic unit 6.
[0081]
Reference numeral 144 denotes a buffer register which receives and holds data in the register space 6 according to an instruction from the arithmetic unit 6. The data in the buffer register 144 is copied to a buffer register at a subsequent stage.
[0082]
Reference numeral 146 denotes a long-form instruction word, and its basic instruction 1 includes a store instruction (store Reg → a) that causes the buffer register (a) 134 to hold the contents of the register space 1.
[0083]
147 is a long instruction word, and its basic instruction 2 includes an instruction (Load b → Reg) for loading the contents of the buffer register (b) 135 into the register space 2.
[0084]
When performing data transfer between register spaces, first, the following operation is performed on a basic instruction corresponding to the register space for transmitting data. The case of transferring data from the register space 1 to the register space 2 will be described as an example.
[0085]
First, an instruction (store Reg → a) for storing the contents of the register space 1 in the buffer register a (buffer register 134) is set as the basic instruction 1 of the long-form instruction word 146 (the basic instruction 1 is set in the transfer program). The contents of the register space 1 are held in the buffer register (a). Next, an instruction (load Reg → b) for loading the contents of the buffer register b into the register space 2 is set in the basic instruction 2 corresponding to the register space 2 for receiving data. The contents of the buffer register b are loaded into the register space 2.
[0086]
FIG. 5 shows a second embodiment of the present invention.
In FIG.
Reference numeral 150 denotes a fetched instruction word (I), which is a basic instruction.
[0087]
Reference numeral 151 denotes a basic instruction word for setting an instruction extension control register, which sets a mask pattern representing a repetition pattern of the basic instruction word in the instruction word in the instruction extension control register 152.
[0088]
An instruction extension control register 152 is a long-form instruction word that repeats the basic instruction I, and includes a mask pattern composed of a bit representing a position of the basic instruction I and a bit identifying a non-basic instruction I. Have.
[0089]
Reference numeral 153 denotes an instruction generation unit which generates the instruction 154 based on the fetched basic instruction (I) 150 and the mask pattern of the instruction extension control register 152.
[0090]
Reference numeral 154 denotes a long-form instruction word to be executed.
In the second embodiment, when the maximum size of the instruction word is M (M basic instructions), M bits of M bits corresponding to the position (1, 2,..., M) of the basic instruction word one by one. A basic instruction word 151 for setting an instruction extension control register is provided. When a basic instruction word I (150) repeated as an instruction word is fetched, a bit pattern indicating whether the fetched instruction I is a basic instruction, NOP or no instruction is set is extended. Set in the control register. Whether the received basic instruction word follows the mask pattern of the instruction extension control register 152 or not is determined, for example, when the fetched instruction word is only one instruction word, the basic instruction is repeated according to the mask pattern. . Then, when the instruction I is fetched, the basic instruction word 151 of the instruction extension control register setting is referred to, and if the value of the bit position K of the instruction extension control register 152 is 0, the basic instruction word corresponding to the position K is NOP. I do. If the value 0 continues from the middle to the end of the pattern, no basic instruction needs to be set (see FIG. 6). If the value of the position K is 1, the long instruction word 154 is executed by regarding the basic instruction as I.
[0091]
FIG. 6 is an explanatory diagram of a command word generating method according to the second embodiment of the present invention.
In FIG.
160 is a command word generation program.
[0092]
The first line “setlen 0011111100” is a basic instruction word for setting a mask pattern “11111100” in the instruction extension control register.
The second line is a description for generating a command 171 composed of two basic commands, a basic command “add” having a basic command “add & sub” and a basic command “sub”.
[0093]
The third line “load & store” is a description for generating a command 172 composed of two basic commands, a basic command “load” and a basic command “store”.
[0094]
“Load” in the fourth line is a description for generating an instruction word 173 in which the basic instruction word is only “load” and six of which are repeated.
“Load” in the fourth line is a description for generating an instruction word 173 in which the basic instruction word is only “load” and six of which are repeated.
[0095]
“Add” on the fifth line is a description for generating an instruction word 174 in which the basic instruction word is only “add” and six of which are repeated.
“Multit” in the sixth line is a description for generating an instruction word 175 in which the basic instruction word is only “mult” and six of them are repeated.
[0096]
“Store” in the seventh line is a description for generating a command word 176 in which the basic command word is only “store” and which is repeated six times.
The eighth line "branch &nop" is for creating a command composed of the basic command "branch" and two basic commands "nop".
[0097]
Referring to FIG. 5, a description will be given of an instruction word generation method according to the second embodiment of the present invention in FIG.
The basic instruction word 151 (the instruction on the first line of the instruction word generation program 160 in FIG. 6) of the instruction extension control register setting is input, and the mask pattern (11111100) given by the instruction is set in the instruction extension control register. (The mask pattern is different from the mask pattern (11011111) in FIG. 5).
[0098]
Since the program description “add & sub” of the instruction word in the second line is a description of two basic instructions, the instruction word 171 is generated without generating the instruction word according to the mask pattern.
[0099]
Similarly, in the third line, the description "load &store" of the program is a description of two basic instructions, so that the instruction word 172 is generated without depending on the mask pattern.
Since the instruction word fetched according to the description of the fourth line “load” is only one basic instruction, the instruction word generation unit 153 refers to the instruction extension control register 152 and repeats six basic instruction words “load” according to the mask pattern. An instruction 173 is generated.
[0100]
According to the description in the fifth row, the instruction word similarly fetched is only one basic instruction “add”. Therefore, the instruction word generation unit 153 generates the instruction word 174 according to the mask pattern of the instruction extension control register 152.
[0101]
Since the instruction word fetched according to the description in the sixth row is only the basic instruction “multi”, the instruction word generation unit 153 generates the instruction word 175 by referring to the mask pattern of the instruction extension control register 152.
[0102]
According to the description on the seventh line, the fetched instruction word “store” is also only one basic instruction, so that the instruction word 176 is generated by referring to the mask pattern of the instruction extension control register 152.
[0103]
In the eighth line, only the "branch" instruction is sufficient. However, if the basic instruction word is one "branch" instruction, the instruction extension control register is referred to, and an instruction word for repeating six "branch" instructions is generated. Therefore, in order to prevent this, "nop" is added to the basic instruction word to describe two basic instructions, and the instruction word 177 is generated.
[0104]
In the present invention, it is not necessary to add any basic instruction when no basic instruction follows the basic instruction of the instruction word as in each instruction word in FIG.
Comparing the instruction word generation program 160 of this embodiment with the conventional instruction word generation program 210 of FIG. 8, the conventional instruction word generation program 210 requires a total of 29 basic instruction words to be described. In the present invention, a total of 11 basic instructions may be described. In addition, in the conventional instruction word, it is necessary to add a large number of NOP instructions to form a fixed-length instruction word, whereas in the present invention, this is not necessary as shown in FIG. Significantly improved. Also, the hit rate in a cache memory or the like increases.
[0105]
【The invention's effect】
According to the present invention, a fixed-length long instruction word can be handled as a variable-length instruction word. When there are few basic instructions that can be processed in parallel at the same timing, the basic instructions that can be processed at the same timing with the next instruction word can be processed in parallel. As a result, the execution speed of the parallel processing is increased, and the number of NOP instructions and the like added to make the instruction words have a fixed length is reduced, so that the memory utilization efficiency can be greatly improved. Also, the hit rate in the cache memory is increased.
[Brief description of the drawings]
FIG. 1 is a diagram showing a basic configuration of the present invention.
FIG. 2 is a diagram showing an operation example of the present invention.
FIG. 3 is a diagram showing a configuration of an embodiment of the present invention.
FIG. 4 is a diagram showing a first embodiment of the present invention.
FIG. 5 is a diagram showing a second embodiment of the present invention.
FIG. 6 is a diagram illustrating an instruction word generation method according to a second embodiment of the present invention.
FIG. 7 is a diagram illustrating a conventional long-form instruction word execution method.
FIG. 8 is a diagram showing a conventional method for generating a long-form instruction word.
[Explanation of symbols]
1: Parallel processor
2: Command word
2 ': Instruction buffer
3: Command suppression section
4: Decoder
5: Operation unit
6: Register section
10, 11: Instruction continuation specification bit

Claims (1)

In a parallel processor that collectively processes multiple basic instructions as one instruction word,
The basic instruction shall have an instruction continuation specification bit for specifying whether it can be processed at the same timing.
An instruction buffer for storing a plurality of basic instructions for each basic instruction, an operation unit for operating each of the basic instructions in the instruction buffer, a register for storing the operation result of each operation unit, and a value of the instruction continuation designation bit. An instruction inhibiting unit for discriminating and inhibiting the input of the basic instruction that should not be processed at the same timing among the basic instructions to the arithmetic unit;
The instruction inhibiting unit inhibits the input of the basic instruction after the basic instruction instructed not to be processed at the same timing to the arithmetic unit, and outputs one basic instruction that can be operated at the same timing before that instruction. Are considered as words and input to the arithmetic unit at the same time for parallel processing.
Assuming that the one instruction word includes M basic instructions, an instruction extension control register consisting of M bits and a mask pattern indicating a position of a valid basic instruction among the M basic instructions are stored in the instruction extension control register. An instruction word generation unit that sets the instruction word in a register and generates an instruction word by referring to the instruction extension control register;
Referring to the input basic instruction, the mask pattern is referred to, the basic instruction is set at a position corresponding to the mask pattern indicating validity, and no operation is performed at a position corresponding to the mask pattern indicating invalidity. A parallel processor which generates an instruction word having M basic instructions by giving no instruction or any instruction.

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