JP3569154B2 - Semiconductor device test apparatus and calibration method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device test apparatus for testing a semiconductor device (also referred to as a “DUT”; for example, a semiconductor integrated circuit), and more particularly to a calibration jig for the apparatus and a calibration method thereof.
[0002]
[Problems to be solved by the invention]
FIG. 1 is a sectional view of a conventional semiconductor test apparatus. The test head 70 outputs a test signal for testing the semiconductor device 20 and receives an output signal output from the semiconductor device 20. A performance board 66 for transmitting a signal between the test head 70 and the coaxial cables 62 and 64 is mounted on the test head 70. A coaxial cable 62 transmits the test signal from the performance board 66 to the socket board 60, and transmits the output signal from the socket board 60 to the performance board 66. A socket 50 is provided on the socket board 60, a test signal is supplied to the semiconductor device 20 via a pin 52 and the first terminal 12 of the socket 50, and the output signal is supplied to the semiconductor device 20 via the second terminal 14 and the pin 54. A signal is received from semiconductor device 20.
[0003]
The test head 70 includes a driver 76 (76A, 76B) for generating a test signal, a driver delay circuit 78 (78A, 78B) for delaying the test signal generated by the driver 76, and a comparator 80 (80A, 80A, 80B) and a comparator delay circuit 82 (82A, 82B) for delaying the time from when the comparator 80 receives the output signal to when the output signal is output. A test signal output from each driver 76 is measured by a probe of a measuring instrument such as an oscilloscope, and the delay time given by the driver delay circuit 78 is adjusted so that the timing of the test signal output from each driver is the same. Thereby, the skew between the plurality of drivers 76 can be canceled. Further, the skew between the plurality of comparators 80 can be canceled by adjusting the delay time given by the comparator delay circuit 82.
[0004]
2A and 2B are a top view and a front view of the semiconductor device 20, respectively. Although a TSOP type semiconductor device is shown here, the semiconductor device may be of a type such as QFP or BGA. By preparing sockets 50 corresponding to semiconductor devices of various shapes, any of the semiconductor devices can be similarly tested. The semiconductor device 20 has a semiconductor device input pin 22 for inputting a signal and a semiconductor device output pin 24 for outputting a signal. Is an example , These pins contact the first terminal 12 and the second terminal 14 of the socket 50.
[0005]
FIG. 3 is a sectional view showing the socket 50 and the socket board 60 on which the socket 50 is mounted. When the socket 50 is mounted along the socket guide 58 of the socket board 60, the pins 52 and 54 of the socket 50 are inserted into the through holes 56 of the socket board 60. The core wires of the coaxial cables 62 and 64 are inserted and soldered from below the through hole 59 of the socket board 60. In recent years, since the number of pins of the semiconductor device 20 has increased, it has been difficult to accurately apply a probe such as an oscilloscope to the first terminal 12 of the socket 50. Therefore, a method has been proposed in which the semiconductor device 20 is removed from the socket 50 and the probe is directly brought into contact with the socket board.
[0006]
FIG. 4 is a top view of the socket board 60. The socket board 60 has a through hole 56 for inserting the pins 52 and 54 of the socket 50 and a through hole 59 for inserting and soldering a coaxial cable. On the upper surface of the socket board 60, a ground pattern (GND) and a power supply pattern (VDD) are provided. By applying an oscilloscope probe to the socket board 60, the semiconductor test apparatus can be calibrated.
[0007]
FIG. 5 shows a state where the probe 44 is applied to the socket board 60. The probe 44 has a signal terminal 40 and a ground terminal 42. The socket 50 is removed from the socket board 60 provided in the test apparatus, the signal terminal 40 of the probe 44 is brought into contact with the through hole 56 for the socket, and the ground terminal 42 is brought into contact with the ground pattern on the socket board 60. , The signal supplied to the through hole 56 can be measured. However, when the ground pattern is not near the through hole to be measured, the ground wire of the probe 44 connected to the ground terminal 42 must be lengthened, and the line impedance at the time of measurement increases. In recent years, as the speed of the semiconductor device 20 increases, it is necessary to test the semiconductor device 20 with high accuracy. Therefore, it is necessary to calibrate the semiconductor test device with high accuracy. However, if the line impedance of the signal when measuring the test signal is large, the semiconductor test device cannot be accurately calibrated.
[0008]
Since the signal wiring pattern and the ground pattern are provided adjacent to each other on the performance board 66, when the socket 50, the socket board 60, and the coaxial cables 62 and 64 are removed and the probe is directly brought into contact with the performance board, The line impedance of the signal can be reduced. However, in this case, since the effects of the inductance and stray capacitance of the coaxial cables 62 and 64, the socket board 60, and the socket 50 do not appear in the test signal, accurate calibration in an actual test state cannot be performed.
[0009]
FIG. 6 shows another conventional method for calibrating a semiconductor test apparatus. In this embodiment, a comparator 80 and a programmable load 180 are provided in parallel with the driver 76. By appropriately setting the programmable load 180, a desired load can be applied to the driver 76. When the semiconductor device 20 is removed from the socket 50 and a test signal is output from the driver 76, the test signal is reflected at the upper end of the socket 50 and is input to the comparator 80. By dividing the time (time during which the test signal reciprocates) t1 by 2, the signal transmission time from the driver 76 to the socket 50 can be measured.
[0010]
FIG. 7 shows still another embodiment of the conventional semiconductor test apparatus. A form has been proposed in which two coaxial cables are connected to each pin of the socket 50 as shown in the figure. In this case, even if the semiconductor device 20 is removed to generate a test signal, the test signal is transmitted to the comparator 90 without being reflected by the socket 50. For this reason, it is impossible to measure the test signal transmission time from the driver 76 to the socket 50.
[0011]
FIG. 8 shows a flowchart of a conventional calibration method. First, the probe 44 is brought into contact with the through hole 56 of the socket board 60 and the ground pattern GND, which are measurement points (S302). Next, timing measurement and calibration are performed (S310). That is, the rising or falling timing of the waveform of the test signal output from the one-channel driver is measured, and calibration data is obtained. The setting value of the driver delay circuit 78 is set to an initial state, and a test signal is generated under a predetermined amplitude condition (S312). Next, the timing of the rising waveform of the test signal is measured, and the driver 76 is calibrated with the rising waveform (S314). Next, the timing of the falling waveform of the test signal is measured, and the driver 76 is calibrated with the falling waveform (S316).
[0012]
FIG. 9A shows the waveform of the test signal measured in the timing measurement step (S310). Waveform S ₀ Is the reference timing position t ₀ At 50% level. Waveform S ₁ And S ₂ Is the timing t ₁ And t ₂ At 50% level. The slew rate represents the rising or falling slope of the waveform. The plurality of drivers 76 included in the test head 70 are adjusted to output signals at a slew rate of less than 500 picoseconds / V ± 10%. In the rising waveform measurement step (S314), the delay amount of the driver delay circuit 78 corresponding to each of the plurality of drivers 76 is adjusted as shown in FIG. ₀ Timing t ₁ And t ₂ Are moved to calibrate the plurality of drivers 76. As a result of this movement, setting data obtained by increasing or decreasing the delay amount of the driver delay circuit 78 is obtained as calibration data. If the signal terminal 40 of the probe 44 and the through-hole 56 of the socket board 60 are in a high resistance state due to dust or the like, the level of the test signal becomes small, and the level of 50% is not detected. It is easy to see that poor contact has occurred.
[0013]
FIG. 9C shows the waveform of the test signal when the ground terminal 42 of the probe 44 and the ground pattern GND of the socket board 60 have a poor contact. Waveform S ₄ FIG. 8 is a waveform example when the ground terminal 42 and the ground pattern GND are open. Waveform S ₆ Is a waveform example when there is a high contact resistance between the ground terminal 42 and the ground pattern GND. Waveform S ₄ And S ₆ Has waveform distortion and rounding. However, the waveform S ₄ And S ₆ , The normal waveform S ₀ Since the level of 50% is measured in the same manner as in the above, the contact failure is overlooked and the timing is calibrated. Therefore, since calibration cannot be performed at an appropriate timing position, erroneous calibration may be performed. For example, the waveform S ₆ , The original normal waveform S ₀ The timing shift e ₂ Has occurred. Also, the waveform S ₄ Also the timing shift e ₁ Has occurred. Therefore, the driver 76 is calibrated at an incorrect timing. If the calibration is performed in a state where the timing shift occurs, it may be a factor of deteriorating the accuracy of the calibration or a factor of deteriorating the reliability in the calibration work.
[0014]
As a method of checking for a contact failure, there is a method of measuring a DC resistance at a contact point between the probe 44 and the socket board 60. This method can be applied to a contact failure between the signal terminal 40 of the probe 44 and the through hole 56 of the socket board 60. However, the poor contact between the ground terminal 42 of the probe 44 and the ground pattern GND of the socket board 60, which is the ground line, can be detected because the ground pattern GND is a circuit ground and is commonly connected. Have difficulty.
[0015]
Therefore, an object of the present invention is to provide a semiconductor test apparatus that can solve at least one of the above problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.
[0016]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor having a socket having a first terminal capable of supplying a test signal to a semiconductor device by mounting the semiconductor device, and a driver for outputting a test signal to the first terminal. Mounting a test board having a terminal arrangement similar to the terminal arrangement of the semiconductor device to the socket in order to calibrate the output timing of the test signal in the test apparatus; generating a test signal by a driver; The method includes a detecting step of detecting a test signal that has reached the board, and a setting step of setting an output timing of the test signal based on the test signal detected by the detecting step. Here, it is preferable that the contact terminal of the test board that contacts the first terminal has the same input impedance as the contact terminal of the semiconductor device that contacts the first terminal.
[0017]
According to a second aspect of the present invention, a test board has a ground short pattern that contacts the first terminal and is connected to ground, and the detecting step is output from the driver and reflected by the test board. Measure the test signal.
[0018]
According to the third aspect of the present invention, the semiconductor test apparatus further includes a delay circuit for delaying the test signal, wherein the generating step includes outputting the test signal by the driver, generating a predetermined reference signal, and setting the Has a delay setting step of setting the magnitude of the delay added by the delay circuit based on the phase difference of the test signal detected in the detection step with respect to the reference signal.
[0019]
According to a fourth aspect of the present invention, a test board has a signal wiring pattern in contact with a first terminal and an earth pattern arranged adjacent to the signal wiring pattern, and the detecting step comprises: And a test signal is detected by an electrical characteristic test probe attached to the ground pattern.
[0020]
According to the fifth aspect of the present invention, a semiconductor test apparatus has a plurality of drivers, a socket has a plurality of first terminals associated with each of the plurality of drivers, and the test board has a plurality of first terminals. A plurality of signal wiring patterns associated with each of the plurality of signal wiring patterns, a detecting step being performed on each of the plurality of signal wiring patterns, and a delay setting step comprising: detecting a phase difference measured in each of the plurality of signal wiring patterns; Are set to be the same in each of the plurality of delay circuits.
[0021]
According to the sixth aspect of the present invention, the socket further has a second terminal for contacting the semiconductor device and receiving an electric signal from the semiconductor device, and the semiconductor test apparatus transmits the signal input from the second terminal. The test board further includes a receiving comparator, and the test board is a short board having a short pattern for electrically connecting the first terminal and the second terminal.
[0022]
According to the seventh aspect of the present invention, the test signal output from the driver and passed through the short board is detected by the comparator. Next, a value obtained based on a time difference between a reference timing having a predetermined time difference with respect to the output step and a time when the test signal is detected in the comparator detection step is set as a reference time for testing the semiconductor device. I do. A semiconductor test device is provided with a plurality of drivers and a plurality of comparators, and a socket is provided with a plurality of first terminals associated with each of the plurality of drivers and a plurality of second terminals associated with each of the plurality of comparators. Providing a plurality of short patterns for connecting the plurality of first terminals and the plurality of second terminals to the short board, executing the detection step on each of the plurality of signal wiring patterns, and setting the reference time to each of the plurality of comparators. On the other hand, the reference times may be independently set.
[0023]
According to the eighth aspect of the present invention, the apparatus further includes a plurality of sockets, a plurality of test boards such as a short board corresponding to each of the plurality of sockets, and a frame integrally holding the plurality of test boards. Each frame has a call-in mechanism for moving the test board to a desired position when the frame is mounted at a predetermined position in the semiconductor test apparatus.
[0024]
According to the ninth aspect of the present invention, a driver that outputs a test signal used for testing a semiconductor device, a comparator that receives an electric signal from the semiconductor device, and a semiconductor device mounted on the semiconductor device and transmits the test signal to the semiconductor device In a calibration method for calibrating the processing timing of a semiconductor test apparatus having a socket that can be provided, a connection necessary for providing a test signal or an electrical signal is provided to a measuring instrument for measuring a waveform of the test signal. A connection step, a waveform measuring step of measuring a test signal output by the driver with a measuring instrument, a waveform determining step of determining whether a waveform of the test signal measured by the measuring instrument is within a desired range, and a measuring step of measuring by the measuring instrument. Notify the measurement equipment that the connection is bad when the waveform is outside the desired range It is preferable to provide a knowledge step. In the waveform measuring step, it is preferable to measure at least one of rising and falling waveforms of the test signal. The notification step further includes a reconnection step of repeating the connection step, the waveform measurement step, and the waveform determination step when the waveform is out of a desired range, and the connection step, the waveform measurement step, and the waveform determination step for a predetermined number of times. It is preferable to include a failure notifying step of notifying that the connection made to the measuring instrument is defective when the waveform is out of the desired range even after repetition.
[0025]
According to a tenth aspect of the present invention, in the above-mentioned calibration method, the measuring device is a measuring device external to the semiconductor test device, the measuring device has an electrical characteristic test probe for inputting a test signal, and Preferably, the steps include making the necessary connections to provide a test signal to the electrical property test probe.
[0026]
According to an eleventh aspect of the present invention, in the above-mentioned calibration method, the measuring device is a measuring device inside the semiconductor test device, and the waveform measuring step is performed by outputting the test signal output from the driver and reflected by the socket from the comparator. It is preferable to have a step of performing measurement with a measuring instrument.
[0027]
According to a twelfth aspect of the present invention, in the above-mentioned calibration method, the measuring device is a measuring device inside the semiconductor test apparatus, and the waveform measuring step measures a predetermined reference signal input from the comparator in the measuring device. It is preferable to have steps.
[0028]
According to a thirteenth aspect of the present invention, in the above-mentioned calibration method, the connecting step may include a step of connecting a test board for inputting a test signal for calibration and applying the test signal to the measuring instrument. preferable.
[0029]
According to a fourteenth aspect of the present invention, in the above-mentioned calibration method, the measuring device is a measuring device inside the semiconductor test apparatus, and the waveform measuring step includes the steps of: outputting the test signal output from the driver and reflected by the test board Preferably, the method includes a step of inputting from the comparator and measuring at the measuring device.
[0030]
According to a fifteenth aspect of the present invention, in the above-mentioned calibration method, it is preferable that the waveform determining step determines whether or not the level of the test signal within a rising or falling period of the test signal is within a desired range.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the claimed invention, and all combinations of features described in the embodiments are solutions of the invention. It is not always necessary for the means.
[0032]
FIG. 10 shows a cross section of the entire semiconductor test apparatus according to the present embodiment. 1 are given the same reference numerals as in FIG. 1 and will not be described. On the socket board 60, a plurality of sockets 50 connected to the performance board by coaxial cables 62 and 64 are provided. Also, a plurality of holding units 110 are mounted (mounted) on the frame 100, and an opening 120 is provided at an upper portion of each holding unit. Each holding unit 110 holds one semiconductor device 20. In the test head 70, only the circuits for the two coaxial cables 62 and 64 are shown. However, in actuality, a coaxial cable is provided for each pin of the semiconductor device 20. In addition, a driver 76, a delay circuit 78, a comparator 80, and a comparator delay circuit 82 are provided. Although only a circuit corresponding to one semiconductor device 20 is shown in the figure, a similar circuit is actually provided for each semiconductor device.
[0033]
Since the semiconductor test apparatus can test a plurality of semiconductor devices at the same time, it is possible to test more semiconductor devices in a given time. When calibrating the semiconductor test apparatus, the test board 10 is mounted on each holding unit 110 instead of the semiconductor device 20 in advance. When the frame 100 is mounted on the semiconductor test apparatus, the test board 10 is mounted on the socket 50. Next, a probe is applied to the test board 10 from above the opening 120, and a test signal is generated by the driver 76. The test signal that has reached the test board 10 is detected by an oscilloscope, and the output timing of the test signal is set by changing the setting of the delay circuit 78A based on the detected test signal.
[0034]
The driver 76 is provided for each of a plurality of signals applied to the semiconductor device 20. The test head 70 further has one driver 176 for generating a reference signal and one delay circuit 178 for giving a predetermined delay to the reference signal. The time difference between when the reference signal is generated and when the driver 76 generates the test signal is always constant. Therefore, this reference signal is input to the oscilloscope as a trigger. By making the phase difference between the phase of the test signal output from each driver 76 and the phase of the reference signal the same, it is possible to indirectly align the phases of the plurality of drivers 76 and reduce the skew between the drivers. it can. However, as another form, one test signal reaching the test board 10 may be selected as a reference signal and input as a trigger of an oscilloscope, and the phase of another test signal may be matched to the phase of the selected test signal. .
[0035]
11A and 11B are a top view and a bottom view of a probe board 10A as an example of the test board 10 mounted on the holding unit 110. On the lower surface of the test board 10, contact terminals 30 are provided in the same arrangement as the terminals of the semiconductor device 20. When the frame 100 is attached to the semiconductor test device, the contact terminals 30 come into contact with the first terminal 12 and the second terminal 14 of the socket 50. The ground pattern 36 and the plurality of signal wiring patterns 32 provided on the upper surface are connected to the contact terminals 30 provided on the lower surface. The ground pattern 36 extends to the center of the upper surface. The ground pattern 36 is adjacent to each signal wiring pattern 32, and the shortest distance is about 2 mm or less. Therefore, the signal terminal 40 and the ground terminal 42 of the probe 44 can be easily brought into contact with each of the signal wiring patterns 32 and the ground pattern 36. Further, since the shortest distance between each signal wiring pattern 32 and the ground pattern 36 is substantially equal, variation in line impedance of each signal is small, and each signal can be measured accurately.
[0036]
In order to prevent an error from occurring between the output timing from the driver 76 at the time of calibration and the output timing from the driver 76 when the actual semiconductor device 20 is mounted on the semiconductor test apparatus, each of the contact terminals 30 Preferably, the input impedance of the signal is substantially the same as the input impedance of the signal in the actual semiconductor device 20. In order to make the input impedance the same as that of the semiconductor device 20, an appropriate capacitor (capacitance), a resistor, and the like may be provided between the signal wiring pattern 32 and the ground pattern 36, as is well known.
[0037]
FIG. 12 shows another embodiment of the probe board 10A. The probe board 10 </ b> A is provided with a plurality of contact terminals 30 on the outer peripheral side surface of an insulating block 270 having substantially the same external dimensions as the semiconductor device 20, in substantially the same arrangement as the terminals of the semiconductor device 20. The contact terminal 30 can make contact with the first terminal 12 and the second terminal 14 of the socket 50 on the side surface or the lower surface of the insulating block 270.
[0038]
A plurality of signal wiring patterns 32 are formed at locations extending from the plurality of contact terminals 30 to the periphery of the upper surface of the insulating block 270, respectively. The signal wiring pattern 32 is used to contact the signal terminal 40 of the probe 44. Therefore, the signal wiring pattern 32 has a bulged shape so that the signal terminal 40 can easily contact. A ground pattern 36 is formed inside the plurality of signal wiring patterns 32 so as to extend from the ground terminal 37. The ground pattern 36 is used to contact the ground terminal 42 of the probe 44. Note that the probe 44 is held by a holding bracket 262.
[0039]
Since the ground pattern 36 is adjacent to each signal wiring pattern 32, the signal wiring pattern 32 and the ground pattern 36 can easily contact the signal terminal 40 and the ground terminal 42 of the probe 44. Since the ground terminal 42 and the ground pattern 36 can be brought into contact with each other in a short distance, the ground terminal 42 can be grounded with low impedance. For this reason, the external noise superimposed on the test signal via the conventional ground impedance is reduced, the distortion of the test signal due to the influence of the noise is suppressed, and the accuracy of the calibration is improved. Further, since the signal wiring pattern 32 and the signal terminal 40 can maintain stable contact, noise generated from a contact portion between the signal wiring pattern 32 and the signal terminal 40 and distortion of a test signal due to the noise are suppressed, and calibration is performed. Accuracy is improved.
[0040]
13A and 13B show a short board 10B as another example of the test board 10. FIG. A contact terminal 30 that contacts the first terminal 12 and the second terminal 14 of the socket 50 is provided on the lower surface of the short board 10B. On the upper surface of the short board 10B, a plurality of short patterns 46 for short-circuiting the contact terminals 30 contacting the first terminals and the contact terminals 30 contacting the second terminals 14 are provided. After the probe board 10A shown in FIG. 11 is mounted on the semiconductor test device and the skew between the plurality of drivers 76 is calibrated, the probe board 10A is removed from the semiconductor test device, and the short board 10B shown in FIG. Attach to test equipment.
[0041]
In this state, the skew between the plurality of comparators 80 is calibrated. First, test signals are simultaneously generated from the plurality of drivers 76A. The test signal generated by the driver 76A reaches the comparator 80B via the short board 10B. The approximate delay time from when the driver 76 generates the test signal to when the comparator 80 detects the test signal is known in advance. Thus, for example, when the reference signal is taken into the oscilloscope 150 as a trigger, a time obtained by adding a known delay time by the oscilloscope 150 is selected as the reference timing. However, in another embodiment of the present invention, a time when a reference signal is detected may be selected as the reference timing. This corresponds to a case where zero “0” is selected as the delay time.
[0042]
Next, the time difference from the reference timing to when each of the comparators 80 detects the test signal is measured for each comparator 80, and a value based on this time difference is set as a reference time for testing the semiconductor device 20 and is used as a reference time for each of the comparators 80. Set to. For example, when the time difference is + a, the delay time of the comparator delay circuit 82 corresponding to the comparator 80 is reduced by a, and when the time difference is −a, the delay time by the comparator delay circuit 82 is reduced. a is increased. Thereby, the skew between the plurality of comparators 80 can be calibrated.
[0043]
However, as another embodiment, a memory for storing the delay time may be provided for each comparator 80 instead of the comparator delay circuit 82, and the time difference may be simply stored in the memory. In this case, by subtracting the time difference stored in the memory from the time when the comparator 80 detects when the semiconductor device 20 is actually tested, a value in which the influence of the skew between the comparators 80 can be obtained. As such a memory, in addition to a semiconductor digital memory, an analog memory, a delay circuit capable of setting a delay time, or the like can be used. As a means for reducing the time difference, in addition to subtraction by numerical operation, subtraction by analog operation, subtraction by a delay circuit, and the like can be used.
[0044]
FIG. 14 shows another embodiment of the semiconductor test apparatus. The same components as those shown in FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, the coaxial cable 64 corresponding to the output terminal of the semiconductor device 20 is provided with only the comparator 80B and the comparator delay circuit 82B, and the driver 76B and the driver delay circuit 78B shown in FIG. 10 are omitted. ing. A programmable load 180 for applying a desired load to the driver 76A is provided in parallel with the driver 76A and the comparator 80A.
[0045]
First, the semiconductor device 20 and the test board 10 are removed from the socket 50, and the delay time by the driver delay circuit 78A and the comparator delay circuit 82A is set to zero “0”. Next, the time from when the output voltage of the driver 76A is changed to when the comparator 80A detects the reflected current, that is, the time t1 during which the test signal reciprocates between the driver 76A and the socket 50 is measured. By dividing the time t1 by 2, the time from when the driver 76A generates the test signal to when the test signal is transmitted to the socket 50, that is, the one-way time (t1) / 2 can be obtained. By measuring the transmission time (t1) / 2 of the test signal for each driver 76A, the time difference Δdr of each test signal in the path from the plurality of drivers 76 to the socket 50 can be obtained.
[0046]
FIG. 15 shows a method for further easily obtaining the signal transmission time from the socket 50 to the comparator 80B. The short board 10B is attached to the socket 50, and a test signal is generated by the driver 76A. The test signal is received by the comparator 80B via the coaxial cable 62, the short board 10B, and the coaxial cable 64. The time from when the driver 76 generates the test signal to when the comparator 80B receives the test signal, that is, the signal transmission time t2 between the driver 76 and the comparator 80B is measured, and the transmission time between the driver 76 and the socket 50 is measured. By subtracting (t1) / 2 from t2, the signal transmission time t3 from the socket 50 to the comparator 80B can be obtained. By measuring the transmission time t3 from the socket 50 to each comparator 80B, the time difference Δcp of the test signal in the path from the socket 50 to each comparator 80B can be obtained.
The skew between the drivers 76A can be canceled by changing the delay time set in the driver delay circuit 78 based on the time difference Δdr in the path on the driver 76A side. Further, by changing the delay time set in the delay circuit 82B for the comparator 80B based on the time difference Δcp, the skew between the plurality of comparators 80B can be canceled.
[0047]
FIG. 16 shows still another embodiment of the semiconductor test apparatus. In the present embodiment, two coaxial cables are connected to one terminal of the socket 50. In this case, since the impedance mismatch does not occur in the socket 50 even when the semiconductor device 20 and the test board 10 are removed, the signal transmission time from the driver 76 to the socket 50 and the signal transmission time from the socket 50 to the comparator 90 are obtained. I can't. Therefore, first, an earth short board 10C as an example of the test board 10 is attached to the socket 50. In the ground short board 10C, each test signal is short-circuited to ground. As a result, impedance mismatch occurs in the ground short board 10C, so that the signal generated by the driver 76 is reflected to the comparator 80.
[0048]
Next, the earth short board 10C in FIG. 16 is removed from the socket 50, and the delay time in the delay circuit 92 for the comparator 90 is set to zero “0”. When a test signal is further generated by the driver 76, the test signal is received by the comparator 90 via the coaxial cables 62 and 64, as in the case of FIG. The time from when the driver 76 generates the test signal to when the comparator 90 receives the test signal, that is, the signal transmission time t2 between the driver 76 and the comparator 90 is measured, and the transmission time between the driver 76 and the socket 50 is measured. By subtracting (t1) / 2 from t2, the signal transmission time t3 from the socket 50 to the comparator 90 can be obtained. By measuring the transmission time t3 from the socket 50 to each comparator 90, a time difference Δcp of the test signal in the path from the socket 50 to each comparator 90B is obtained.
The skew between the drivers 76 can be offset by changing the delay time set in the driver delay circuit 78 based on the time difference Δdr in the path on the driver 76 side. Further, by changing the delay time set in the delay circuit 92 for the comparator 90 based on the time difference Δcp, the skew between the plurality of comparators 90 can be canceled.
[0049]
17A and 17B show the configuration of the ground short board 10C. A contact terminal 30 that contacts the first terminal 12 and the second terminal 14 of the socket 50 is provided on the lower surface of the ground short board 10C. On the upper surface of the ground short board 10C, each signal wiring pattern 32 that contacts the first terminal of the socket 50 is short-circuited to the ground pattern 36. For this reason, the line impedance of the test signal rapidly decreases after being short-circuited to the ground by the ground short board 10C. Due to the impedance mismatch, the signal generated by the driver 76A is reflected by the ground short board 10C and detected by the comparator 80A.
[0050]
FIG. 18 shows still another configuration of the semiconductor test apparatus. In the present embodiment, two coaxial cables 62 and 64 are connected to one terminal of the socket 50, and a driver, a driver delay circuit, a comparator, a programmable load, and a comparator delay circuit are connected to each coaxial cable. Have been. In this case, the ground short board 10C is attached to the socket 50, test signals are sequentially generated from the drivers 76 and 77, and the test signals reflected by the socket 50 are detected by the comparators 80 and 90, respectively.
Thereby, the time difference Δdr of the transmission delay time in the line from the driver 76 to the socket 50 and in the line from the driver 77 to the socket 50 can be obtained. Based on the time difference Δdr, the skew between the plurality of drivers 76, the skew between the plurality of drivers 77, the skew between the plurality of comparators 80, and the skew between the plurality of comparators 90 are respectively determined by delay circuits 78, 79, 82 and Calibration can be performed by 83.
[0051]
FIG. 19 shows a modification of the method for calibrating the semiconductor test apparatus shown in FIG. For the sake of easy understanding, the illustration of the delay circuits 78, 79, 82, and 83 shown in FIG. 18 is omitted in FIG. Also, the same components as those shown in FIG. 18 are denoted by the same reference numerals as those in FIG. 18, and the description thereof will be omitted. In this embodiment, a test signal can be supplied from one waveform shaper 160 to two drivers 76 and 77. A gate 162 is provided between the waveform shaper 160 and the driver 77 to control whether or not to pass a test signal. According to the present embodiment, it is not necessary to provide a pattern generator, a waveform formatter, and the like for generating a test signal for each of the drivers 76 and 77, so that the test apparatus can be configured at low cost.
[0052]
FIG. 20 is an enlarged view of the opening 120 of the frame 100, the holding unit 110, and the test board 10. The column member 104 of the frame 100 is passed through the holding unit 110, and the holding unit 106 prevents the holding unit 110 from coming off. The holding unit 110 can hold the test board 10 or the semiconductor device 20. Since a large clearance is provided between the holding unit 110 and the columnar member 104, each of the time keeping units 110 can be freely displaced with respect to the frame 100 within the range of the clearance. The spring 102 presses the holding unit 110 against the socket 50. The socket 50 is provided with a positioning rod 108 having a conical tip.
The positioning rod 108 functions as a loading mechanism that loads each holding unit 110 and the test board 10 to an appropriate position. That is, by inserting the positioning rod 108 into the positioning hole provided in the holding unit 110, the holding unit is displaced to an appropriate position. Therefore, the first terminal 12 and the second terminal 14 of the socket 50 can accurately contact the contact terminal 30 of the test board 10 or the semiconductor device 20.
[0053]
FIG. 21 is a top view of the frame 100. At both ends of the frame 100, handles 140 for gripping the frame 100 with human hands or a robot are provided. Each holding unit 110 can be freely displaced within the frame 100 independently of the other holding units 110. Conventionally, in order to ensure that each of the holding units 110 comes into contact with the socket 50, each holding unit is first mounted on the socket, and then the holding unit is fixed from above. According to the present embodiment, when the frame 100 is mounted on the semiconductor test apparatus, each holding unit 110 is displaced to an appropriate position, so that a large number of test boards 10 or the semiconductor devices 20 can be easily mounted or removed. Can be.
[0054]
In particular, by preparing a plurality of frames 100 on which necessary types of test boards 10 are mounted in advance and a frame 100 on which the semiconductor device 20 is mounted, the plurality of test boards 10 Can be changed or the semiconductor device 20 can be changed.
[0055]
In the above embodiment, the semiconductor test apparatus is calibrated by mounting the test board 10 in the socket 50 instead of the semiconductor device 20. According to the above embodiment, the signal line when actually testing the semiconductor device and the signal line when calibrating the semiconductor test apparatus are substantially the same, so that the line impedance in each case is substantially equal. Therefore, the semiconductor test apparatus can be calibrated in a state close to actual use. However, as another embodiment, for example, the semiconductor device 20 and the socket 50 may be removed from the semiconductor test apparatus, and the test board 10 may be directly attached to the socket board 60. In this case, the line impedance in the actual use state is slightly different from the line impedance at the time of calibration. However, since the area of the socket board 60 is larger than that of the upper side of the socket 50, the probe 44 can be easily brought into contact with the signal line.
[0056]
FIG. 22 is a top view of the socket board 60 to which the probe board 10D is attached. On the upper surface of the probe board 10D, signal wiring patterns 132 are arranged at a predetermined interval from each other. For this reason, when the signal terminal 40 of the probe 44 is brought into contact, it is possible to prevent the signal terminal 40 from being short-circuited to another signal wiring pattern. An earth pattern 136 is provided on the upper surface of the probe board 10D. The ground pattern 136 is adjacent to each signal wiring pattern 132, and the shortest distance is about 2 mm or less. Therefore, the signal terminal 40 and the ground terminal 42 of the probe 44 can be easily brought into contact with each of the signal wiring patterns 132 and the ground pattern 136. Further, since the shortest distance between each signal wiring pattern 132 and the ground pattern 136 is substantially equal, variation in line impedance of each signal is small, and each signal can be accurately measured.
[0057]
A large number of test boards 10 to be attached in place of the semiconductor device 20 and the socket 50 may be prepared, and each of them may be held by the holding unit 110 shown in FIG. In an actual semiconductor test, a socket 50 for the semiconductor device 20 is mounted on the holding unit 110 in addition to the semiconductor device 20, and further mounted on the frame 100. By preparing each of the frames 100 to which necessary types of test boards are attached, the types of many test boards 10 can be easily exchanged only by exchanging the frame 100, or the test boards 10 can be replaced with the semiconductor devices 20. Can be exchanged.
In the above calibration, various terminals need to be brought into contact with each other, but this may be performed using a robot instead of manually. Thereby, not only can a uniform pressure be applied, but also productivity can be improved. Further, in the present embodiment, the test signal is detected by the oscilloscope. However, the test signal may be detected by using, for example, a standard driver and a standard comparator.
[0058]
As described above, according to the present embodiment, the accuracy of calibration of the semiconductor test apparatus can be improved. Further, since a plurality of semiconductor devices can be easily mounted on the test apparatus, the productivity of the semiconductor test can be improved.
[0059]
FIG. 23 shows another embodiment of the test board 10. In FIG. 23, the components denoted by the same reference numerals as those in FIG. 10 have the same configurations as those in FIG. The test board 10 is set on the test head 70 so as to contact the pogo pins 204 provided on the test head 70. The contact terminals 30 formed on the lower surface of the test board 10 are formed in accordance with the arrangement of the pogo pins 204 of the test head 70. The signal wiring pattern 32 and the ground pattern 36 formed on the upper surface of the test board 10 are formed in accordance with the arrangement of the signal terminal 40 and the ground terminal 42 of the probe 44. The signal wiring pattern 32 and the ground pattern 36 of the test board 10 are electrically connected to the contact terminals 30. In this manner, by arranging the contact terminals 30 of the test board 10 in accordance with the arrangement of the terminals of the socket board 60, the performance board 66, or the test head 70, not only the test board 10 is mounted on the socket 50, but also the socket. It can be mounted on the board 60, the performance board 66, or the test head 70.
[0060]
The test head 70 receives a command from the test apparatus main body 208, generates a test signal of a predetermined level, and supplies the test signal to the test board 10 via the pogo pin 204. The test head 70 includes the pin electronics 206 therein. The pin electronics 206 includes a plurality of drivers 76 (not shown), a driver delay circuit 78, a comparator 80, and a comparator delay circuit 82. The oscilloscope 200 is a measuring instrument that has been calibrated in advance. The oscilloscope 200 and the test apparatus main body 208 are connected by communication means such as GPIB that can be controlled bidirectionally. Therefore, measurement can be performed under desired conditions, and the timing data of the measurement result is used in the test apparatus main body 208 for calibration data or determination processing. The test apparatus main body 208 has a main body delay circuit 210 and can adjust set values of delay times of the driver delay circuit 78 and the comparator delay circuit 82 included in the pin electronics 206.
[0061]
A reference pulse signal 220 is input to a trigger input terminal of the oscilloscope 200 from a reference signal terminal 221 provided in the test head 70. The timing at which the driver 76 outputs the test signal is adjusted by the reference pulse signal 220. The signal terminal 40 and the ground terminal 42 of the probe 44 connected to the oscilloscope 200 are in contact with and electrically connected to the signal wiring pattern 32 and the ground pattern 36 of the test board 10.
[0062]
FIG. 24 shows a connection diagram of the semiconductor test apparatus shown in FIG. The test board 10 is in contact with the pogo pins 204 provided at the output end P1 of the pin electronics 206 at the contact terminals 30 to be electrically connected. Calibration is performed so that the timing at which the plurality of drivers 76 output the test signals in the signal wiring pattern 32 of the test board 10 is the same for all drivers.
[0063]
FIG. 25 is a flowchart showing a method for calibrating the semiconductor test apparatus shown in FIG. 23 or FIG. However, the calibration method shown in this flowchart is not limited to the semiconductor test device shown in FIG. 23 or FIG. 24, and a signal obtained from the test object by contacting the probe 44 with the test object is measured outside the test device. Applicable to a test device that measures with an instrument. In the conventional calibration method, there is a possibility that a contact failure between the probe 44 and the measurement target cannot be detected. Therefore, in the present embodiment, before the calibration of the driver 76, the contact between the probe 44 and the measurement target is checked.
[0064]
First, the signal terminal 40 and the ground terminal 42 of the probe 44 are brought into contact with the signal wiring pattern 32 and the ground pattern 36 of the test board 10 (S302). Next, when the probe 44 is in contact with the test board 10, the slew rate value, which is the time required for the rise or fall of the waveform of the test signal output from the driver 76, is given to the oscilloscope 200 connected to the probe 44. (S304). The quality of the contact check between the probe 44 and the test board 10 may be determined by either the rising or falling of the waveform. Next, it is determined whether the measured slew rate value is within the range of the desired slew rate value, and the process branches (S306).
[0065]
When it is determined in the slew rate determination step (S306) that the slew rate value is out of the desired range, the probing step (S302), the slew rate measurement step (S304), and the slew rate determination step (S306) are determined. Repeat the number of times. Further, it is determined whether the probing step (S302), the slew rate measuring step (S304), and the slew rate determining step (S306) have been repeated a predetermined number of times (S322). If it is determined that the slew rate value is out of the desired range even after repeating the probing step (S302), the slew rate measuring step (S304), and the slew rate determining step (S306) a predetermined number of times, the probe 44 The failure of contact between the semiconductor test apparatus and the test board 10 is notified to the outside of the semiconductor test apparatus (S326). The test operator checks the connection failure portion of the transmission line between the driver 76 and the test board 10 to remove dust.
[0066]
FIG. 26 shows three types of probing contact waveforms when the waveform measured in the slew rate measurement step (S304) rises. First waveform S ₀ Is a case of a good contact state, and the second waveform S ₄ Is an example in which the ground terminal 42 of the probe 44 and the ground pattern 36 of the test board 10 are open, and the third waveform S ₆ Is an example in the case where there is a high contact resistance of several hundred Ω between the ground terminal 42 and the ground pattern 36. The slew rate value is obtained by calculating the difference between the times when the waveform levels reach the respective thresholds, using the 20% and 80% levels as thresholds for the 100% level.
[0067]
First waveform S ₀ Is the case where the slew rate value Tr1 substantially matches the normal slew rate value, and it can be easily determined that the contact state is good. Next, the second waveform S ₄ Indicates a slew rate value several times the normal slew rate value Tr1. Therefore, it can be determined that the ground terminal 42 and the ground pattern 36 are in poor contact. Also, the third waveform S ₆ The slew rate value Tr2 also shows a slew rate value several times the normal slew rate value Tr1. Therefore, also in this case, it can be determined that the ground terminal 42 and the ground pattern 36 are in poor contact.
[0068]
As yet another embodiment, instead of measuring the slew rate value, a desired threshold range is set based on the level of a normal signal at a specific time within the rising or falling period of the test signal, and the measurement is performed. The contact failure may be determined based on whether or not the level of the obtained signal falls within a desired threshold range. For example, when the timing of measuring the waveform level is Ts and the range of the threshold is a level within 20% from the level of 100% of the normal signal, that is, a level of 80% or more of the normal signal, the waveform S ₀ Is within the range of the threshold, but the waveform S ₆ And waveform S ₄ Is out of the range of the threshold. Therefore, the waveform S ₀ The contact state is good and the waveform S ₆ And S ₄ In, it can be determined that the contact state is bad.
[0069]
FIG. 27 shows a schematic diagram and a connection diagram of a semiconductor test apparatus for showing still another embodiment of the calibration method. In FIGS. 27A and 27B, the components denoted by the same reference numerals as those in FIGS. 23 and 24 have the same configurations as those in FIGS. The performance board 66 is installed so as to be in contact with the pogo pins 204, and is electrically connected to the pogo pins 204. The socket 50 on which the semiconductor device 20 or the test board 10 is mounted is connected to a performance board 66 by a coaxial cable 64. The socket 50 inputs a test signal generated by the driver 76 in the pin electronics 206 through the pogo pin 204, the performance board 66, and the coaxial cable 64, and provides the semiconductor device 20 or the test board 10 with the test signal. In the semiconductor test device shown in FIG. 27, there is a possibility that a contact failure occurs at a contact portion 272 between the pogo pin 204 and the performance board 66.
[0070]
FIG. 28 is a flowchart showing an embodiment of the calibration of the semiconductor test apparatus shown in FIG. First, the reflected waveform output from the driver 76 and reflected from the socket 50 is input using the comparator 80 connected to the driver 76, and the reflected waveform input from the comparator 80 is measured in the test apparatus main body 208. (S404). Next, the test apparatus main body 208 determines whether the measured reflected waveform is within a desired range, and if it is determined to be defective, the process branches to a loop count determination step (S322) (S406).
[0071]
When it is determined that the reflection waveform is out of the desired range, the performance board 66 and the pogo pin 204 are re-contacted (S424), and the reflection waveform measurement step (S404) and the reflection waveform determination step (S406) are repeated. . Next, it is determined whether the re-contact step (S424), the reflected waveform measuring step (S404), and the reflected waveform determining step (S406) have been repeated a predetermined number of times (S322). If it is determined that the measured waveform is out of the desired range even after repeating the re-contacting step (S424), the reflected waveform measuring step (S404), and the reflected waveform determining step (S406) a predetermined number of times, the performance is determined. The contact failure between the board 66 and the pogo pins 204 is notified to the outside of the semiconductor test apparatus (S326).
[0072]
FIG. 29 shows an example of the reflection waveform measured in the reflection waveform measurement step (S404). In the reflection waveform measurement step (S404), the transition waveform S shown in FIG. ₁₀ Is measured. Transition waveform S ₁₀ Is a transition waveform in a normal case. The transition of the reflected waveform is determined by the output of the driver 76 and the length of the transmission line. In other words, as shown in FIG. ₁₀ First transitions at a level V2, which is half of the level V4, and reaches the level V4 after a lapse of a round-trip time T1 during which a pulse reciprocates in the transmission line. Transition waveform S ₁₀ Is the measured transition waveform S ₁₂ Used as a reference to be compared to. In the reflected waveform determination step (S406), the transition waveform S ₁₂ Data and the reference transition waveform S ₁₀ Is calculated, and the distribution state D which is the amount of the difference is calculated. ₁₀ Is used to determine the quality of the waveform.
[0073]
The calibration method shown in FIGS. 28 and 29 is also applicable to the calibration method of generating a reflection signal using the ground short board 10C shown in FIGS. 17, 18, and 19. Further, even when the test board 10 shown in FIG. 23 is mounted in a place other than the socket 50, the reflection signal can be generated by using the earth short board 10C as the test board 10, so that the present invention is applicable.
[0074]
FIG. 30 shows another embodiment of the calibration method for the comparator 80. The probe 44 is connected to the reference signal terminal 221, and the reference pulse signal 220 input from the reference signal terminal 221 is applied to the test board 10 via the probe 44, except that the probe 44 is similar to the semiconductor test apparatus shown in FIG. Configuration. As a method of calibrating the comparator 80, there is a method in which the reference pulse signal 220 is supplied to the test board 10 as a reference timing to input the reference timing to the plurality of comparators 80 and perform calibration. Also in the method of calibrating the comparator 80, the method of detecting a contact failure described with reference to FIGS. 25 and 26 can be applied. For example, when there is a contact failure between the probe 44 and the test board 10, the comparator 80 supplies the waveform S shown in FIG. ₄ Or S ₆ A reference pulse signal 220 having a waveform similar to the above is input. Also in this case, for example, the waveform S ₀ The time required for each waveform to reach the threshold level may be measured using the 20% and 80% levels as thresholds for the 100% level. By calculating the difference between the measured times, the slew rate value can be calculated, and the difference from the slew rate value Tr1 in a normal state can be obtained. Therefore, similarly to the calibration of the output timing of the driver 76, the contact failure between the probe 44 and the test board 10 can be detected by the comparator 80.
[0075]
As yet another embodiment, similarly to FIG. 26, instead of measuring a slew rate value, a range of a desired threshold is set from a level of a normal signal within a rising or falling period of a test signal. Then, the contact failure may be determined based on whether or not the measured signal level falls within a desired threshold range.
[0076]
As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such modifications or improvements are also included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a sectional view of a conventional semiconductor test apparatus.
2 is a top view and a front view of the semiconductor device 20. FIG.
FIG. 3 is a cross-sectional view showing the socket 50 and a socket board 60 on which the socket 50 is mounted.
FIG. 4 is a top view of the socket board 60.
5 shows a state where a probe 44 is applied to the socket board 60. FIG.
FIG. 6 shows another conventional method for calibrating a semiconductor test apparatus.
FIG. 7 shows still another embodiment of the conventional semiconductor test apparatus.
FIG. 8 shows a flowchart of a conventional calibration method.
FIG. 9 shows a waveform of a test signal measured in a timing measurement step (S310).
FIG. 10 shows a cross section of the entire semiconductor test apparatus in the present embodiment.
11A and 11B are a top view and a bottom view of a probe board 10A as an example of the test board 10 mounted on the holding unit 110.
FIG. 12 is a short board as another example of the test board 10;
FIG. 13 shows another embodiment of the semiconductor test apparatus.
FIG. 14 shows a method for easily obtaining a signal transmission time from the socket 50 to the comparator 80B.
FIG. 15 shows still another embodiment of the semiconductor test apparatus.
FIG. 16 shows a configuration of an earth short board 10C.
FIG. 17 shows still another configuration of the semiconductor test apparatus.
FIG. 18 shows a modified example of a method of calibrating the semiconductor test apparatus shown in FIG.
FIG. 19 is an enlarged view of the opening 120 of the frame 100, the holding unit 110, and the test board 10.
20 is a top view of the frame 100. FIG.
FIG. 21 is a top view of the socket board 60 to which the probe board 10D is attached.
FIG. 22 shows still another embodiment of the semiconductor test apparatus.
FIG. 23 shows another embodiment of the test board 10.
24 shows a connection diagram of the semiconductor test apparatus shown in FIG.
FIG. 25 is a flowchart showing a method of calibrating the semiconductor test device shown in FIG. 23 or 24.
FIG. 26 shows a waveform measured in a slew rate measurement step (S304).
FIG. 27 shows a schematic diagram and a connection diagram of a semiconductor test apparatus for showing still another embodiment of the calibration method.
FIG. 28 is a flowchart illustrating an embodiment of a calibration method of the semiconductor test apparatus illustrated in FIG. 27.
FIG. 29 shows an example of a reflected waveform measured in a reflected wave measuring step (S404).
FIG. 30 shows another embodiment of the calibration method for the comparator 80.
[Explanation of symbols]
10 Test board
10A probe board
10B short board
10C Earth short board
10D probe board
12 1st terminal
14 2nd terminal
20 Semiconductor devices
30 contact terminals
32 signal wiring pattern
36 earth pattern
40 signal terminals
42 Ground terminal
44 probe
46 short pattern
50 sockets
52 pins
54 pins
56 Through Hole
58 Socket Guide
59 Through hole
60 Socket Board
62 coaxial cable
64 coaxial cable
66 Performance Board
70 Test Head
76 Driver
77 Driver
78 delay circuit
79 Delay circuit
80 Comparator
90 Comparator
82 delay circuit
83 delay circuit
100 frames
102 spring
104 cylindrical member
106 Fastener
108 Positioning rod
110 Holding unit
120 opening
132 signal wiring pattern
136 Ground pattern
140 handle
150 oscilloscope
160 Waveform shaper
162 gate
180 Programmable Load
200 oscilloscope
204 Pogo Pin
206 pin electronics
208 Test equipment main body
210 Body delay circuit
220 Reference pulse signal
221 Reference signal end
222 Reference Driver
S302 Probing step
S304 Slew rate measurement step
S306 Slew rate determination step
S310 Timing measurement step
S312 Test signal generation step
S314 Rising waveform measurement step
S316 Falling waveform measurement step
S322 Loop count determination step
S424 Re-contact step
S326 Failure notification step
S404 Reflection waveform measurement step
S406 Reflection waveform determination step
S ₀ , S ₁ , S ₂ , S ₄ , S ₆ Waveform
S ₁₀ , S ₁₂ Transition waveform
t ₀ Reference timing position
t ₁ , T ₂ timing
e ₁ , E ₂ Timing deviation
D ₁₀ Distribution
V2 Half level
V4 level
T1 Round trip time

Claims (15)

A semiconductor having a first terminal for mounting a semiconductor device thereon and supplying a test signal used for testing the semiconductor device to the semiconductor device, and a driver for outputting the test signal to the first terminal A calibration method for calibrating the output timing of the test signal in a test apparatus,
A mounting step of mounting a test board having a pin arrangement similar to the pin arrangement of the semiconductor device to the socket,
A generating step of generating the test signal by the driver;
A detecting step of detecting the test signal that has reached the test board,
The semiconductor test apparatus further includes a comparator that receives the test signal from the test board,
The detection step is a reflected wave measurement step of measuring the test signal output from the driver and reflected by the test board by the comparator,
A transition of the waveform of the test signal measured by the comparator is compared with the transition of the waveform in a normal case, and a reflected waveform determination step of determining whether or not the waveform is within a desired range.
And a notification step of notifying a connection failure of a transmission line from an output end of the driver to the test board when a transition of the waveform measured by the comparator is out of the desired range. Characteristic calibration method. The calibration method according to claim 1, wherein a pin of the test board that contacts the first terminal has the same input impedance as a pin of the semiconductor device that contacts the first terminal. In the test board, a contact terminal that contacts the first terminal is connected to a ground pattern,
The calibration method according to claim 1, wherein the detecting step includes a step of measuring the test signal output from the driver and reflected by the test board. A semiconductor having a first terminal for mounting a semiconductor device thereon and supplying a test signal used for testing the semiconductor device to the semiconductor device, and a driver for outputting the test signal to the first terminal A calibration method for calibrating the output timing of the test signal in a test apparatus,
A mounting step of mounting a test board having a pin arrangement similar to the pin arrangement of the semiconductor device to the socket,
A generating step of generating the test signal by the driver;
An inspection step for checking a contact failure between the electrical characteristic test probe and the test board,
The inspection step includes:
A probing step of bringing the electrical property test probe into contact with the test board;
A waveform measuring step of measuring the test signal detected by the electrical property test probe with an external measuring instrument,
A waveform determination step in which a slew rate value based on the waveform of the test signal measured by the external measuring device is compared with a slew rate value based on a waveform in a normal case to determine whether the slew rate value is within a desired range. ,
When the slew rate value based on the waveform measured by the external measuring device is out of the desired range, a notification step of notifying a contact failure between the electrical characteristic test probe and the test board. A calibration method comprising: A driver that outputs a test signal used for testing a semiconductor device, a comparator that receives an electrical signal from the semiconductor device, and a socket that can be mounted on the semiconductor device and can provide the test signal to the semiconductor device. A calibration method for calibrating the processing timing of a semiconductor test apparatus having
A connection step of connecting an electrical characteristic test probe and a test board to provide a reference signal to an internal measuring instrument for measuring the waveform of the test signal,
A waveform measuring step of measuring the reference signal supplied from the electrical property test probe via the test board and input to the comparator in the measuring device,
A waveform determination step in which a slew rate value based on the waveform of the reference signal measured by the measuring device is compared with a slew rate value based on a waveform in a normal case to determine whether the value is within a desired range,
A notification step of notifying that the connection between the electrical characteristic test probe and the test board is defective when the waveform measured by the measuring device is out of the desired range. Characteristic calibration method. The calibration method according to claim 5 , wherein the waveform measuring step measures at least one of a rising edge and a falling edge of the reference signal . The notifying step includes:
When the waveform is out of the desired range, the connection step, the waveform measurement step, and a reconnection step of repeating the waveform determination step,
In the reconnecting step, if the waveform is out of the desired range even after repeating the connecting step, the waveform measuring step, and the waveform determining step a predetermined number of times, the connection made to the measuring instrument is defective. 6. The calibration method according to claim 5, further comprising: a failure notification step of notifying that the above is true. A driver that outputs a test signal used for testing a semiconductor device, a comparator that receives an electrical signal from the semiconductor device, and a socket that can be mounted on the semiconductor device and can provide the test signal to the semiconductor device. A calibration method for calibrating the processing timing of a semiconductor test apparatus having
A connection step of connecting to the driver via the socket to provide the test signal to a measuring instrument inside the semiconductor test apparatus that measures the waveform of the test signal;
A waveform measuring step of inputting the test signal output from the driver and reflected by the socket from the comparator and measuring the test signal in the measuring instrument;
A transition of the waveform of the test signal measured by the measuring instrument is compared with the transition of the waveform in a normal case, and a waveform determination step of determining whether the waveform is within a desired range.
And a notification step of notifying that the connection of the transmission line from the driver to the socket is defective when the waveform measured by the measuring device is out of the desired range. Calibration method to be used. The reflected waveform determination step determines whether the measured waveform is within the desired range based on a difference between a transition of the waveform in the normal case and a transition of the measured waveform. 2. The calibration method according to 1. 9. The waveform determining step determines whether the measured waveform is within the desired range based on a difference between a transition of the waveform in the normal case and a transition of the measured waveform. Calibration method described in 1. A semiconductor having a first terminal for mounting a semiconductor device thereon and supplying a test signal used for testing the semiconductor device to the semiconductor device, and a driver for outputting the test signal to the first terminal A calibration method for calibrating the output timing of the test signal in a test apparatus,
A mounting step of mounting a test board having a pin arrangement similar to the pin arrangement of the semiconductor device to the socket,
A generating step of generating the test signal by the driver;
An inspection step for checking a contact failure between the electrical characteristic test probe and the test board,
The inspection step includes:
A probing step of bringing the electrical property test probe into contact with the test board;
A waveform measuring step of measuring the test signal detected by the electrical property test probe with an external measuring instrument,
The level of the test signal measured by the external measuring instrument based on the level of the normal signal at a specific time within the rising or falling period of the test signal measured by the external measuring instrument, A waveform determination step of determining whether the waveform is within a desired range;
When the level measured by the external measuring device is out of the desired range, a notification step of notifying a contact failure between the electrical characteristic test probe and the test board is provided. Calibration method. A driver that outputs a test signal used for testing a semiconductor device, a comparator that receives an electrical signal from the semiconductor device, and a socket that can be mounted on the semiconductor device and can provide the test signal to the semiconductor device. A calibration method for calibrating the processing timing of a semiconductor test apparatus having
A connection step of connecting an electrical characteristic test probe and a test board to provide a reference signal to an internal measuring instrument for measuring the waveform of the test signal,
A waveform measuring step of measuring, in the measuring device, a reference signal supplied from the electrical characteristic test probe and input to the comparator via the test board,
The level of the test signal measured by the measuring device is within a desired range based on the level of the normal signal at a specific time within the rising or falling period of the reference signal measured by the measuring device . A waveform determining step of determining whether
A notification step of notifying that the connection between the electrical characteristic test probe and the test board is defective when the waveform measured by the measuring device is out of the desired range. Characteristic calibration method. The notifying step includes:
When the slew rate value is out of the desired range, the probing step, the waveform measurement step, and a reconnection step of repeating the waveform determination step,
In the reconnecting step, if the slew rate value is out of the desired range even after repeating the probing step, the waveform measuring step, and the waveform determining step a predetermined number of times, the electrical characteristic test probe 5. The calibration method according to claim 4, further comprising a failure notification step of notifying that the contact between the test board and the test board is defective. 2. The calibration method according to claim 1, wherein the reflected wave measurement step measures at least one of a rising waveform and a falling waveform of the test signal. 3. The calibration method according to claim 4, wherein the waveform measuring step measures at least one of a rising edge and a falling edge of the test signal.

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