JP3560763B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device, and mainly forms a P-channel MOSFET and an N-channel MOSFET in a peripheral circuit section provided in a memory cell array section of a dynamic RAM (random access memory) having a large storage capacity. The present invention relates to a technology effective for use in a mask layer forming technology for ion implantation for performing ion implantation.
[0002]
[Prior art]
To operate only the necessary blocks in which the selected memory cells are provided, to reduce the memory area to be operated as much as possible for low power consumption, and to speed up the operation of selecting the sub-word line to which the memory cells are connected. There has been proposed a divided word line system in which a plurality of sub-word lines for connecting memory cells to a main word line are provided. An example of such a divided word line system is disclosed in Japanese Patent Laid-Open No. 2-158959. In the above publication, the main word line is referred to as a pre-word line, and the sub-word lines are referred to as word lines.
[0003]
[Problems to be solved by the invention]
In the above-mentioned divided word line system, a complementary bit line arranged so as to intersect with a word line is also divided through a sense amplifier. The memory cells are arranged in a matrix of the divided word lines and the divided bit lines, and the sense amplifiers and word drivers for selecting the divided word lines are arranged in the periphery thereof. For example, in a dynamic RAM such as 64 Mbits, the whole is divided into four memory blocks, and each memory block forms as many as 8 × 16 memory cell arrays.
[0004]
FIG. 6 shows a configuration diagram of a 64-Mbit memory cell array and its peripheral circuits developed prior to the present invention. FIG. 1 shows four memory cell arrays (memory mats) MMAT and two sense amplifiers SA and sub-word drivers SWD provided in the periphery thereof as representatives. The sense amplifier SA and the sub-word driver in the peripheral circuit section are constituted by a CMOS circuit composed of an N-channel MOSFET and a P-channel MOSFET. As shown in an enlarged view in FIG. In consideration of a mask shift of a mask layer used for ion implantation for forming a MOSFET, a margin such as 2L 'is provided in consideration of a mask shift from a center line indicated by a dotted line in FIG. And an N-channel MOSFET. For example, when a P-channel MOSFET is formed, a mask layer is formed on the N-channel MOSFET side as indicated by hatching in the enlarged view of FIG.
[0005]
In the present inventors, the margin itself is small because of the mask layer for separately forming the P-channel MOSFET and the N-channel MOSFET. However, in the dynamic RAM having a large storage capacity as described above, a memory cell array is used. Since a large number of parts are stacked vertically and horizontally as described above, the small mask alignment margin increases in proportion to the number of the divided memory cell arrays, and becomes noticeable. .
[0006]
An object of the present invention is to provide a method of manufacturing a semiconductor memory device which realizes a reduction in chip size while achieving a large storage capacity. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in the method of manufacturing a semiconductor memory device, a space is provided at the boundary between the peripheral circuit portion and the memory cell array portion, and the first conductivity type MOSFET and the second conductivity type MOSFET constituting the peripheral circuit portion are used for ion implantation. The mask layer formed in the first conductivity type MOSFET portion used for ion implantation for forming the second conductivity type MOSFET is set in accordance with the minimum processing size of the element ignoring the dimensional deviation for forming the mask layer. It is formed so as to be separated at the space between the peripheral circuit section and the memory cell array section composed of the first conductivity type MOSFET.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a schematic layout diagram of one embodiment of a dynamic RAM according to the present invention. In the figure, a portion related to the present invention is shown in each of the circuit blocks constituting the dynamic RAM so as to be understood, and it is formed by a known semiconductor integrated circuit manufacturing technique such as single crystal silicon. It is formed on one semiconductor substrate.
[0009]
In this embodiment, although not particularly limited, the memory array is divided into four as a whole. Two memory arrays are divided into two on the left and right sides with respect to the longitudinal direction of the semiconductor chip. An input / output interface circuit including a row of address input circuits, a data input / output circuit, and a bonding pad, a power generation circuit, etc. Can be Column decoder regions 13 are arranged at portions of both sides of the central portion 14 in contact with the memory array.
[0010]
As described above, in each of the four memory arrays divided into two on the left and right sides and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder area 11 is located at the upper and lower central parts in the longitudinal direction. Provided. Main word driver regions are formed above and below the main row decoder, and drive the main word lines of the memory array divided into upper and lower parts. Hereinafter, as shown in the enlarged view of the memory cell array, the sense amplifier region 16 and the sub-word driver region 17 are formed with the memory cell array 15 interposed therebetween. An intersection between the sense amplifier region and the sub-word driver region is an intersection region 18. The sense amplifier provided in the sense amplifier region is configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Are selectively connected to the complementary bit lines of the memory cell array.
[0011]
Although not particularly limited, the dynamic RAM according to this embodiment has a storage capacity of about 64 M (mega) bits. As described above, four memory arrays are divided on the left and right sides with respect to the longitudinal direction of the semiconductor chip, and although omitted in the figure at the center, the address input circuit, data input / output circuit, etc. Are provided.
[0012]
As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. In the two memory arrays arranged in pairs as described above, the main word driver 11 is arranged at the center. The main word driver 11 is provided corresponding to the two memory arrays which are divided up and down around the main word driver 11. The main word driver 11 generates a selection signal of a main word line extended so as to penetrate the one memory array.
[0013]
Although not shown, one memory cell array 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 16 memory cell arrays 15 are provided in the word bit line direction, so that about 4K sub word lines are provided as a whole, and 8 sub word lines are provided in the word line direction. A total of about 2K is provided. Since eight such memory arrays are provided in total, a large storage capacity such as 8 × 2K × 4K = 64 Mbits is provided as a whole.
[0014]
The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line and forms a sub-word line selection signal extending in parallel with the main word line. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. As described above, in order to select one sub-word line from sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver forms a selection signal for selecting one of the four sub-word selection lines extending in the arrangement direction of the sub-word drivers.
[0015]
Thus, focusing on the one memory array, one sub-word driver corresponding to one memory cell array including a memory cell to be selected among the eight memory cell arrays allocated to one main word line. As a result of the selection line being selected, one sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to one main word line. As described above, since 2K (2048) memory cells are provided in the main word line direction, 2048/8 = 256 memory cells are connected to one sub-word line. Although not particularly limited, in a refresh operation (for example, a self-refresh mode), eight sub-word lines corresponding to one main word line are set to a selected state.
[0016]
As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, when as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level read out cannot be obtained due to a capacitance ratio with a minute information storage capacitor. Are also divided into 16 parts in the complementary bit line direction. That is, the complementary bit line is divided into 16 parts by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifiers 16 are configured by a shared sense system, and except for the sense amplifiers 16 arranged at both ends of the memory array, complementary bit lines are provided on the left and right around the sense amplifier 16. Are selectively connected to the complementary bit lines.
[0017]
FIG. 2 is a main block diagram for explaining the relationship between a main word line and a sub word line of the memory array. In the figure, two main word lines MWL0 and MWL1 are shown as representatives for explaining the sub-word line selection operation. These main word lines MWL0 are selected by a main word driver MWD0. The other main word line MWL1 is similarly selected by the same main word driver.
[0018]
The one main word line MWL0 is provided with eight sets of sub-word lines in the extending direction thereof. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. As the sub-word lines, a total of eight sub-word lines of even numbers 0 to 6 and odd numbers 1 to 7 are alternately arranged in one memory cell array. Except for even numbers 0 to 6 adjacent to the main word driver and odd numbers 1 to 7 arranged at the far end of the main word line (opposite to the word driver), the sub word drivers arranged between the memory cell arrays are , And a selection signal for the sub-word lines of the left and right memory cell arrays centered at.
[0019]
As a result, the memory cell array is divided into eight blocks as described above, but since the sub-word lines corresponding to the two memory cell arrays are simultaneously selected by the sub-word driver SWD substantially as described above, substantially The memory array is divided into four blocks. In the configuration in which the sub-word lines SWL are divided into even numbers 0 to 6 and even numbers 1 to 7 as described above, and the sub-word drivers SWD are arranged on both sides of the memory block, respectively, the sub-word lines SWD are densely arranged in accordance with the arrangement of the memory cells. The substantial pitch of the SWL can be relaxed twice in the sub-word driver SWD, and the sub-word driver SWD and the sub-word line SWL can be efficiently laid out on the semiconductor chip.
[0020]
In this embodiment, the sub-word driver SWD supplies a selection signal from the main word line MWL to four sub-word lines 0 to 6 (1 to 7) in common. A sub-word selection line FXB for selecting one sub-word line from the four sub-word lines is provided. The sub-word selection lines are composed of eight lines FXB0 to FXB7, of which the even-numbered FXB0 to FXB6 are supplied to the sub-word drivers 0 to 6 of the even-numbered columns, and the odd-numbered FXB1 to FXB7 are provided to the sub-word drivers 1 to 7 of the odd-numbered columns. Supplied to
[0021]
The sub-word select lines FXB0 to FXB7 are formed by a second metal wiring layer M2 in the periphery of the array, and extend in parallel with the main word lines MWL0 to MWLn also formed by the second metal wiring layer M2. And a second sub-word selection line extending in a direction orthogonal thereto. Although not particularly limited, the second sub-word selection line is formed by a third-layer metal wiring layer M3 to cross the main word line MWL.
[0022]
The sub-word driver SWD includes a P-channel MOSFET Q1 and an N-channel MOSFET Q2 having an input terminal connected to the main word line MWL and an output terminal connected to the sub-word line SWL, as one of them is illustratively shown. And a switch MOSFET Q3 provided between the sub-word line SWL and the ground potential of the circuit and receiving the sub-word selection signal FXB. A second CMOS inverter circuit N1 for forming an inverted signal of the sub-word selection signal FXB is provided, and its output signal is supplied to a source terminal of a P-channel MOSFET Q1, which is an operating voltage terminal of the first CMOS inverter circuit. I do. Although not particularly limited, the second CMOS inverter circuit N1 is formed in the intersection area of FIG. 1, and is commonly used corresponding to the plurality of sub-word drivers SWD.
[0023]
In the above configuration, when the main word line MWL is at a high level such as the high voltage VPP corresponding to the selected level of the word line, the N-channel MOSFET Q2 of the first CMOS inverter circuit is turned on, and the sub-word line SWL is turned on. A low level such as the ground potential of the circuit. At this time, even if the sub-word selection signal FXB becomes a selection level such as a low level such as the VPP and the output signal of the second CMOS inverter circuit N1 is set to a selection level corresponding to the VPP, the main word line MWL is Since the P-channel MOSFET Q1 is in the OFF state due to the non-selection level, the sub-word line SWL is set to the non-selected state due to the ON state of the N-channel MOSFET Q2.
[0024]
When the main word line MWL is at a low level such as the ground potential of a circuit corresponding to the word line non-selection level, the N-channel MOSFET Q2 of the first CMOS inverter circuit is turned off and the P-channel MOSFET Q2 is turned on. become. At this time, if the sub-word selection signal FXB is at a selection level such as a low level such as VPP, the output signal of the second CMOS inverter circuit N1 is set to a selection level corresponding to VPP, and the sub-word line SWL is set to VPP. Selection level. If the sub-word selection signal FXB is a non-selection level such as a high level, the output signal of the second CMOS inverter circuit N2 goes to a low level, and at the same time, the N-channel MOSFET Q3 turns on to bring the sub-word line SWL to a low level. To a non-selection level.
[0025]
FIG. 3 is a main part circuit diagram of one embodiment of the sense amplifier section of the dynamic RAM according to the present invention. FIG. 2 exemplarily shows a sense amplifier SA1 arranged between memory mats (same as the memory block) MAT0 and MAT1 and circuits related thereto. The memory mat MAT1 is shown as a black box, and the sense amplifier SA0 provided at the end is also shown as a black box.
[0026]
Four dynamic memory cells are exemplarily shown as representatives corresponding to the sub-word lines SWL provided in the memory mat MMAT0. The dynamic memory cell includes an address selection MOSFET Qm and an information storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub-word line SWL, the drain of this MOSFET Qm is connected to the bit line, and the source is connected to the information storage capacitor Cs. The other electrode of the information storage capacitor Cs is shared and receives a plate voltage. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm. For example, in the case of operating with a power supply voltage VCC of a sense amplifier to be described later, the high level given to the bit line is set to a level corresponding to the power supply voltage VCC. VPP is set to VCC + Vth.
[0027]
The pair of complementary bit lines are arranged in parallel as shown in the figure, and are appropriately crossed as needed to balance the bit line capacitance. Such complementary bit lines are connected to input / output nodes of a unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2. The unit circuit of the sense amplifier includes N-channel MOSFETs Q5 and Q6 and P-channel MOSFETs Q7 and Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. An N-channel MOSFET and a P-channel MOSFET are provided on the common source lines CSN and CSP, respectively. The power switch MOSFET is turned on by an activation signal of the sense amplifier, and the operation of the sense amplifier is performed. , For example, VCC and VSS.
[0028]
An input / output node of the unit circuit of the sense amplifier is provided with a MOSFET Q11 for short-circuiting a complementary bit line and a precharge circuit including switch MOSFETs Q9 and Q10 for supplying a half precharge voltage HVC to the complementary bit line. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB.
[0029]
The MOSFETs Q12 and Q13 form a column switch that is switch-controlled by the column selection signal YS. In this embodiment, four pairs of bit lines can be selected by one column selection signal YS. That is, a similar column switch is provided in the sense amplifier SA0 indicated by a black box. As described above, the two sense amplifiers SA0 and SA1 sandwich the memory mat MMAT0 to divide the complementary bit lines into even-numbered bit lines and odd-numbered bit lines, thereby associating the sense amplifiers SA0 and SA1 with each other. is there. Therefore, the column selection signal YS has a total of four bits corresponding to the two pairs of bit lines exemplarily shown on the sense amplifier SA1 side and the remaining two pairs of bit lines (not shown) provided on the sense amplifier SA0 side. A pair of complementary bit lines can be selected. These two pairs of complementary bit line pairs are connected to two pairs of common input / output lines I / O via the column switches.
[0030]
The sense amplifier SA1 is connected to similar odd-numbered complementary bit lines of the memory mat MMAT1 via shared switch MOSFETs Q3 and Q4. The even-numbered complementary bit lines of the memory mat MMAT1 are connected to a sense amplifier SA2 (not shown) arranged on the right side of the memory mat MMAT1 via shared switch MOSFETs corresponding to the shared switch MOSFETs Q1 and Q2. With such a repetitive pattern, the memory array is connected to a sense amplifier provided between memory mats (the memory blocks) obtained by dividing the memory array. For example, when the sub-word line SWL of the memory mat MMAT0 is selected, the right shared switch MOSFET of the sense amplifier SA0 and the left shared switch MOSFET of the sense amplifier SA1 are turned on. However, in the sense amplifier SA0 at the end, only the right shared switch MOSFET is provided. The signal SHRL is a left shared selection signal and a SHRR right shared selection signal.
[0031]
FIG. 4 is a configuration diagram for explaining an embodiment of a mask layer used for ion implantation for explaining a method of manufacturing the divided memory cell array portion and its peripheral circuit. In this embodiment, a space is provided between the memory cell array (memory mat) MMAT and the sub-word driver SWD and the sense amplifier SA which are peripheral circuits.
[0032]
When forming the P-channel MOSFET in the peripheral circuit section, a P-type impurity is ion-implanted. In order to prevent the P-type impurity from being introduced into the N-channel MOSFET, an N-channel MOSFET is formed. A mask layer as indicated by oblique lines is formed on the MOSFET side. Conversely, when an N-type impurity is ion-implanted in order to form an N-channel MOSFET, a max layer is formed on the P-channel MOSFET side for preventing the ion implantation. In this embodiment, the space L between the P-channel MOSFET and the N-channel MOSFET is provided without providing a margin in consideration of the displacement of the mask layer for separately producing the P-channel MOSFET and the N-channel MOSFET. Is set according to the minimum processing size.
[0033]
Therefore, a mask layer for forming the P-channel MOSFET may be shifted toward the gate electrode FG of the P-channel MOSFET due to a positional shift. However, on the N-channel MOSFET side, a space is provided between the memory cell array portion having a larger area and the peripheral circuit portion, and the mask layer is separated here. Therefore, when the P-type impurity is ion-implanted, the mask layer has a potential due to the ionized P-type impurity, but has a large area with the mask layer of the peripheral circuit portion where the gate portion FG is exposed. Since the mask on the memory cell array side that accumulates a large amount of electric charge is separated, gate insulation breakdown occurs in a MOSFET in which P-type impurities are implanted into the gate FG due to a shift of the mask layer in the peripheral circuit portion. This does not cause a problem.
[0034]
When ion-implanting an N-type impurity to form an N-channel MOSFET, what is masked is a small-area mask layer formed on the P-channel MOSFET in the peripheral circuit section. There is no fear that the gate insulating film of the P-channel MOSFET masked by the ions trapped in the layer is broken down.
[0035]
According to the calculation by the inventor of the present application, by applying the present invention to a dynamic RAM such as the 64 Mbit described above, even if the space provided between the memory cell array section and the peripheral circuit section is subtracted, X and The chip size can be reduced by about 90 μm in the Y direction.
[0036]
FIG. 5 is a schematic sectional view of the element structure of a dynamic RAM to which the present invention is applied. Although not particularly limited, a P-type well region PW is formed at the outermost periphery of the semiconductor chip, and a P-type region for ohmic contact formed by the same diffusion layer as the source and drain of the P-channel MOSFET is formed therein. The ground line is provided in such a P-type region, and a ground potential PVS1 of the circuit is applied from a bonding pad or the like. The address selection MOSFET constituting the memory cell MC is surrounded by an N-type well region NW which is also used as the space, and a deep N-type well region DW is formed below the N-type well region NW. A negative substrate back bias voltage VBB is applied electrically separated from the P-Sub. The boosted voltage VPP corresponding to the selected level of the word line is applied to the N-type wells NW and DW for isolation, although not particularly limited. When only the memory cells MC are formed in the separated P-type well region, if the highest voltage supplied to the source and drain of the address selection MOSFET is VCL, the applied VCL or power supply voltage VCC is applied.
[0037]
The P-channel MOSFET (P-SA) constituting the sense amplifier SA is formed in the N-type well region NW. When the operating voltage of the sense amplifier is set to the voltage VCL lower than the power supply voltage, the N-type well region NW may be configured to supply the VCL instead of the power supply voltage VCC. An N-channel MOSFET (N-SA) constituting the sense amplifier is formed in the P-type well region PW. The ground potential VSS of the circuit is applied to the P-type well region PW from the substrate P-Sub. Similarly, each P-channel MOSFET constituting the peripheral circuit Peri and the peripheral circuit IO is formed in the N-type well region NW, and the power supply voltage VCC is applied to the N-type well region. Each N-channel MOSFET constituting the peripheral circuit Peri and the peripheral circuit IO is formed in the P-type well region PW, and the ground potential VSS of the circuit is applied to the N-type well region.
[0038]
In the figure, the N-channel MOSFET and the N-channel MOSFET of the peripheral circuit Peri are formed according to a minimum processing size in accordance with a regularly arranged memory cell array. On the other hand, unlike the input / output circuit IO, the arrangement of the memory cell array is not restricted and the portion where the arrangement is free has a relatively large area allowance. The element dimensions and intervals are set with allowance in consideration.
[0039]
The operational effects obtained from the above embodiment are as follows. That is,
(1) In a method of manufacturing a semiconductor memory device, a space portion is provided at a boundary between a peripheral circuit portion and a memory cell array portion, and a first conductivity type MOSFET and a second conductivity type MOSFET constituting the peripheral circuit portion are used for ion implantation. A mask layer formed in a first conductivity type MOSFET portion used for ion implantation for forming a second conductivity type MOSFET, while being set according to a minimum processing size of a device ignoring a dimensional deviation forming a mask layer to be formed. Are formed separately in the space between the peripheral circuit section and the memory cell array section composed of the first conductivity type MOSFET, so that the gate insulating film of the first conductivity type MOSFET can be prevented from being damaged by electrostatic discharge, The effect that integration can be achieved is obtained.
[0040]
(2) By applying the present invention to a dynamic RAM of a word line division system and a bit line division system, the memory cell array is divided into a large number of parts, so that the effect of reduction in the peripheral circuit portion can be enhanced. The effect is obtained.
[0041]
Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, the configuration of a memory array or the arrangement of a plurality of memory arrays mounted on a semiconductor chip can employ various embodiments according to the storage capacity and the like. The present invention provides various types of semiconductor memory devices having a main word line and a sub word line, a memory cell array portion formed of MOSFETs of the same conductivity type, and a dynamic RAM or a static RAM of a divided word line type. Can be widely used in manufacturing methods.
[0042]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application. That is, in the method of manufacturing a semiconductor memory device, a space is provided at the boundary between the peripheral circuit portion and the memory cell array portion, and the first conductivity type MOSFET and the second conductivity type MOSFET constituting the peripheral circuit portion are used for ion implantation. The mask layer formed in the first conductivity type MOSFET portion used for ion implantation for forming the second conductivity type MOSFET is set in accordance with the minimum processing size of the element ignoring the dimensional deviation for forming the mask layer. By forming the peripheral circuit portion and the memory cell array portion composed of the first conductivity type MOSFETs separately in a space portion, the gate insulating film of the first conductivity type MOSFET is prevented from electrostatic breakdown, and high integration is achieved. Can be realized.
[Brief description of the drawings]
FIG. 1 is a layout diagram showing one embodiment of a dynamic RAM according to the present invention.
FIG. 2 is a main block diagram for explaining a relationship between a main word line and a sense amplifier of the memory array of FIG. 1;
FIG. 3 is a main part circuit diagram showing one embodiment of a sense amplifier section of the dynamic RAM according to the present invention.
FIG. 4 is a configuration diagram for explaining an embodiment of a mask layer used for ion implantation for explaining a method of manufacturing the divided memory cell array portion and its peripheral circuit.
FIG. 5 is a sectional view of an element structure for explaining a dynamic RAM to which the present invention is applied.
FIG. 6 is a configuration diagram for explaining a mask layer used for ion implantation for explaining a method of manufacturing a memory cell array portion and peripheral circuits developed prior to the present invention.
[Explanation of symbols]
Reference Signs List 10: memory chip, 11: main row decoder area, 12: main word driver area, 13: column decoder area, 14: peripheral circuit, bonding pad area, 15: memory cell array, 16: sense amplifier area, 17: sub-word driver Area, 18 ... intersection area,
Q1 to Q13: MOSFET, CSP, CSN: common source line, YS: column selection signal, HVC: half precharge voltage, SHRL, SHRR: shared selection line, I / O: input / output line,
MMAT: memory cell array (memory mat), SWD: sub-word driver, SA: sense amplifier.

Claims (3)

A memory cell array section in which a plurality of memory cells each composed of a first conductivity type MOSFET are regularly arranged; and a first conductivity type MOSFET and a second conductivity type MOSFET provided around the memory cell array section. In a method of manufacturing a semiconductor memory device including a configured peripheral circuit portion,
A space portion is provided at the boundary between the peripheral circuit portion and the memory cell array portion, and the first conductive type MOSFET and the second conductive type MOSFET forming the peripheral circuit portion are dimensionally shifted to form a mask layer used for ion implantation thereof. Is set in accordance with the minimum processing size of the element ignoring the above, and a mask layer formed in the first conductivity type MOSFET portion used for ion implantation for forming the second conductivity type MOSFET is formed in the peripheral circuit portion and the memory cell array portion. A method for manufacturing a semiconductor memory device, wherein the semiconductor memory device is formed while being separated at a space portion. 2. The method according to claim 1, wherein the memory cell is a dynamic memory cell including an N-channel address selection MOSFET and an information storage capacitor. The semiconductor memory device is
A main word line,
A sub-word line having a length divided in the direction in which the main word line extends and a plurality of the memory cells connected to a plurality of memory cells arranged in a complementary bit line direction crossing the main word line. When,
The complementary bit line is divided into a plurality by a sense amplifier,
The one memory cell array section is constituted by the divided complementary bit lines and the sub-word lines, and the memory cells are arranged on the semiconductor substrate in a grid pattern corresponding to the number of divisions. ,
3. The method according to claim 1, wherein said peripheral circuit section includes said sense amplifier and a sub-word driver for selecting said sub-word line.

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