JP3555501B2 - Noise filter circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a noise filter circuit for removing external noise.
[0002]
[Prior art]
FIG. 7 is a circuit diagram showing a configuration of a conventional noise filter circuit.
FIG. 7A is a circuit diagram of a configuration that includes a capacitor and a resistor that constitute a CR filter and a digital filter circuit to remove noise, and FIG. The presence noise filter is the same as in FIG.
However, the capacitor also smoothes the input signal.
FIGS. 7 (C) and 7 (D) are circuit diagrams showing a case where a CR filter is not provided and only a digital filter circuit is used to remove noise, and an input signal is monitored by a single clock. ing.
[0003]
[Problems to be solved by the invention]
In the conventional noise filter circuit as shown in FIGS. 7A and 7B, noise is removed by a CR filter and a digital filter. An accurate filter circuit cannot be obtained. In addition, there is a problem that an area for mounting a capacitor and a resistor on a printed wiring board must be secured in order to constitute a CR filter.
[0004]
Therefore, in a filter circuit that removes noise only with a digital filter as shown in FIGS. 7C and 7D, when the monitoring time of the input signal is increased to improve the noise removal performance, the input signal is turned on. (Or OFF), the time from when the internal signal is turned on (or turned off) becomes longer, which degrades the input response performance to the input signal. Conversely, the input signal monitoring time is increased to improve the input response performance. If the length is shortened, a noise signal having a width longer than the monitoring time is input as a normal input signal, so that there is a contradictory problem that the noise removal performance is reduced.
[0005]
Further, when the power of the external signal is an AC power supply, the output from the photocoupler when the switch is ON is in a sine wave state as shown in FIG. 8, and the ON state / OFF state of the switch is determined by the high level of the input signal. In the case of a circuit configuration that recognizes at the / low level, it is recognized that the switch is repeatedly ON / OFF based on the sine wave output from the photocoupler. Therefore, a capacitor for smoothing an input signal is required to prevent erroneous recognition, and there is a problem that an area for mounting the capacitor on a printed wiring board must be secured.
[0006]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a noise filter circuit which has good accuracy, input response performance, and noise removal performance and does not limit the power supply of an external signal.
[0007]
[Means for Solving the Problems]
The noise filter circuit of the present invention determines that the input signal is normal if the input signal does not change for a first monitoring time after the input signal changes, and outputs the input signal. If the input signal changes within the monitoring time, a first filter circuit that outputs the immediately preceding input state that has been determined and held as a noise signal, and an output of the first filter circuit as an input signal; If the input signal does not change for a second monitoring time after the input signal changes, the input signal is determined to be a normal input signal and the input signal is output. If the input signal changes within the second monitoring time, noise is output. A second filter circuit that outputs the immediately preceding input state that has been determined and held as a signal, and a filter clock generation circuit that supplies a clock for monitoring time to the first and second filter circuits. With .
[0008]
Further, different monitoring times can be set for the first and second filter circuits.
[0009]
Further, the second filter circuit can set a monitoring time for a high-level signal and a monitoring time for a low-level signal when the power of the external signal is an AC power supply.
[0010]
In supplying a clock for monitoring time from the filter clock generation circuit to the first and second filter circuits, the frequency of the clock to the first filter circuit is changed by the clock to the second filter circuit. To make it higher.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a noise filter circuit according to the present invention.
FIG. 1A shows a case where the power of the external signal is a DC power supply, and FIG. 1B shows a case where the power of the external signal is an AC power supply, but other configurations are the same.
In FIG. 1, reference numeral 1 denotes a normal input signal when the input signal does not change for a predetermined monitoring time after the input signal changes, and outputs the input signal, and the input signal changes within the predetermined monitoring time. In this case, the first filter circuit which determines that the signal is a noise signal and retains and outputs the immediately preceding input state, uses the output of the first filter circuit 1 as an input signal, and a predetermined monitoring time or more after the input signal changes If the input signal does not change, the input signal is determined to be normal and the input signal is output. If the input signal changes within a predetermined monitoring time, the signal is determined to be a noise signal and the input state immediately before is held and output. A second filter circuit 3, which sets a high-level monitoring time and a low-level monitoring time of the signal, is a filter for supplying a clock for monitoring time to the first filter circuit 1 and the second filter circuit 2. It is a use clock generation circuit.
[0012]
FIG. 2 is a circuit configuration diagram showing a circuit configuration of the first and second filter circuits. Here, FIG. 2A shows an internal configuration of the first filter circuit 1, and FIG. 2B shows an internal configuration of the first filter circuit 2.
[0013]
In FIG. 2A, the first filter circuit 1 includes a monitoring timer 11, a comparison circuit 12, and a holding circuit 13.
Here, the monitoring timer 2 is a timer operated by the clock signal CLK1, is a circuit that outputs a latch operation signal to the holding circuit 13 by counting up the timer, and the comparison circuit 12 is a signal level of the input signal and the output signal ( (A high level or a low level), and resets the monitoring timer 11 when the signal level is different, and resets the monitoring timer 11 when the signal level is the same. This is a circuit that latches and outputs an input signal in response to a latch operation signal from the CPU.
[0014]
In FIG. 2B, the second filter circuit 2 includes a monitoring timer 21, a comparison circuit 22, and a holding circuit 23.
Here, the monitoring timer 21 sets the input mode setting signal for setting whether the external power supply is a DC power supply or an AC power supply to a high level (the external signal power supply is a DC power supply; hereinafter, the input mode setting signal is a high level). In the case of the DC input mode, the counting operation is performed by the clock signal CLK2, and the input mode setting signal is at a low level (the external signal power supply is an AC power supply; hereinafter, when the input mode setting signal is at a low level, the AC input mode). When the output signal from the second filter circuit 5 is at a low level, the counting operation is performed with the clock signal CLK2, and when the output signal from the second filter circuit 2 is at the high level in the AC input mode. Is a timer that counts in response to the clock signal CLK3. Is a circuit to output.
The comparison circuit 22 compares the signal level (high level or low level) of the input signal and the output signal, and releases the reset to the monitoring timer 21 when the signal level is different, and to the monitoring timer 21 when the signal level is the same. This is a reset circuit. The holding circuit 23 is a circuit that latches and outputs an input signal in accordance with a latch operation signal from the monitoring timer 21.
[0015]
The filter clock generation circuit 3 is a circuit that divides the CLK signal and outputs CLK1, CLK2, and CLK3, and sets the division ratio of the clock output to each of CLK1, CLK2, and CLK3 by setting the division. Can be.
[0016]
FIG. 3 is an internal circuit diagram showing details of the first and second filter circuits.
Here, FIG. 3A shows the first filter circuit 1, and FIG. 3B shows the second filter circuit 2.
FIG. 4 is a timing chart showing operation timings of the first and second filter circuits.
Here, FIG. 4A shows the first filter circuit 1 and FIG. 4B shows the second filter circuit 2.
[0017]
Next, the operation of the noise filter circuit will be described with reference to the drawings.
First, the operation of the first filter circuit 1 will be described with reference to FIGS. 3A and 4A.
In the present embodiment, the monitoring timer 11 counts up when the rising edge of CLK1 is input three times.
First, an operation when a noise component is not superimposed on an input signal will be described.
[0018]
When the input signal changes from low level to high level, the levels of the input signal and the output signal are different, so that the comparison circuit 12 releases the reset to the monitoring timer 11 (outputs the high level).
The monitoring timer 11 starts counting at CLK1 when the reset is released, and outputs a latch operation signal to the holding circuit 13 when counting up (counting three times).
The holding circuit 13 receives the latch operation signal and latches the high level of the input signal, and the output signal changes from the low level to the high level.
When the output signal changes to the high level, the output signal becomes the same level as the input signal, so that the comparison circuit 12 resets the monitoring timer 11 (outputs a low level), and the monitoring timer 11 stops operating.
[0019]
Next, when the input signal changes from the high level to the low level, the levels of the input signal and the output signal are different, so that the comparator 12 releases the reset to the monitoring timer 11.
The monitoring timer 11 starts counting at CLK1 when the reset is released, and outputs a latch operation signal to the holding circuit 13 when counting up (counting three times).
The holding circuit 13 receives the latch operation signal, latches the low level of the input signal, and changes the output signal from the high level to the low level.
When the output signal changes to the low level, the output signal becomes the same level as the input signal, so that the comparison circuit 12 resets the monitoring timer 11, and the monitoring timer 11 stops operating.
[0020]
Next, an operation when a noise component is superimposed will be described.
In FIG. 4A, when a high-level noise at time t1 (t1 <two cycles of CLK2) is superimposed on the input signal, the comparison circuit 12 resets the monitoring timer 11 by changing the input signal to the high level. Cancel the output.
The monitoring timer 11 starts the counting operation in response to the release of the reset.
However, since the input signal changes to the low level at time t1, the comparator 12 outputs a reset to the monitoring timer, the monitoring timer 11 is reset, and the latching signal is not output from the monitoring timer 11 to the holding circuit 13. Keeps the low level, thereby removing the noise component.
[0021]
Also, in FIG. 4A, when low-level noise at time t2 (t2 <two cycles of CLK2) is superimposed on the input signal, the noise component can be removed by the same operation.
[0022]
As described above, in the first filter circuit 1, two cycles of CLK1 are the monitoring time of the input signal, and if the superimposition time of the noise component is within the monitoring time, the first filter circuit 1 can remove it.
[0023]
Subsequently, the operation of the second filter circuit 3 will be described with reference to FIGS. 3B and 4B. The monitoring timer 21 counts up when the rising edge of CLK2 or CLK3 is input three times.
First, an operation when a noise component is not superimposed on an input signal from the first filter circuit 1 will be described.
[0024]
The second filter circuit 3 has two modes, a DC input mode and an AC input mode.
In the DC input mode (when the input mode setting is at the high level), the input mode setting is always at the high level. Therefore, the value of CLK2 is input to the first-stage flip-flop of the monitoring timer 21, and the value shown in FIG. The operation is the same as that of the circuit in which CLK1 is changed to CLK2, and the operation is the same as that of the first filter circuit 1.
However, the monitoring time of the input signal is two cycles of CLK2.
[0025]
Next, the operation in the AC input mode (when the input mode setting is at the low level) will be described with reference to FIG.
When the input signal changes from the low level to the high level, the levels of the input signal and the output signal are different, so that the comparator 22 releases the reset to the monitoring timer 21 (outputs the high level).
When the reset is released, the monitoring timer 21 starts counting at CLK2 because the input mode setting is at the low level and the output signal is at the low level, and when counting up (counting three times), the latch operation signal is sent to the holding circuit 23. Output.
The holding circuit 23 receives the latch operation signal and latches the high level of the input signal, and the output signal changes from the low level to the high level.
When the output signal changes to the high level, it becomes the same level as the input signal, so that the monitoring circuit 21 is reset (outputs the low level) from the comparison circuit 22 and the monitoring timer 21 stops operating.
[0026]
Next, when the input signal changes from the high level to the low level, the level of the input signal and the level of the output signal are different, so that the comparator 22 releases the reset to the monitoring timer 21.
When the reset is released, the input mode setting is at the low level and the output signal is at the high level. Therefore, the monitoring timer 21 starts counting at CLK3, and when counting up (three times), holds the latch operation signal at the holding circuit 23. Output to
The holding circuit 23 receives the latch operation signal and latches the low level of the input signal, and the output signal changes from the high level to the low level.
When the output signal changes to a low level, the output signal becomes the same level as the input signal, so that the comparator 22 resets the monitoring timer 21 and stops the operation of the monitoring timer 21.
[0027]
Next, an operation when a noise component is superimposed will be described.
In FIG. 4B, when a high-level noise at time t3 (t3 <two cycles of CLK2) is superimposed on the input signal, the comparator 22 resets the monitoring timer 21 by changing the input signal to the high level. Cancel the output.
The monitoring timer 21 starts the counting operation in response to the release of the reset.
However, since the input signal changes to the low level at time t3, the comparison circuit 21 outputs a reset to the monitoring timer 21, the monitoring timer 21 is reset, and the latching signal is not output from the monitoring timer 21 to the holding circuit 23. The signal remains at the low level, and the noise component can be removed.
[0028]
Further, in FIG. 4B, when low-level noise at time t4 (t4 <two cycles of CLK3) is superimposed on the input signal, the comparison circuit 22 resets the monitoring timer 21 by changing the input signal to low level. Cancel the output.
The monitoring timer 21 starts the counting operation in response to the release of the reset.
However, since the input signal changes to the high level at time t4, the comparison circuit 22 outputs a reset to the monitoring timer, the monitoring timer 21 is reset, and the latching signal is not output from the monitoring timer 21 to the holding circuit 23. The signal remains at the high level, and the noise component can be removed.
[0029]
As described above, in the second filter circuit when the AC input mode is set, two cycles of CLK2 are the monitoring time of the high level of the input signal, and two cycles of CLK3 are the monitoring time of the low level of the input signal. If the time is within the monitoring time, it can be removed by the second filter circuit 3.
[0030]
Next, the operation of the entire noise filter circuit will be described.
FIG. 5 is a timing chart showing the operation timing of the entire noise filter circuit when the input mode setting is the DC input mode (the target of FIG. 1A).
Note that, as a precondition for the description, the relationship between the frequencies of CLK1 and CLK2 is CLK1> CLK2.
In FIG. 1A, when the switch is on, the input signal goes high, and when the switch is off, the input signal goes low.
[0031]
In the input signal shown in FIG. 5, noise t5 (t5 <two cycles of CLK1) and noise t6 (two cycles of CLK1 <t6 <two cycles of CLK2) are superimposed on the input signal when the switch is ON, and the input signal when the switch is OFF Noise t7 (t7 <two periods of CLK1) and noise t8 (two periods of CLK1 <t8 <two periods of CLK2) are superimposed on the input signal.
[0032]
When this input signal is input to the first filter circuit 1, the first filter circuit 1 monitors the input signal at CLK1, and has a width within the monitoring time (3 counts of CLK1 rising, 2 cycles of CLK1). Since the input signal is determined to be noise and removed, a signal (first filter output in FIG. 5) from which noise t5 and noise t7 have been removed is output.
[0033]
The first filter output becomes an input signal to the second filter circuit 2.
When the input signal is input to the second filter circuit 2, the second filter circuit 2 monitors the input signal at CLK2, and has a width within a monitoring time (3 counts of rising of CLK2, two cycles of CLK2). In order to remove the input signal of No. 6 as noise, the signal (No. 2 filter output in FIG. 5) from which the noise t6 and the noise t7 have been removed is output.
Therefore, the filter circuit output signal is a signal from which noises t5, t6, t7, and t8 have been removed.
[0034]
As described above, in the noise filter circuit of the present invention, the noise superimposed on the input signal is removed by the first filter circuit 1 and the second filter circuit 2.
Accordingly, by setting the input clocks CLK1 and CLK2 to the respective filter circuits to different frequencies and setting the frequency relationship to CLK1> CLK2, the first filter circuit 1 removes high-frequency (narrow signal width) noise. Since the second filter circuit 5 can remove low-frequency (wide signal) noise, the noise removal performance can be improved.
Further, since the high frequency noise is removed by the first filter circuit 1, the input signal to the second filter circuit 2 is a signal from which the high frequency noise has been removed, and the signal of the second filter circuit 2 is affected by the high frequency noise. A noise filter circuit that can suppress a decrease in input responsiveness, has high noise elimination performance, and has high input responsiveness.
For reference, the operation timing of a conventional noise filter is shown in FIG.
[0035]
FIG. 6 is a timing chart showing the operation timing of the entire noise filter circuit when the input mode is set to the AC input mode (target of FIG. 1B).
Note that, as a precondition for the description, the relationship between the frequencies of CLK1, CLK2, and CLK3 is CLK1>CLK2> CLK3.
When the switch is ON in FIG. 1B, the input signal has a sine waveform that repeats a high level and a low level as shown in the input signal to the filter circuit in FIG. 8 (without a smoothing capacitor), and the switch is OFF. In this case, the input signal goes low.
[0036]
In the input signal shown in FIG. 6, noise t9 (two cycles of CLK1 <t9 <two cycles of CLK2) and noise t10 (t10 <two cycles of CLK1) are superimposed on the input signal when the switch is ON, and when the switch is OFF. Noise t11 (two periods of t11 <CLK1) and noise t12 (two periods of CLK1 <t12 <two periods of CLK2) are superimposed on the input signal.
The low-level time of the input signal when the switch is ON is shorter than two cycles of CLK3.
[0037]
When this input signal is input to the first filter circuit 1, the first filter circuit 1 monitors the input signal at CLK1, and has a width within the monitoring time (3 counts of CLK1 rising, 2 cycles of CLK1). Since the input signal is determined to be noise and removed, a signal from which noises t10 and t11 have been removed (first filter output in FIG. 6) is output.
[0038]
The first filter output becomes an input signal to the second filter circuit 2.
When the input signal is input to the second filter circuit 2, the second filter circuit 2 monitors the high-level time of the input signal with CLK2, and monitors the monitoring time (3 rising edges of CLK2, 2 cycles of CLK2). An input signal having a width within the range of () is judged as noise and removed, and a low-level time of the input signal is monitored at CLK3. An input signal having a width within the monitoring time (3 rising edges of CLK3, two cycles of CLK3) is noise. Therefore, the noise t9 and the noise t11 are removed, and a low-level signal when the switch is turned on is also determined to be noise, and the removed signal (the second filter output in FIG. 6) is output.
Therefore, the filter circuit output signal is a signal from which noises t9, t10, t11, and t12 have been removed and a low-level signal when the switch is turned on has been removed.
[0039]
As described above, the noise filter circuit of the present invention removes the noise superimposed on the input signal by the first filter circuit 1 and the second filter circuit 2, and removes the sine waveform input to the second filter circuit 2. Are removed as noise.
Therefore, the input clocks CLK1, CLK2, and CLK3 to each filter circuit have different frequencies, and the frequency relationship is CLK1>CLK2> CLK3. By setting the monitoring time of CLK2 shorter than the high-level time of the input sine waveform and setting the monitoring time of CLK3 longer than the low-level time of the input sine waveform, the first time is obtained. The high frequency (narrow signal width) noise can be removed by the filter circuit 1, and the low frequency (wide signal width) noise can be removed by the second filter circuit 2, so that the noise removal performance can be improved. .
Further, since the high frequency noise is removed by the first filter circuit 1, the input signal to the second filter circuit 2 is a signal from which the high frequency noise has been removed, and the signal of the second filter circuit 2 is affected by the high frequency noise. A noise filter circuit that can suppress a decrease in input responsiveness, has high noise elimination performance, and has high input responsiveness.
Further, even if the ON state of the switch is input in a sine waveform, the second filter circuit 2 removes the low level signal of the sine waveform, so that when the switch is in the ON state, the noise filter outputs a high level to the output signal. It becomes a circuit.
For reference, the operation timing of a conventional noise filter is shown in FIG.
[0040]
As described above, according to the present embodiment, the first filter circuit removes high-frequency noise components, and the second noise filter removes low-frequency noise components. The removal performance can be improved.
[0041]
In addition, since the monitoring time for noise removal is determined by the clock frequency supplied to each filter circuit, a filter characteristic with good noise removal accuracy and suitable for an external environment can be obtained.
[0042]
Further, by switching the input mode in accordance with the power supply of the external input signal, a noise filter circuit that outputs a high level when the switch is on and a low level when the switch is off even if a signal indicating the ON state of the switch is input in a sine wave state. Can be configured.
[0043]
【The invention's effect】
According to the present invention, by providing a plurality of filter circuits, it is possible to obtain a noise filter circuit which has good noise removal accuracy and input response performance and does not limit the power supply of an external signal even without a CR filter.
[0044]
Further, since the high frequency noise is removed by the first filter circuit 1, the input signal to the second filter circuit 2 is a signal from which the high frequency noise has been removed, and the signal of the second filter circuit 2 is affected by the high frequency noise. A noise filter circuit that can suppress a decrease in input responsiveness, has high noise elimination performance, and has high input responsiveness.
[0045]
Further, the second filter circuit switches the monitoring time according to the power supply of the external signal.
[0046]
Further, when the power source of the external signal is an AC power source, the ON / OFF of a switch input in a sine waveform is not erroneously recognized, a smoothing capacitor for preventing erroneous recognition is not required, and the circuit configuration can be simplified.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a noise filter circuit of the present invention.
FIG. 2 is a circuit configuration diagram of first and second filter circuits.
FIG. 3 is a circuit diagram showing details of first and second filter circuits.
FIG. 4 is a timing chart showing operation timings of the first and second filter circuits.
FIG. 5 is a timing chart showing the operation timing of the entire noise filter circuit when the input mode setting is the DC input mode.
FIG. 6 is a timing chart showing the operation timing of the entire noise filter circuit when the input mode is set to the AC input mode.
FIG. 7 is a circuit configuration diagram showing a conventional noise filter circuit.
FIG. 8 is a waveform diagram of a noise filter circuit when an external signal power supply is an AC power supply.
[Explanation of symbols]
Reference Signs List 1 1st filter circuit, 2nd filter circuit, 3 filter clock generation circuit, 11 monitoring timer, 12 comparison circuit, 13 holding circuit, 21 monitoring timer, 22 comparison circuit, 23 holding circuit.

Claims (4)

If the input signal does not change for a first monitoring time after the input signal changes, the input signal is determined to be a normal input signal and the input signal is output, and the input signal is output within the first monitoring time. A first filter circuit that outputs an immediately preceding input state that has been determined and held as a noise signal when has changed;
The output of the first filter circuit is used as an input signal. If the input signal does not change for a second monitoring time after the input signal changes, it is determined that the input signal is normal and the input signal is output. A second filter circuit that outputs an immediately preceding input state that is determined as a noise signal when the input signal changes within the monitoring time of
A filter clock generation circuit for supplying a clock for monitoring time to the first and second filter circuits,
A noise filter circuit having: The noise filter circuit according to claim 1, wherein different monitoring times can be set for the first and second filter circuits. 2. The noise filter circuit according to claim 1, wherein the second filter circuit can set a monitoring time for a high-level signal and a monitoring time for a low-level signal, respectively, when the power of the external signal is an AC power supply. When supplying a clock for monitoring time from the filter clock generation circuit to the first and second filter circuits, the frequency of the clock to the first filter circuit is set higher than that of the clock to the second filter circuit. The noise filter circuit according to claim 1, wherein:

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