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JP3555062B2 - Structure of semiconductor device - Google Patents

Structure of semiconductor device Download PDF

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Publication number
JP3555062B2
JP3555062B2 JP19556097A JP19556097A JP3555062B2 JP 3555062 B2 JP3555062 B2 JP 3555062B2 JP 19556097 A JP19556097 A JP 19556097A JP 19556097 A JP19556097 A JP 19556097A JP 3555062 B2 JP3555062 B2 JP 3555062B2
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Japan
Prior art keywords
chip
electrode pad
protective film
barrier metal
metal wire
Prior art date
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Expired - Lifetime
Application number
JP19556097A
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Japanese (ja)
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JPH1140601A (en
Inventor
和孝 柴田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP19556097A priority Critical patent/JP3555062B2/en
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to US09/155,134 priority patent/US6133637A/en
Priority to PCT/JP1998/000281 priority patent/WO1998033217A1/en
Priority to KR10-1998-0707403A priority patent/KR100522223B1/en
Priority to EP98900725A priority patent/EP0890989A4/en
Priority to KR10-2004-7000090A priority patent/KR100467946B1/en
Publication of JPH1140601A publication Critical patent/JPH1140601A/en
Priority to US09/612,480 priority patent/US6458609B1/en
Application granted granted Critical
Publication of JP3555062B2 publication Critical patent/JP3555062B2/en
Anticipated expiration legal-status Critical
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Description

【０００１】
【発明の属する技術分野】
本発明は、ＩＣチップの表面に、各種の回路素子を形成すると共に、この回路素子に対する金属ワイヤ接続用電極パッドを形成し、且つ、前記ＩＣチップを、パッケージ部にて密封して成る半導体装置の構造に関するものである。
【０００２】
【従来の技術】
一般、この種の半導体装置では、前記ＩＣチップの表面に形成する金属ワイヤ接続用電極パッドをアルミニウム製にする一方、前記ＩＣチップの表面に、当該表面に形成されている各種の回路素子を覆う絶縁体による保護膜を、前記電極パッドの部分に開口部を設けて形成し、前記電極パッドのうち前記保護膜の開口部内の部分に対して、外部との接続用金属ワイヤにおけるボール部を接合するように構成しているが、この構造では、金等の金属ワイヤを電極パッドに対してボール接合するときの衝撃等にて、電極パッド及び保護膜を損傷するおそれが大きいのであった。
【０００３】
そこで、最近の半導体装置においては、例えば、特開平３−２２７５３９号公報等に記載されているように、前記金属ワイヤ接続用電極パッドの部分に、バリアメタルを、当該電極パッドのうち前記保護膜の開口部内の部分及び保護膜のうち開口部の周囲縁の部分を覆うように形成し、このバリアメタルの表面に対して、金属ワイヤにおけるボール部を接合するようにしている。
【０００４】
【発明が解決しようとする課題】
しかし、このように、金属ワイヤ接続用電極パッドの部分に、バリアメタルを形成して、このバリアメタルの表面に対して、金属ワイヤにおけるボール部を接合することは、そのボール接合の際に発生する電極パッド及び保護膜の損傷を、前記バリアメタルにて低減することができるものの、このバリアメタルをアルミニウム製電極パッドの表面に形成すると、この電極パッドに対する金等の金属ワイヤの接合性が低下するから、その接合に接合強度の低下等の接合不良が発生することのおそれが大きくなり、半導体装置におけるＩＣチップに金属ワイヤを接続するに際しての不良率が高くなると言う問題があった。
【０００５】
本発明は、この問題を解消することを技術的課題とするものである。
【０００６】
【課題を解決するための手段】
この技術的課題を達成するため本発明は、
「ＩＣチップの表面に、当該表面に形成されている各種の回路素子を覆う保護膜を、当該表面に形成されている金属ワイヤ接続用電極パッドを覆うように形成し、この保護膜のうち前記電極パッドの部分に、当該電極パッドの周囲に保護膜の電極パッドに対する重なり部を残して開口部を設け、前記金属ワイヤ接続用電極パッドの部分に、当該電極パッドに対して金属ワイヤにおけるボール部を接合するとき前記電極パッド及び前記保護膜に及ぼす損傷を低減するようにしたバリアメタル層を形成して成り、且つ、前記ＩＣチップを、パッケージ部にて密封して成る半導体装置であって、
前記バリアメタル層を、前記保護膜のうち前記電極パッドに対する重なり部を当該バリアメタル層にて覆うように構成することに加えて、このバリアメタル層のうち前記重なり部を覆う部分の外周縁に、前記保護膜のうち前記重なり部よりも外側の部分を覆うように同じ厚さで外向きに一体的に延びる延長部を設け、このバリアメタル層の表面に、金の層を形成し、この金の層に対して前記金属ワイヤにおけるボール部を、当該金の層がボール部と前記バリアメタル層との両方に合金化するように接合する。」
と言う構成にした。
【０００７】
【発明の作用・効果】
このように、金属ワイヤ接続用電極パッドに対するバリアメタル層の表面に、金の層を形成し、この金の層に対して前記金属ワイヤにおけるボール部を、当該金の層がボール部と前記バリアメタル層との両方に合金化するように接合することにより、金属ワイヤのバリアメタル層に対する接合性を確実に向上できるのである。
【０００８】
従って、本発明によると、半導体装置におけるＩＣチップに対する金属ワイヤの接合に際して、その金属ワイヤを電極パッドに対して確実、且つ、強固に接合することができるから、その際の不良率を大幅に低減できる効果を有する。
【０００９】
しかも、前記金属ワイヤ接続用電極パッドに対するバリアメタル層は、電極パッドのうち前記保護膜の開口部内の部分及び保護膜のうち開口部の周囲縁の部分を覆うように形成されていることにより、このバリアメタル層にて保護膜を押さえることができるから、前記の効果をより助長できる。
【００１０】
【発明の実施の形態】
以下、本発明の実施の形態を、二つのＩＣチップを使用した半導体装置に適用した場合の図面（図１〜図８）について説明する。
【００１１】
この図において符号１は、矩形状のチップマウント部１ａと、このチップマウント部１ａにおける四つの各辺から外向きに延びる複数本のリード端子１ｂとを備えたリードフレームを示す。
【００１２】
また、符号２は、前記リードフレーム１におけるチップマウント部１ａの上面にマウントされるメインＩＣチップを示し、このメインＩＣチップ２の上面には、図示しない能動素子又は受動素子等のような回路素子の多数個が形成されていると共に、その周囲に金属ワイヤ接続用電極パッド２ｃの多数個が、その内側に後述するサブＩＣチップ３に対する接続用の電極パッド２ａの多数個が各々形成されている。
【００１３】
更に、このメインＩＣチップの上面には、図３に示すように、当該上面に形成されている各種の回路素子を覆う保護膜２ｄが、前記各金属ワイヤ接続用電極パッド２ｃの部分を覆うように形成され、この保護膜２ｄのうち前記各金属ワイヤ接続用電極パッド２ｃの部分には、当該電極パッド２ｃの周囲に保護膜２ｄの電極パッド２ｃに対する重なり部を残すようにして開口部が設けられている。
【００１４】
加えて、前記各金属ワイヤ接続用電極パッド２ｃの部分には、当該電極パッド２ｃに対するバリアメタル層２ｅを、当該電極パッド２ｃのうち前記保護膜２ｄの開口部内の部分を覆うように形成することにより、前記電極パッド２ｃに対して後述する金属ワイヤ５をボール接合するとき前記電極パッド２ｃ及び前記保護膜２ｄに及ぼす損傷を前記バリアメタル層２ｅにて低減するようにする。
【００１５】
この場合において、前記バリアメタル層２ｅを、前記保護膜２ｄのうち前記電極パッド２ｃに対する重なり部を当該バリアメタル層２ｅにて覆うように構成することに加えて、このバリアメタル層２ｅのうち前記重なり部を覆う部分の外周縁に、前記保護膜２ｄのうち前記重なり部よりも外側の部分を覆うように同じ厚さで外向きに一体的に延びる延長部を設けた構成にする。なお、このバリアメタル層２ｅは、例えば、チタンを下層としタングステンを上層とするか、クロムを下層とし銀を上層とする二層構造に構成されている。
【００１６】
一方、符号３は、前記メインＩＣチップ２の上面にマウントされるサブＩＣチップを示し、このサブＩＣチップ３における表裏両面のうち片面には、前記メインＩＣチップ２と同様に図示しない能動素子又は受動素子等のような回路素子の多数個が形成されていると共に、前記メインＩＣチップ２の上面における各電極パッド２ｂの各々に対応する箇所ごとに接続用の電極パッド３ａが形成されている。
【００１７】
そして、前記メインＩＣチップ２における各電極パッド２ａ、及び前記サブＩＣチップ３における各電極パッド３ａの各々に、金又は半田によるバンプ２ｂ，３ｂを設ける一方、前記サブＩＣチップ３を、図４に示すように、その回路素子及び電極パッド３ａを形成した面を下向きにして、前記メインＩＣチップ２の上面側に、当該サブＩＣチップ３の各電極パッド３ａにおけるバンプ３ｂの各々が、メインＩＣチップ２の各電極バンプ２ｂにおけるバンプ２ｂの各々に接当するように載置したのち、全体を加熱しながら、サブＩＣチップ３をメインＩＣチップ２に対して押圧（この押圧と同時に超音波を振動を付与しても良い）することにより、互いに接当するバンプ２ｂ，３ｂを電気的に接合すると共に、前記メインＩＣチップ２の上面と、前記サブＩＣチップ３の下面との間の隙間に、エポキシ樹脂等の合成樹脂による接着剤４又はエラストマーを充填して、両ＩＣチップ２，３を一体化する。
【００１８】
次いで、これらの全体を、図５に示すように、前記リードフレーム１におけるチップマウント部１ａの上面に、前記メインＩＣチップ２を接着剤等にて固着するようにしてマウントしたのち、前記メインＩＣチップ２の上面における各金属ワイヤ接続用電極パッド２ｃと、リードフレーム１における各リード端子１ｂとの間を、細い金等の金属ワイヤ５によるワイヤボンディングにて電気的に接続するのである。
【００１９】
このワイヤボンディングに先立って、前記各金属ワイヤ接続用電極パッド２ｃの部分におけるバリアメタル層２ｅの表面に、予め金の層２ｅ′を、金のフラッシュメッキにて形成しておき、これに対して、図６に示すように、前記金属ワイヤ５に一端的に形成したボール部５ａを押圧することにより接合するのであって、前記金属ワイヤ５を電極パッド２ｃにおけるバリアメタル層２ｅに対してボール接合するときにおいて、前記金の層２ｅ′が、バリアメタル層２ｅ及び金属ワイヤ５の両方に対して合金化することになるから、金属ワイヤ５のバリアメタル層２ｅに対する接合性を確実に向上できるのである。
【００２０】
このようにして、一体化した二つのＩＣチップ２，３を、リードフレーム１にマウントしたのち、メインＩＣチップ２における各金属ワイヤ接続用電極パッド２ｃとリードフレーム１における各リード端子１ｂとの間を金属ワイヤ５にてワイヤボンディングすると、図７に示すように、全体を密封する合成樹脂製のパッケージ部６を、トランスファ成形によって成形し、次いで、図８に示すように、リードフレーム１から切り放したのち、各リード端子１ｂのうちパッケージ部６から突出する部分を、パッケージ部６の下面と略同一平面状になるように折り曲げすることにより、パッケージ型半導体装置の完成品とするのである。
【図面の簡単な説明】
【図１】本発明の実施形態を示す分解斜視図である。
【図２】図１の縦断正面図である。
【図３】図２の要部拡大図である。
【図４】前記実施形態においてメインＩＣチップに対してサブＩＣチップを一体化した状態を示す縦断正面図である。
【図５】前記実施形態においてサブＩＣチップをマウントしたメインＩＣチップをリードフレームに対してマウントした状態を示す縦断正面図である。
【図６】図５の要部拡大図である。
【図７】前記実施形態において全体を密封するパッケージ部を成形した状態を示す縦断正面図である。
【図８】前記実施形態における半導体装置の縦断正面図である。
【符号の説明】
１ リードフレーム
１ａ チップマウント部
１ｂ リード端子
２ メインＩＣチップ
２ａ 電極パッド
２ｂ バンプ
２ｃ 金属ワイヤ接続用電極パッド
２ｄ 保護膜
２ｅ バリアメタル層
２ｅ′ 金の層
３ サブＩＣチップ
３ａ 電極パッド
３ｂ バンプ
４ 合成樹脂の接着剤
５ 金属線
６ パッケージ部意見書に代る手続補正書[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which various circuit elements are formed on a surface of an IC chip, an electrode pad for connecting a metal wire to the circuit element is formed, and the IC chip is sealed in a package portion. It is related to the structure of.
[0002]
[Prior art]
Generally, in this type of semiconductor device, the metal wire connection electrode pads formed on the surface of the IC chip are made of aluminum, while the surface of the IC chip covers various circuit elements formed on the surface. A protective film made of an insulator is formed by providing an opening in the electrode pad portion, and a ball portion of a metal wire for connection to the outside is joined to a portion of the electrode pad in the opening of the protective film. However, in this structure, there is a great possibility that the electrode pad and the protective film may be damaged by an impact or the like when a metal wire such as gold is ball-joined to the electrode pad.
[0003]
Therefore, in a recent semiconductor device, for example, as described in Japanese Patent Application Laid-Open No. 3-227538, a barrier metal is provided at the portion of the metal wire connection electrode pad and the protective film of the electrode pad is provided. Is formed so as to cover the portion inside the opening and the portion of the protective film around the opening, and the ball portion of the metal wire is joined to the surface of the barrier metal .
[0004]
[Problems to be solved by the invention]
However, forming a barrier metal on the metal wire connection electrode pad and bonding the ball portion of the metal wire to the surface of the barrier metal as described above occurs during the ball bonding. damage of the electrode pads and the protective film, although it is possible to reduce by the barrier metal, to form a barrier metal on the surface of the aluminum electrode pad, lowering the bonding of metal wires such as gold for the electrode pads Therefore, there is a high possibility that a bonding failure such as a decrease in bonding strength occurs in the bonding, and a failure rate when a metal wire is connected to an IC chip in a semiconductor device is increased.
[0005]
An object of the present invention is to solve this problem.
[0006]
[Means for Solving the Problems]
To achieve this technical problem, the present invention
"On the surface of the IC chip, a protective film covering various circuit elements formed on the surface is formed so as to cover the metal wire connection electrode pads formed on the surface. In the electrode pad portion, an opening is provided around the electrode pad except for an overlapping portion of the protective film with respect to the electrode pad, and the ball portion of the metal wire with respect to the electrode pad is provided in the metal wire connection electrode pad portion. A semiconductor device formed by forming a barrier metal layer so as to reduce damage to the electrode pad and the protective film when bonding the IC chip, and sealing the IC chip in a package portion.
The barrier metal layer, the overlap portion with respect to the electrode pads of the protective film in addition to be configured to cover at the barrier metal layer, the outer peripheral edge of the portion covering the overlapping portion of the barrier metal layer Providing an extension integrally extending outward with the same thickness to cover a portion of the protective film outside the overlapping portion, forming a gold layer on the surface of the barrier metal layer , The ball portion of the metal wire is bonded to the gold layer such that the gold layer alloys with both the ball portion and the barrier metal layer . "
It was configured to say.
[0007]
[Action and Effect of the Invention]
In this way, a gold layer is formed on the surface of the barrier metal layer for the metal wire connection electrode pad, and the ball portion of the metal wire is formed on the gold layer, and the gold layer is formed on the ball portion and the barrier. by bonding to alloying with both the metal layer, it can be reliably improved bondability with respect to the barrier metal layer of a metal wire.
[0008]
Therefore, according to the present invention, when a metal wire is bonded to an IC chip in a semiconductor device, the metal wire can be securely and firmly bonded to an electrode pad, thereby greatly reducing the defective rate at that time. Has an effect that can be.
[0009]
Moreover, the barrier metal layer for the metal wire connection electrode pad is formed so as to cover a portion of the electrode pad within the opening of the protective film and a portion of the protective film at a peripheral edge of the opening, Since the protective film can be suppressed by the barrier metal layer , the above-mentioned effect can be further promoted.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, drawings (FIGS. 1 to 8) in which the embodiment of the present invention is applied to a semiconductor device using two IC chips will be described.
[0011]
In this figure, reference numeral 1 denotes a lead frame including a rectangular chip mount 1a and a plurality of lead terminals 1b extending outward from four sides of the chip mount 1a.
[0012]
Reference numeral 2 denotes a main IC chip mounted on the upper surface of the chip mount portion 1a of the lead frame 1. On the upper surface of the main IC chip 2, a circuit element such as an active element or a passive element (not shown) is provided. Are formed, a plurality of metal wire connection electrode pads 2c are formed therearound, and a plurality of connection electrode pads 2a for connection to a sub IC chip 3 described later are formed inside thereof. .
[0013]
Further, on the upper surface of the main IC chip, as shown in FIG. 3, a protective film 2d covering various circuit elements formed on the upper surface covers the respective metal wire connection electrode pads 2c. In the protective film 2d, an opening is provided in the portion of each of the metal wire connection electrode pads 2c so as to leave an overlapping portion of the protective film 2d on the electrode pad 2c around the electrode pad 2c. Have been.
[0014]
In addition, a barrier metal layer 2e for the electrode pad 2c is formed on the portion of each metal wire connection electrode pad 2c so as to cover a portion of the electrode pad 2c in the opening of the protective film 2d. Accordingly, when the metal wire 5 described later is ball-bonded to the electrode pad 2c, damage to the electrode pad 2c and the protective film 2d is reduced by the barrier metal layer 2e.
[0015]
In this case, the barrier metal layer 2e, the overlap portion with respect to the electrode pads 2c of the protective layer 2d in addition to be configured to cover at the barrier metal layer 2e, the one of the barrier metal layer 2e An extension is provided on the outer peripheral edge of the portion that covers the overlapping portion and extends outward integrally with the same thickness so as to cover a portion of the protective film 2d outside the overlapping portion. The barrier metal layer 2e has, for example, a two-layer structure in which titanium is a lower layer and tungsten is an upper layer, or chromium is a lower layer and silver is an upper layer.
[0016]
On the other hand, reference numeral 3 denotes a sub IC chip mounted on the upper surface of the main IC chip 2, and one of the front and back surfaces of the sub IC chip 3 has an active element (not shown) similar to the main IC chip 2. A large number of circuit elements such as passive elements are formed, and connection electrode pads 3a are formed at locations on the upper surface of the main IC chip 2 corresponding to the respective electrode pads 2b.
[0017]
Then, bumps 2b and 3b made of gold or solder are provided on each of the electrode pads 2a of the main IC chip 2 and each of the electrode pads 3a of the sub IC chip 3, while the sub IC chip 3 is shown in FIG. As shown, with the surface on which the circuit elements and the electrode pads 3a are formed face down, on the upper surface side of the main IC chip 2, each of the bumps 3b of each electrode pad 3a of the sub IC chip 3 After pressing the sub IC chip 3 against the main IC chip 2 while heating the whole (after the ultrasonic wave is vibrated at the same time) May be provided), thereby electrically connecting the bumps 2b and 3b which are in contact with each other, and the upper surface of the main IC chip 2. , The gap between the lower surface of the sub-IC chip 3, and filled with an adhesive 4 or elastomeric with synthetic resin such as epoxy resin, to integrate both IC chips 2 and 3.
[0018]
Next, as shown in FIG. 5, the entire main IC chip 2 is mounted on the upper surface of the chip mount portion 1a of the lead frame 1 by fixing the main IC chip 2 with an adhesive or the like. The electrode pads 2c for connecting metal wires on the upper surface of the chip 2 and the lead terminals 1b on the lead frame 1 are electrically connected by wire bonding using thin metal wires 5 such as gold.
[0019]
Prior to this wire bonding, a gold layer 2e 'is previously formed on the surface of the barrier metal layer 2e at the portion of each of the metal wire connection electrode pads 2c by gold flash plating. As shown in FIG. 6, the ball portion 5a formed on one end of the metal wire 5 is pressed to join the metal wire 5, and the metal wire 5 is ball-joined to the barrier metal layer 2e in the electrode pad 2c. In this case, the gold layer 2e 'is alloyed with both the barrier metal layer 2e and the metal wire 5, so that the bonding property of the metal wire 5 to the barrier metal layer 2e can be surely improved. is there.
[0020]
After mounting the two integrated IC chips 2 and 3 on the lead frame 1 in this manner, a gap between each metal wire connection electrode pad 2c on the main IC chip 2 and each lead terminal 1b on the lead frame 1 is obtained. 7 is wire-bonded with a metal wire 5 to form a synthetic resin package portion 6 for sealing the whole by transfer molding as shown in FIG. 7, and then cut off from the lead frame 1 as shown in FIG. Thereafter, a portion of each lead terminal 1b protruding from the package portion 6 is bent so as to be substantially flush with the lower surface of the package portion 6, thereby obtaining a completed package type semiconductor device.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing an embodiment of the present invention.
FIG. 2 is a vertical sectional front view of FIG.
FIG. 3 is an enlarged view of a main part of FIG. 2;
FIG. 4 is a longitudinal sectional front view showing a state where a sub IC chip is integrated with a main IC chip in the embodiment.
FIG. 5 is a vertical sectional front view showing a state where a main IC chip on which a sub IC chip is mounted in the embodiment is mounted on a lead frame;
FIG. 6 is an enlarged view of a main part of FIG. 5;
FIG. 7 is a longitudinal sectional front view showing a state in which a package portion for sealing the whole is molded in the embodiment.
FIG. 8 is a vertical sectional front view of the semiconductor device in the embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 Main IC chip 2a Electrode pad 2b Bump 2c Metal wire connection electrode pad 2d Protective film 2e Barrier metal layer 2e 'Gold layer 3 Sub IC chip 3a Electrode pad 3b Bump 4 Synthetic resin Adhesive 5 Metal wire 6 Procedure amendment instead of package part opinion

Claims (1)

ＩＣチップの表面に、当該表面に形成されている各種の回路素子を覆う保護膜を、当該表面に形成されている金属ワイヤ接続用電極パッドを覆うように形成し、この保護膜のうち前記電極パッドの部分に、当該電極パッドの周囲に保護膜の電極パッドに対する重なり部を残して開口部を設け、前記金属ワイヤ接続用電極パッドの部分に、当該電極パッドに対して金属ワイヤにおけるボール部を接合するとき前記電極パッド及び前記保護膜に及ぼす損傷を低減するようにしたバリアメタル層を形成して成り、且つ、前記ＩＣチップを、パッケージ部にて密封して成る半導体装置であって、
前記バリアメタル層を、前記保護膜のうち前記電極パッドに対する重なり部を当該バリアメタル層にて覆うように構成することに加えて、このバリアメタル層のうち前記重なり部を覆う部分の外周縁に、前記保護膜のうち前記重なり部よりも外側の部分を覆うように同じ厚さで外向きに一体的に延びる延長部を設け、このバリアメタル層の表面に、金の層を形成し、この金の層に対して前記金属ワイヤにおけるボール部を、当該金の層がボール部と前記バリアメタル層との両方に合金化するように接合することを特徴とする半導体装置の構造。A protective film covering various circuit elements formed on the surface of the IC chip is formed on the surface of the IC chip so as to cover the metal wire connection electrode pads formed on the surface. In the pad portion, an opening is provided around the electrode pad except for an overlapping portion of the protective film with respect to the electrode pad, and the ball portion of the metal wire with respect to the electrode pad is provided in the metal wire connection electrode pad portion. A semiconductor device comprising a barrier metal layer formed so as to reduce damage to the electrode pad and the protective film at the time of bonding, and sealing the IC chip with a package portion,
The barrier metal layer, the overlap portion with respect to the electrode pads of the protective film in addition to be configured to cover at the barrier metal layer, the outer peripheral edge of the portion covering the overlapping portion of the barrier metal layer Providing an extension integrally extending outward with the same thickness to cover a portion of the protective film outside the overlapping portion, forming a gold layer on the surface of the barrier metal layer , A structure of a semiconductor device, wherein a ball portion of the metal wire is joined to a gold layer such that the gold layer alloys with both the ball portion and the barrier metal layer .
JP19556097A 1997-01-24 1997-07-22 Structure of semiconductor device Expired - Lifetime JP3555062B2 (en)

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JP19556097A JP3555062B2 (en) 1997-07-22 1997-07-22 Structure of semiconductor device
PCT/JP1998/000281 WO1998033217A1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
KR10-1998-0707403A KR100522223B1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
EP98900725A EP0890989A4 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
US09/155,134 US6133637A (en) 1997-01-24 1998-01-22 Semiconductor device having a plurality of semiconductor chips
KR10-2004-7000090A KR100467946B1 (en) 1997-01-24 1998-01-22 Method for manufacturing a semiconductor chip
US09/612,480 US6458609B1 (en) 1997-01-24 2000-07-07 Semiconductor device and method for manufacturing thereof

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