JP3551934B2 - GBIC communication interface device and GBIC communication interface method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a GBIC communication interface device and a GBIC communication interfaceMethodIn particular, the present invention relates to a communication interface system defined in IEEE 802.3.
[0002]
[Prior art]
The relationship between MAC and PHY in 1000BASE-X (1000BASE-SX / LX / CX), 1000BASE-T, and 10 / 100BASE-TX specified in IEEE 802.3 is shown in FIGS. 5 to 7, respectively.
[0003]
In FIG. 5, a PHY (physical layer) 5 of 1000BASE-X includes a PCS (Physical Coding Sublayer: Physical Coding Sublayer) 51, a PMA (Physical Media Attachment sublayer: Physical Media Attachment) 52, and a PMD (PhysicalDiamondMedicalMedicalMedicalMedicalMedication). A media access control (MAC) 4 is provided to a media access control (MAC) 4 by a GMII (Gigabit Media Independent Interface: Gigabit speed medium independent interface) (8-bit parallel data signal + 4-bit control signal + transmission / reception clock signal) ) (125 MHz) It sends the differential serial data signal (1.25 GHz) to the 000BASE-X.
[0004]
Here, the MAC 4 controls access to the PHY 5 to schedule data transmission and reception. The PCS 51 encodes data to be transmitted in a form suitable for a physical medium, and the PMA 52 performs serialization (serialization) of a packet to be transmitted and deserialization that is the reverse process. Further, the PMD 53 converts the transmitted voltage change pattern into a light wave or a pulse so that it can be transmitted by a cable.
[0005]
In the 1000BASE-X, the PCS 51 and the PMA 52 are shared, so that a 1000BASE-SX GBIC (Gigabit Interface Converter) module, a 1000BASE-LX GBIC module, and a 1000BASE-CX are used as a GBD (Gigabit Interface Converter) interface as PMD53. A GBIC module can be connected.
[0006]
In FIG. 6, the PHY 7 of 1000BASE-T includes a T_PCS 71 and a T_PMA 72, is connected to the MAC 6 by GMII (8-bit parallel data signal + 4-bit control signal + transmission / reception clock signal) (125 MHz), A data signal (125 MHz) is transmitted. T_PCS71 and T_PMA72 are different from PCS51 / PMA52 of 1000BASE-X.
[0007]
In FIG. 7, the PHY 9 of 10 / 100BASE-TX includes a TX_PCS 91, a TX_PMA 92, and a TX_PMD 93. The MAC 8 has a media independent interface (MII) (4-bit parallel data signal + 4-bit control signal + transmission / reception clock signal). ) (25 / 2.5 MHz) and sends out a differential serial data signal (125/25 MHz) to 10/100 BASE-TX. TX_PCS91 and TX_PMA92 are different from PCS51 / PMA52 of 1000BASE-X.
[0008]
[Problems to be solved by the invention]
In the conventional communication interface method described above, since 1000BASE-T is configured by T_PCS and T_PMA different from PCS / PMA of 1000BASE-X, it cannot support the GBIC interface.
[0009]
Also, since 10/10 / BASE-TX is configured with TX_PCS and TX_PMA different from PCS / PMA of 1000BASE-X, it cannot support the GBIC interface.
[0010]
Furthermore, since the GMII 4-bit control signal and the transmission / reception clock signal used in 1000BASE-X are not supplied to the GBIC interface, 1000BASE-TPHY and 10 / 100BASE-TX PHY which require the 4-bit control signal and the transmission / reception clock signal as input / output signals. Cannot be connected to the GBIC interface.
[0011]
As described above, the conventional GBIC interface has a problem that 1000BASE-T and 10 / 100BASE-TX cannot support the GBIC interface.
[0012]
Therefore, an object of the present invention is to solve the above-mentioned problems and to realize a GBIC communication interface device and a GBIC communication interface capable of realizing support of various standards of 10 Mbps / 100 Mbps / 1000 Mbps.MethodIs to provide.
[0013]
[Means for Solving the Problems]
A GBIC communication interface device according to the present invention includes a physical coding sublayer that encodes data to be transmitted in a form suitable for a physical medium, and a physical media attachment that performs serialization and deserialization of a packet for transmission. Access control that controls access to the physical layer to schedule data transmission and reception, a GBIC (Gigabit Interface Converter) module that incorporates physical layers of various standards of 10 Mbps / 100 Mbps / 1000 Mbps, and the GBIC Control means for controlling the operation of the physical coding sublayer according to the type of module;Means for determining the type of the GBIC module to be connected;Signal control between the medium access control and a physical layer in the GBIC module according to the determined type of the GBIC moduleWhenSignal control means for performing,
The signal control means controls the physical layer in the GBIC module from the medium access control by using a medium-independent interface / signal via a signal line of transmission disable, transmission failure, and reception loss defined by a GBIC connector. A control data clock, a control data input / output and a transmission clock of a gigabit speed medium independent interface signal are connected between the medium access control and a physical layer in the GBIC module.ing.
[0014]
GBIC communication interface according to the inventionMethodIs a physical coding sublayer that encodes the data to be transmitted in a form suitable for the physical media, a physical layer that includes a physical media attachment that performs serialization and deserialization of packets for transmission, Medium access control for controlling data access and scheduling of data transmission and reception, and a GBIC (Gigabit Interface Converter) module incorporating a physical layer of various standards of 10 Mbps / 100 Mbps / 1000 Mbps are provided.
In accordance with the type of the GBIC module to be connected, operation control of the physical coding sublayer and signal control between the medium access control and a physical layer in the GBIC module are performed.I
A media independent interface / gigabit speed media independent interface via a transmission disable, transmission failure and reception loss signal line defined by a GBIC connector for controlling the physical layer in the GBIC module from the medium access control A control data clock, a control data input / output, and a transmission clock of a signal are connected between the medium access control and a physical layer in the GBIC module.Like that.
[0015]
In other words, the GBIC communication interface device of the present invention provides a 10BASE / 100BASE / 1000BASE Ethernet function in an SFF-8053 GBIC (Gigabit Interface Converter) communication interface corresponding to an IEEE (registered trademark) 802.3 communication interface. In order to support this, the type of the GBIC module connected between the MAC (Media Access Control: Media Access Control) and the GBIC module incorporating the PHY (physical layer) of various standards of 10 Mbps / 100 Mbps / 1000 Mbps is GMII (Gigabit Media Independent Interface) It has a GBIC I / F (interface) control unit for controlling between the communication speed medium independent interface) and the GBIC interface, and connects the GBIC interface and the GMII in the GBIC module to enable data transmission and reception. GMII bridge section.
[0016]
More specifically, in the GBIC communication interface device of the present invention, in order to control the PHY in the GBIC module from the MAC in the GBIC communication interface, the TX_DISABLE (transmission disabled) defined in the GBIC (gigabit interface converter) connector is used. ), TX_FAULT (transmission failure), RX_LOS (reception loss) signals, MDC (control data clock), MDIO (control data input / output) of MII (Media Independent Interface) / GMII interface signals , GTX_CLK (gigabit transmission clock).
[0017]
Further, in the GBIC communication interface device of the present invention, the MDC / MDIO / GTX_CLK / RX_CLK signals and the 8B10B (8-bit 10-bit encoding) of the 1000BASE-X PHY circuit are controlled according to the type of the GBIC module to be connected. It has a GBIC I / F control circuit.
[0018]
Further, in the GBIC communication interface device of the present invention, in the GBIC communication interface, TXD (transmission data) <0-7> and TX_EN (transmission enable) for connecting the PHY MII / GMII interface signal in the GBIC module to the MAC. ), TX_ER (transmission error), RXD (reception data) <0-7>, RX_DV (reception enable), and RX_ER (reception error).
[0019]
As a result, the communication interface using the GBIC I / F can support only 1000 BASE-X, that is, 1000 BASE-SX, 1000 BASE-LX, and 1000 BASE-CX conventionally defined in IEEE802.3. According to the present invention, it is possible to realize support for various standards of 10 Mbps / 100 Mbps / 1000 Mbps.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a GBIC communication interface device according to one embodiment of the present invention. In FIG. 1, a switching hub 1 switches a memory 11 used for storing and holding data, a console I / O 8 input / output circuit for connecting an external management console terminal (not shown) 12, and a packet switch. It comprises a packet switching mechanism 13, a CPU (Central Processing Unit) 14 for performing routing processing and the like, and interface cards 2 and 3.
[0021]
The interface card 2 includes a packet forwarding mechanism 21 for transferring packets, MACs (Media Access Control) 22 and 23 for processing and processing packets, PHYs (physical layers) 24 and 25, and GBICs (Gigabit Media). Independent Interface (gigabit interface converter) I / F (interface) control units 26 and 27, a 1000BASE-T GBIC module 28, and a 1000BASE-SX GBIC module 29 are mounted.
[0022]
The interface card 3 includes a packet forwarding mechanism 31 for transferring packets, MACs 32 and 33 for processing and processing packets, PHYs 34 and 35, GBIC I / F controllers 36 and 37, and a 10/100 BASE-TX GBIC module 38. And a 1000BASE-SX GBIC module 39.
[0023]
The PHYs 24, 25, 34, and 35 are physical layers of 1000BASE-X (1000BASE-SX, 1000BASE-LX, 1000BASE-CX), and 1000BASE-T GBIC module 28, 1000BASE-SX GBIC module 29, and 10 / 100BASE- Each of the TX GBIC module 38 and the 1000 BASE-SX GBIC module 39 has a physical layer (not shown) of various standards (1000 BASE-T, 1000 BASE-SX, and 10/100 BASE-TX) of 10 Mbps / 100 Mbps / 1000 Mbps.
[0024]
FIG. 2 is a block diagram showing a detailed configuration of the MAC 22, the PHY 24, the GBIC I / F control unit 26, and the 1000BASE-T GBIC module 28 constituting the port # 1 of the interface card 2 of FIG. 2, the PHY 24 includes a PCS (Physical Coding Sublayer: Physical Coding Sublayer) 241 and a PMA (Physical Media Attachment sublayer: Physical Media Attachment) 242.
[0025]
Here, the MAC 22 controls access to the PHY 24 to schedule data transmission and reception. The PCS 241 encodes data to be transmitted in a form suitable for a physical medium, and the PMA 242 performs serialization (serialization) of a packet to be transmitted and deserialization that is the reverse process.
[0026]
The GBIC I / F control unit 26 includes a clock recovery circuit 261, a switch circuit 262, a comparison circuit 263, a signal control circuit 264, and a GBIC detection circuit 265.
[0027]
The 1000 BASE-T GBIC module 28 includes a GMII (Gigabit Media Independent Interface) interface 281, a serial ROM 284, and a 1000 BASE-T PHY 285. The GMII bridge unit 281 includes a serial / parallel conversion circuit 282 and a parallel / serial conversion circuit 283.
[0028]
That is, on the port # 1 side of the interface card 2, GMII [MDC (control data clock) / MDIO (control data input / output) / TX_CLK between the MAC 22 and the GBIC interface depends on the type of the GBIC module connected. (Transmission clock) / RX_CLK (reception clock)] and a GBIC I / F control unit 26 that controls the PCS 241 to transmit and receive data, and can transmit and receive data between the MAC 22 and the 1000BASE-T PHY 285. And a 1000 BASE-T PHY 285 connected by GMII are disposed inside the 1000 BASE-T GBIC module 28.
[0029]
Thus, the SFF-8053 GBIC communication interface compatible with the IEEE (registered trademark) 802.3 Ethernet (registered trademark) communication interface can support the 10BASE / 100BASE / 1000BASE Ethernet function.
[0030]
FIG. 3 is a block diagram showing a detailed configuration of the MAC 23, the PHY 25, the GBIC I / F control unit 27, and the 1000BASE-SX GBIC module 29 that constitute the port # 2 of the interface card 2 of FIG. In FIG. 3, the PHY 25 includes a PCS 251 and a PMA 252.
[0031]
The GBIC I / F control unit 27 includes a clock recovery circuit 271, a switch circuit 272, a comparison circuit 273, a signal control circuit 274, and a GBIC detection circuit 275. The 1000BASE-T GBIC module 29 includes a serial ROM 291 and a 1000BASE-SX PMD (Physical Media Dependent sublayer: physical media dependent) 292.
[0032]
FIG. 4 is a block diagram showing a detailed configuration of the MAC 32, the PHY 34, the GBIC I / F control unit 36, and the 10/100 BASE-TX GBIC module 38 that constitute the port # 3 of the interface card 3 in FIG. In FIG. 4, the PHY 34 includes a PCS 341 and a PMA 342.
[0033]
The GBIC I / F control unit 36 includes a clock recovery circuit 361, a switch circuit 362, a comparison circuit 363, a signal control circuit 364, and a GBIC detection circuit 365.
[0034]
The 10 / 100BASE-TX GBIC module 38 includes a GMII bridge unit 381, a serial ROM 384, and a 10 / 100BASE-TX PHY 385. The GMII bridge unit 381 includes a serial / parallel conversion circuit 382 and a parallel / serial conversion circuit 383.
[0035]
That is, on the port # 3 side of the interface card 3, a GMII bridge unit 381 and a MII (Media Independent Interface) for enabling transmission and reception of data between the MAC 32 and the 10/100 BASE-TX PHY 385 And a 10/100 BASE-TX PHY 385 connected inside the 10/100 BASE-TX GBIC module 38.
[0036]
With reference to FIGS. 1 to 4, an overall flow when data is transmitted / received at ports # 1 to # 3 in one embodiment of the present invention will be described. First, the data transmission / reception operation on port # 1 will be described with reference to FIG.
[0037]
The transmission data is transmitted from the packet forwarding mechanism 21 to the MAC 22 in the interface card 2, and is transmitted to the PCS 241 of the PHY 24 as GMII TXD (transmission data) <0-7>, TX_EN (transmission enable), and TX_ER (transmission error).
[0038]
At this time, since the data sent to the PCS 241 is controlled by the GBIC I / F control unit 26 so that the internal function of the PCS 241 does not operate, the data is sent to the PMA 242 without any processing. The detailed operation of the GBIC I / F control unit 26 will be described later. The data sent to the PMA 242 is converted into a serial signal and sent to the 1000BASE-T GBIC module 28 as transmission data.
[0039]
The transmission data sent to the 1000BASE-T GBIC module 28 is sent to the GMII bridge unit 281 and is converted into a parallel signal by the serial / parallel conversion circuit 282, and the GMII RXD (receive data) <0-7> and RX_DV (receive Enable), 1000BASE-T as RX_ER (reception error)
Input to PHY285.
[0040]
At this time, the reception data clock RX_CLK is supplied from the MAC 22 to the 1000BASE-T PHY 285 via the GBIC I / F control unit 26, and the data input to the RXD <0-7> is synchronized with the RX_CLK, The data is transmitted to port # 1 through the internal processing of 1000BASE-T PHY285.
[0041]
The detailed operation of the GBIC I / F control units 26, 27, 36 will be described below. The GBIC I / F control units 26, 27, and 36 can be connected to existing 1000BASE-X GBIC modules (not shown), 1000BASE-T GBIC modules 28, 1000BASE-SX GBIC modules 29, and 10 / 100BASE-TX GBIC modules 38. Thus, it has a function of switching various signals.
[0042]
When the 1000 BASE-X GBIC module, the 1000 BASE-T GBIC module 28, the 1000 BASE-SX GBIC module 29, and the 10/100 BASE-TX GBIC module 38 are connected, the GBIC detection circuits 265, 275, and 365 determine the type of the connected GBIC module. Is read using an I2C I / F (interface) to recognize the type of the GBIC module to be connected.
[0043]
Next, the GBIC I / F control units 26, 27, and 36 use the comparison circuits 263, 273, and 383 to determine whether or not the GBIC module is a 1000BASE-X GBIC module. Using 362, the operation control of PCS 241, 251 and 341 and the signal control of RX_CLK, TX_CLK, MDIO and MDC are performed according to the type of the GBIC module to be connected. Each signal control is performed as follows.
[0044]
When the 1000BASE-X GBIC module is connected, control is performed to operate the PCSs 241, 251 and 341. At this time, the clock recovery circuits 261, 271 and 361 perform control so as not to output RX_CLK, and the signal control circuits 264, 274 and 364 perform control so as not to supply TX_CLK, MDIO and MDC to the GBIC module.
[0045]
Next, when a GBIC module other than the 1000BASE-X GBIC module is connected, control is performed so that the PCSs 241, 251 and 341 are not operated. At this time, the clock recovery circuits 261, 271 and 361 extract the clock from the RXD <0> and control to supply RX_CLK to the MACs 22, 23 and 32, and the signal control circuit 24 controls the GMII of the MACs 22, 23 and 32. TX_CLK (transmission clock), MDIO (control data input / output), and MDC (control data clock) are supplied to the GBIC module.
[0046]
On the other hand, received data is processed as follows. The data received by the port # 1 is transmitted to the GMII bridge unit 281 through the GMII TXD (transmission data) <0-7>, TX_EN (transmission enable), and TX_ER (transmission error) of the 1000BASE-T PHY 285.
[0047]
The GMII bridge section 281 converts the received data into serial data. The serially converted received data is transmitted to the GBIC interface and then input to the PMA 242. The PMA 242 converts the data into parallel data and transmits the data to the PCS 241. At this time, since the PCS 241 is controlled not to operate by the GBIC I / F control unit 26, the data is directly used as RXD (reception data) <0-7>, RX_DV (reception enable), and RX_ER (reception error). Sent to GMII of MAC22.
[0048]
At this time, the reception data clock RX_CLK is supplied from the clock recovery circuit 261 of the GBIC I / F control unit 26, and the signal sent to the MAC 22 is sent to the packet forwarding mechanism 21 and processed as reception data.
[0049]
Also, the communication control signal between the MAC 22 and the 1000BASE-T PHY 285, the MDIO and the MDC are connected via the GBIC I / F control unit 26 and the TX_FAULT (transmission failure) and the RX_LOS (reception loss) defined by the GBIC interface. When a link is established, information is sent from the 1000BASE-T PHY 285 to the MAC 22.
[0050]
The data transmission / reception operation at port # 2 will be described with reference to FIG. The transmission data is transmitted from the packet forwarding mechanism 21 of the interface card 2 to the MAC 23, and is transmitted to the PCS 251 as GMII TXD (transmission data) <0-7>, TX_EN (transmission enable), and TX_ER (transmission error).
[0051]
The data sent to the PCS 251 is 8B10B encoded and sent to the PMA 252. The data sent to the PMA 252 is converted into a serial signal, and sent to the 1000BASE-SX GBIC module 29 as transmission data.
[0052]
The transmission data sent to the 1000BASE-SX GBIC module 29 is sent to the 1000BASE-SX PMD 292, and the 1000BASE-SX PMD292 converts the electrical signal into an optical signal and sends it to the port # 2.
[0053]
The received data is processed as follows. The data received by the port # 2 is converted from an optical signal to an electrical signal by the 1000BASE-SX PMD 292, sent to the GBIC interface as received data, and input to the PMA 252.
[0054]
The received data is parallel-converted by the PMA 252 and transmitted to the PCS 251. The PCS 251 performs 10B8B decoding. The received data is transmitted to the GMII of the MAC 23 as RXD (received data) <0-7>, RX_DV (reception enable), and RX_ER (reception error). Sent. The signal sent to the MAC 23 is sent to the packet forwarding mechanism 21 of the interface card 2 and processed as received data.
[0055]
The data transmission / reception operation at port # 3 will be described with reference to FIG. The transmission data is sent from the packet forwarding mechanism 31 of the interface card 3 to the MAC 32, and is sent to the PCS 341 as GMII TXD (transmission data) <0-3>, TX_EN (transmission enable), and TX_ER (transmission error).
[0056]
At this time, since the internal function of the PCS 341 is controlled not to operate by the GBIC I / F control unit 36, the data sent to the PCS 341 is sent to the PMA 342 without any processing. The data sent to the PMA 342 is converted into a serial signal and sent to the 10/100 BASE-TX GBIC module 38 as transmission data.
[0057]
The transmission data sent to the 10/100 BASE-TX GBIC module 38 is sent to the GMII bridge unit 381, converted into a parallel signal by the serial / parallel conversion circuit 382, and MII RXD (received data) <0-3>, RX_DV ( Reception enable) and RX_ER (reception error) are input to the 10 / 100BASE-TX PHY 385.
[0058]
At this time, the received data clock RX_CLK is supplied from the MAC 32 to the 10/100 BASE-TX PHY 385 via the GBIC I / F control unit 36, and the data input to the RXD <0-3> is synchronized with the RX_CLK. Is transmitted to port # 3 via internal processing of 10 / 100BASE-TX PHY 385.
[0059]
The received data is processed as follows. The data received by the port # 3 is sent to the GMII bridge unit 381 through the MII TXD (transmission data) <0-3>, TX_EN (transmission enable), and TX_ER (transmission error) of the 10/100 BASE-TX PHY 385.
[0060]
The received data sent to the GMII bridge unit 381 is serial-converted, sent to the GBIC interface, and then input to the PMA 342. The received data is parallel-converted by the PMA 342 and transmitted to the PCS 341. At this time, the PCS 341 is controlled so as not to operate by the GBIC I / F control unit 36. -3>, RX_DV (reception enable), and RX_ER (reception error) to the GMII of the MAC 32.
[0061]
At this time, the reception data clock RX_CLK is supplied from the clock recovery circuit 361 of the GBIC I / F control unit 36, and the signal transmitted to the MAC 32 is transmitted to the packet forwarding mechanism 31 of the interface card 3 and processed as reception data. You.
[0062]
Further, the communication control signal between the MAC 32, the 10 / 100BASE-TX PHY 385, the MDIO and the MDC are transmitted via the GBIC I / F control unit 36 and TX_FAULT (transmission failure) and RX_LOS (reception loss) defined by the GBIC interface. When the connection is established and a link is established, information is sent from the 10/100 BASE-TX PHY 385 to the MAC 32.
[0063]
As described above, in the communication interface using the GBIC I / F, conventionally, only 1000BASE-SX, 1000BASE-LX, and 1000BASE-CX defined in IEEE802.3 can be supported, but according to the present invention, 10 Mbps is used. Support for various standards of / 100 Mbps / 1000 Mbps can also be realized.
[0064]
【The invention's effect】
As described above, according to the present invention, a physical coding sublayer that encodes data to be transmitted in a form suitable for a physical medium and a physical media attachment that performs serialization and deserialization of a packet for transmission are provided. GBIC in which a physical layer including a physical layer, a medium access control that controls access to the physical layer to schedule data transmission and reception, and a GBIC module that incorporates physical layers of various standards of 10 Mbps / 100 Mbps / 1000 Mbps are provided. The communication interface device controls the operation of the physical coding sublayer according to the type of the GBIC module to be connected, and controls the medium access control and the signal control between the physical layer in the GBIC module, thereby achieving 10Mbps / 100Mbps / 1000M. There is an effect that it is possible to realize the support of ps of various standards.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a GBIC communication interface device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of a MAC, a PHY, a GBIC I / F control unit, and a 1000BASE-T GBIC module which constitute a port # 1 of the interface card of FIG. 1;
FIG. 3 is a block diagram showing a detailed configuration of a MAC, a PHY, a GBIC I / F control unit, and a 1000BASE-SX GBIC module which constitute port # 2 of the interface card of FIG. 1;
FIG. 4 is a block diagram showing a detailed configuration of a MAC, a PHY, a GBIC I / F control unit, and a 10 / 100BASE-TX GBIC module which constitute port # 3 of the interface card of FIG. 1;
FIG. 5 is a diagram showing the relationship between MAC and PHY in 1000BASE-X defined in IEEE 802.3.
FIG. 6 is a diagram showing the relationship between MAC and PHY in 1000BASE-T defined in IEEE 802.3, as shown in FIGS.
FIG. 7 is a diagram showing the relationship between MAC and PHY in 10 / 100BASE-TX defined in IEEE 802.3.
[Explanation of symbols]
1 switching hub
2,3 interface card
11 Memory 11
12 Console I / O
13. Packet switching mechanism
14 CPU
21,31 Packet forwarding mechanism
22,23,32,33 MAC
24, 25, 34, 35 PHY
26, 27, 36, 37 GBIC I / F control unit
28 1000BASE-T GBIC module
29 1000BASE-SX GBIC module
38 10 / 100BASE-TX GBIC module
39 1000BASE-SX GBIC module
241,251,341 PCS
242,252,342 PMA
261, 271 and 361 clock recovery circuits
262,272,362 switch circuit
263,273,363 Comparison circuit
264, 274, 364 signal control circuit
265, 275, 365 GBIC detection circuit
281,381 GMII bridge
282,382 Serial / parallel conversion circuit
283,293 Parallel-serial conversion circuit
284,291,384 Serial Rom
285 1000BASE-T PHY
292 1000BASE-SX PMD
385 10 / 100BASE-TX PHY

Claims (8)

A physical layer including a physical coding sublayer for encoding data to be transmitted in a form suitable for a physical medium, a physical medium attachment for serializing and deserializing a packet for transmission, and an access to the physical layer Access control that controls transmission and reception of data by controlling data transfer, a GBIC (Gigabit Interface Converter) module having a built-in physical layer of various standards of 10 Mbps / 100 Mbps / 1000 Mbps, and the physical coding according to the type of the GBIC module said control means for controlling the operation of the sub, and means for discriminating a type of the GBIC module coupled, to the medium access control according to the type of the discriminated said GBIC module GBIC Have a signal control means for performing a signal control between the physical layer in joules,
The signal control means controls the physical layer in the GBIC module from the medium access control by using a medium-independent interface / signal via a signal line of transmission disable, transmission failure, and reception loss defined by a GBIC connector. A GBIC communication interface , wherein a control data clock, a control data input / output, and a transmission clock of a gigabit-speed medium-independent interface signal are connected between the medium access control and a physical layer in the GBIC module. apparatus. The signal control unit, according to claim 1, characterized in that so as to control the supply to the GBIC module and said GBIC module receive clock type in accordance with the control data clock control data input and output and the transmission clock GBIC communication interface apparatus according. The control means according to claim 1 or claim 2, characterized in that so as to control so as not to operate the physical coding sub-layer if the GBIC module other than the predetermined GBIC module which is set in advance is connected GBIC communication interface apparatus according. Connect the transmission data, transmission enable, transmission error, reception data, reception enable, and reception error for linking the medium independent interface / gigabit speed medium independent interface signal of the physical layer in the GBIC module to the medium access control. 4. The GBIC communication interface device according to claim 1 , wherein a bridge circuit for performing the operation is included in the GBIC module. A physical layer including a physical coding sublayer for encoding data to be transmitted in a form suitable for a physical medium, a physical medium attachment for serializing and deserializing a packet for transmission, and an access to the physical layer And a medium access control for scheduling data transmission and reception and a GBIC (Gigabit Interface Converter) module including a physical layer of various standards of 10 Mbps / 100 Mbps / 1000 Mbps are provided.
There line signals control between the physical layer in the GBIC module the GBIC module and motion control and the medium access control of the physical coding sub-layer according to the type of connected,
A media independent interface / gigabit speed media independent interface via a transmission disable, transmission failure and reception loss signal line defined by a GBIC connector for controlling the physical layer in the GBIC module from the medium access control A GBIC communication interface method , wherein a control data clock of a signal, a control data input / output, and a transmission clock are connected between the medium access control and a physical layer in the GBIC module . 6. The GBIC communication interface method according to claim 5 , wherein supply of a control data clock, a control data input / output, a transmission clock, and a reception clock to the GBIC module is controlled in accordance with the type of the GBIC module. . 7. The GBIC communication interface according to claim 5 , wherein when a GBIC module other than a predetermined GBIC module set in advance is connected, the physical coding sublayer is controlled so as not to operate. How . The transmission data, transmission enable, transmission error, reception data, reception enable, and reception error for connecting the medium independent interface / gigabit speed medium independent interface signal of the physical layer in the GBIC module to the medium access control. 8. The GBIC communication interface method according to claim 5 , wherein the connection is made by a bridge circuit in the GBIC module.

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