JP3551356B2 - Integrated circuit device and liquid crystal display device using the same - Google Patents

Description

【００２１】
以上の構成のＰＲＯＭデコーダ５１６Ｐの１段の動作を説明する。各トランジスタ直列回路３３ＰＡ，３３ＰＢの一端側である第１列目，第２４列目のトランジスタ３１Ｐ又は３２Ｐのソースに６４階調の正極性階調電圧ＶＰ１ 〜ＶＰ３２，ＶＰ３３〜ＶＰ６４が与えられる。この状態で各ゲート列対３４ＰＡ，３４ＰＢに”Ｈ（ハイレベル）”又は”Ｌ”の表２に示す所定のデータ信号ＤＰ１，ＤＰ２，…，ＤＰ６がゲート列３４ＰＡａ，３４ＰＢａに正相ＤＰ１，ＤＰ２，…，ＤＰ６で供給され、ゲート列３４ＰＡｂ，３４ＰＢｂに逆相ＤＰ１バー，ＤＰ２バー，…，ＤＰ６バーでそれぞれ供給されると各トランジスタ直列回路３３ＰＡ，３３ＰＢの内選択された１つのトランジスタ直列回路３３ＰＡ，３３ＰＢのトランジスタ３１Ｐ，３２Ｐがすべてオン状態（トランジスタ３２Ｐは常時オン状態）となり、そのトランジスタ直列回路３３ＰＡ，３３ＰＢに与えられている階調電圧が取り出される。尚、ＮＲＯＭデコーダ５１６Ｎの１段分の構成、動作についても、各極性および導電型が替わる以外は同様なため説明を省略する。
【００２２】
【表２】

【００２３】
次に、図２に示す回路ブロック５０３ａ内のＤ／Ａコンバータ５１６のＰＲＯＭデコーダ５１６ＰとＮＲＯＭデコーダ５１６Ｎの半導体チップ５０１上でのパターン配置は、図５に示すように、３段を一まとめにしたＰＲＯＭデコーダ５１６Ｐが３段を一まとめにしたＮＲＯＭデコーダ５１６Ｎにチップ長尺方向（図面で右側）に隣接して配置されている。ＰＲＯＭデコーダ５１６ＰはＰ型半導体基板４１に配置されたＮウェル４２内に、３２行２４列のマトリックス配置されたトランジスタ３１Ｐ，３２ＰのソースおよびドレインとなるＰ型拡散層４３Ｐと、各段２４本のゲート列３４ＰＡａ，３４ＰＡｂ，３４ＰＢａ，３４ＰＢｂとなるゲート配線４４Ｐとを３段分含んで構成されている。ゲート配線４４Ｐは各段それぞれ、第ｉ（ｉ＝１，２，…，１２）列目と第（２５−ｉ）列目とのゲート列を共通接続している。第１段目の第１列目、第２段目の第２４列目および第３段目の第１列目のトランジスタ３１Ｐ又は３２ＰのソースとなるＰ型拡散層４３Ｐは行毎に金属配線４５ＰＡにより電気的に共通接続（●印で図示する）され階調電圧発生回路から各正極性階調電圧ＶＰ１ 〜ＶＰ３２がそれぞれ１階調づつ供給されるようになっている。第１段目の第２４列目、第２段目の第１列目および第３段目の第２４列目のトランジスタ３１Ｐ又は３２ＰのソースとなるＰ型拡散層４３Ｐは行毎に金属配線４５ＰＢにより電気的に共通接続（●印で図示する）され階調電圧発生回路から各正極性階調電圧ＶＰ３３〜ＶＰ６４がそれぞれ１階調づつ供給されるようになっている。各第１２列目および第１３列目のトランジスタ３１Ｐ又は３２ＰのドレインとなるＰ型拡散層４３Ｐは列毎にポリシリコンおよび金属または金属からなる配線４６Ｐにより電気的に共通接続（■印で図示する）され後段回路に正極性階調電圧ＶＰ１ 〜ＶＰ６４のうち表示データに対応する１階調の階調電圧が出力されるようになっている。ＮＲＯＭデコーダ５１６ＮはＮウェル４２にチップ長尺方向（図面で左側）に隣接してＰ型半導体基板４１内に、３２行２４列のマトリックス配置されたトランジスタ３１Ｎ，３２ＮのソースおよびドレインとなるＮ型拡散層４３Ｎと、各段２４本のゲート列３４ＮＡａ，３４ＮＡｂ，３４ＮＢａ，３４ＮＢｂとなるゲート配線４４Ｎとを３段分含んで構成されている。ゲート配線４４Ｎは各段それぞれ、第ｉ（ｉ＝１，２，…，１２）列目と第（２５−ｉ）列目とのゲート列を共通接続している。第１段目の第１列目、第２段目の第２４列目および第３段目の第１列目のトランジスタ３１Ｎ又は３２ＮのドレインとなるＮ型拡散層４３Ｎは行毎に金属配線４５ＮＡにより電気的に共通接続（●印で図示する）され階調電圧発生回路から各負極性階調電圧ＶＮ１ 〜ＶＮ３２がそれぞれ１階調づつ供給されるようになっている。第１段目の第２４列目、第２段目の第１列目および第３段目の第２４列目のトランジスタ３１Ｎ又は３２ＮのドレインとなるＮ型拡散層４３Ｎは行毎に金属配線４５ＮＢにより電気的に共通接続（●印で図示する）され階調電圧発生回路から各負極性階調電圧ＶＮ３３〜ＶＮ６４がそれぞれ１階調づつ供給されるようになっている。各第１２列目および第１３列目のトランジスタ３１Ｎ又は３２ＮのソースとなるＮ型拡散層４３Ｎは列毎にポリシリコンおよび金属または金属からなる配線４６Ｎにより電気的に共通接続（■印で図示する）され後段回路に負極性階調電圧ＶＮ１ 〜ＶＮ６４のうち表示データに対応する１階調の負極性階調電圧が出力されるようになっている。Ｐ型拡散層４３ＰとＮ型拡散層４３Ｎはチップ短尺方向に互いに半ピッチずらして配置にしている。回路ブロック５０３ｂの場合は、図５とは逆に３段を一まとめにしたＰＲＯＭデコーダ５１６Ｐが３段を一まとめにしたＮＲＯＭデコーダ５１６Ｎにチップ長尺方向（図面で左側）に隣接して図５と同様の構成で配置されている。尚、隣接する回路ブロック５０３ａと回路ブロック５０３ｂはＰＲＯＭデコーダ５１６ＰとＮＲＯＭデコーダ５１６Ｎとがミラー配置されているため両者間でＰＲＯＭデコーダ５１６Ｐ同士の隣接配置とＮＲＯＭデコーダ５１６Ｎ同士の隣接配置が交互に生じるが、このＰＲＯＭデコーダ５１６Ｐ同士の隣接配置は回路ブロック５０３ａのＮウェル４２と回路ブロック５０３ｂのＮウェル４２とを１つに一体化して行っている。
【００２４】
以上のように、半導体チップ５０１上の内部回路５０２として６個の出力を有する回路ブロック５０３をチップ長尺方向に６４段配置し、各回路ブロック５０３単位にＰＲＯＭデコーダ５１６Ｐの３段をチップ長尺方向に隣接して一まとめにすると共に、ＮＲＯＭデコーダ５１６Ｎの３段をチップ長尺方向に隣接して一まとめにしＰＲＯＭデコーダ５１６Ｐにチップ長尺方向に隣接配置することにより、ＮＲＯＭデコーダ５１６ＮとＰＲＯＭデコーダ５１６Ｐとの隣接個所は各回路ブロック５０３内で１個所となり、また隣接する回路ブロック５０３間でＰＲＯＭデコーダ５１６ＰとＮＲＯＭデコーダ５１６Ｎとがミラー配置されているために回路ブロック５０３間にはＮＲＯＭデコーダ５１６ＮとＰＲＯＭデコーダ５１６Ｐとの隣接個所は発生せず、Ｎ型拡散層４３ＮとＮウェル４２との全離間距離が減少し、Ｄ／Ａコンバータ５１６のチップ長尺方向の寸法を小さくすることができる。従来の３８４本出力の半導体チップ５０１の場合、ＮＲＯＭデコーダ３１６ＮとＰＲＯＭデコーダ３１６Ｐとの隣接個所は３８３個所あり、Ｎ型拡散層１３ＮとＮウェル１２との全離間距離を３８３×５０μｍ≒１９ｍｍ必要とするのに対して、本実施例の半導体チップ５０１ではＮＲＯＭデコーダ５１６ＮとＰＲＯＭデコーダ５１６Ｐとの隣接個所は回路ブロック５０３内の１個所×６４＝６４個所で、Ｎ型拡散層４３ＮとＮウェル４２との全離間距離は６４×５０μｍ≒３ｍｍとなり、全離間距離は約８０％低減されることになる。また、従来の集積回路装置ではＰＲＯＭデコーダ３１６ＰおよびＮＲＯＭデコーダ３１６Ｎの各段のトランジスタを６４行と１２列のマトリックス配置としていたのを、本実施例の集積回路装置ではＰＲＯＭデコーダ５１６ＰおよびＮＲＯＭデコーダ５１６Ｎの各段のトランジスタを３２行と２４列のマトリックス配置とし、チップ長尺方向には、１２列から２４列とトランジスタの配置が２倍に増加する分の領域は上記のＮ型拡散層４３ＮとＮウェル４２との全離間距離の減少分でほぼ又は完全に吸収し、チップ短尺方向には、６４行から３２行とトランジスタの配置が半分に減少し、半導体チップ５０１の長尺方向の寸法をほぼ又は全く増加させずに短尺方向の寸法を縮小することができる。例えば、トランジスタ３１Ｐ，３２Ｐ，３１Ｎ，３２Ｎのチップ長尺方向のセルピッチを５μｍとすると従来の６４行×５μｍ＝３２０μｍから３２行×５μｍ＝１６０μｍと１６０μｍ縮小することができる。尚、ＲＯＭデコーダ５１６Ｐ，５１６Ｎの各段のチップ長尺方向の寸法は逆に２倍になるが、上述したように、ＮＲＯＭデコーダ５１６ＮとＰＲＯＭデコーダ５１６Ｐとの隣接個所の低減によりチップ長尺方向の寸法をほとんど増加させずに吸収することができる。従って、従来の半導体チップ１の短尺方向の寸法を例えば、１．５ｍｍとすると半導体チップ４１の短尺方向の寸法およびチップ面積を１０％程度縮小できる。
【００２５】
尚、上記実施例において、図３に示すＰＲＯＭデコーダは、ゲート列を２倍に展開したとき第１２列目のゲート列３４ＰＡｂおよび第１４列のゲート列３４ＰＢａは表１に示すようにすべてデプレッション形トランジスタ３２Ｐであるためこれらのゲート列３４ＰＡｂ，３４ＰＢａにはデータ信号を入力する必要がないためこれらのゲート列３４ＰＡｂ，３４ＰＢａを省略することができ、図４に示すように第１および第２分割ＰＲＯＭデコーダ６１６ＰＡ，６１６ＰＢは、行毎にエンハンスメント形トランジスタ３１Ｐとデプレッション形トランジスタ３２Ｐとの２個を１対とする５対と単独のエンハンスメント形トランジスタ３１Ｐとをソースとドレインとで接続した３２個のトランジスタ直列回路５３ＰＡ，５３ＰＢを有し、各対の一方のトランジスタ３１Ｐ，３２Ｐのゲートが列毎に共通接続された一方のゲート列３４ＰＡａ，３４ＰＢａと各対の他方のトランジスタ３１Ｐ，３２Ｐのゲートが列毎に共通接続された他方のゲート列３４ＰＡｂ，３４ＰＢｂとからなるゲート列対３４ＰＡ，３４ＰＢと、単独のエンハンスメント形トランジスタ３１Ｐのゲートが列に共通接続された単独のゲート列５４ＰＡａ，５４ＰＢｂとを有し、各トランジスタ直列回路５３ＰＡ，５３ＰＢの一端は正極性階調電圧ＶＰ１ 〜ＶＰ３２，ＶＰ３３〜ＶＰ６４が接続され、各トランジスタ直列回路５３ＰＡ，５３ＰＢの各他端は共通接続されて後段回路に接続されると共に、一方のゲート列３４ＰＡａ，３４ＰＢａおよび第１分割ＰＲＯＭデコーダ６１６ＰＡの単独のゲート列５３ＰＡａが表示データの正相ＤＰ１，ＤＰ２，…，ＤＰ６に接続され他方のゲート列３４ＰＡｂ，３４ＰＢｂおよび第２分割ＰＲＯＭデコーダ６１６ＰＢｂの単独のゲート列５４ＰＢｂが表示データの逆相ＤＰ１バー，ＤＰ２バー，…，ＤＰ６バーに接続される構成となり、トランジスタ２列分の幅を小さくすることができ、図３のＰＲＯＭデコーダ５１６ＰよりさらにＰＲＯＭデコーダのチップ長尺方向の寸法を縮小できる。ＮＲＯＭデコーダ５１６Ｎについても同様にゲート列２列分を減らすことができるが説明を省略する。
【００２６】
また、上記実施例では、一導電型としてＰ型、他導電型としてＮ型、一極性として正極性、および他極性として負極性で説明したが、一導電型としてＮ型、他導電型としてＰ型、一極性として負極性、および他極性として正極性であってもよい。
また、上記実施例では、奇数段目の回路ブロックと偶数段目の回路ブロックとでＰＲＯＭデコーダとＮＲＯＭデコーダとの配置をミラー配置として説明したが、同一配置でもよい。この場合、上記実施例のように回路ブロックの出力数が６個と少なく、回路ブロックが６４段と多いと回路ブロック間のＰＲＯＭデコーダとＮＲＯＭデコーダとの隣接個所が増加するので、例えば、回路ブロックの出力数が９６出力と多く、回路ブロックが４段と少ない場合に適用するとよい。
また、上記実施例では、１個の階調電圧発生回路で正極性階調電圧および負極性階調電圧を供給するために正極性階調電圧を供給する金属配線がＮＲＯＭデコーダ上を介して、また負極性階調電圧を供給する金属配線がＰＲＯＭデコーダ上を介して配置されているが、回路ブロック内のＰＲＯＭデコーダとＮＲＯＭデコーダ間、又は、回路ブロック間に階調電圧発生回路を配置して正極性階調電圧を供給する金属配線はＮＲＯＭデコーダ上を介さずに、負極性階調電圧を供給する金属配線はＰＲＯＭデコーダ上を介さずに配置することもできる。この場合、上記実施例のように回路ブロックの出力数が６個と少なく、回路ブロックが６４段と多いと階調電圧発生回路の個数が増加するので、例えば、回路ブロックの出力数が９６出力と多く、回路ブロックが４段と少ない場合に適用するとよい。この場合、ＰＲＯＭデコーダのＰ型拡散層とＮＲＯＭデコーダのＮ型拡散層との配置関係は規制されることなく、チップ短尺方向のトランジスタのセルピッチも金属配線により規制されることがなくなる。
【００２７】
【発明の効果】
本発明によれば、半導体チップ上の内部回路としてＬ個の出力を有する回路ブロックをチップ長尺方向にＭ段配置し、各回路ブロック単位に一導電型ＲＯＭデコーダの（Ｌ／２）段をチップ長尺方向に隣接して一まとめにすると共に、他導電型ＲＯＭデコーダの（Ｌ／２）段をチップ長尺方向に隣接して一まとめにし一導電型ＲＯＭデコーダにチップ長尺方向に隣接配置したうえで、各ＲＯＭデコーダのゲート列を横方向に２倍に展開することにより、ゲート列を横方向に２倍に展開した分の寸法を一導電型ＲＯＭデコーダと他導電型ＲＯＭデコーダの隣接個所が減少した分で吸収して半導体チップの長尺方向の寸法をほとんどまたは全く増加させずにＲＯＭデコーダの行数を半減することができ、半導体チップの短尺方向の寸法を縮小し、かつチップ面積も縮小した集積回路装置およびそれを用いた液晶表示装置を提供することができる。また、ＲＯＭデコーダのゲート列を横方向に展開することによりデプレッション形トランジスタのみで構成されるゲート列を省略することにより、さらに、ＲＯＭデコーダのゲート列を横方向に展開した分の寸法を一導電型ＲＯＭデコーダと他導電型ＲＯＭデコーダの隣接個所が減少した分で吸収しやすくなる。
【図面の簡単な説明】
【図１】本発明の１実施例である集積回路装置としての半導体チップの概略平面図。
【図２】図１の半導体チップに配置された回路ブロックの概略構成図。
【図３】図２の回路ブロックのＤ／Ａコンバータに含まれる１実施例のＰＲＯＭデコーダの回路図。
【図４】図２の回路ブロックのＤ／Ａコンバータに含まれる他の実施例のＰＲＯＭデコーダの回路図。
【図５】図２の回路ブロックのＤ／Ａコンバータに含まれるＰＲＯＭデコーダとＮＲＯＭデコーダの半導体チップ上での概略平面パターン図。
【図６】従来の集積回路装置としての半導体チップの概略平面図。
【図７】図６の半導体チップに配置された回路ブロックの概略構成図。
【図８】図７の回路ブロックのＤ／Ａコンバータに含まれるＰＲＯＭデコーダの回路図。
【図９】図７の回路ブロックのＤ／Ａコンバータに含まれるＮＲＯＭデコーダの回路図。
【図１０】図７の回路ブロックのＤ／Ａコンバータに含まれるＰＲＯＭデコーダとＮＲＯＭデコーダの半導体チップ上での概略平面パターン図。
【図１１】液晶表示モジュールの概略構造図。
【図１２】図１１の液晶表示モジュールの水平ドライバの概略構成を示すブロック図。
【符号の説明】
３１Ｐ Ｐチャネルエンハンスメント形トランジスタ
３１Ｎ Ｎチャネルエンハンスメント形トランジスタ
３２Ｐ Ｐチャネルデプレッション形トランジスタ
３２Ｎ Ｎチャネルデプレッション形トランジスタ
３３ＰＡ，３３ＰＢ、５３ＰＡ，５３ＰＢ トランジスタ直列回路
３４ＰＡ，３４ＰＢ ゲート列対
３４ＰＡａ，３４ＰＡｂ，３４ＰＢａ，３４ＰＢｂ，５４ＰＡａ，５４ＰＢｂゲート列
４１ 半導体基板
４２ Ｎウェル
４３Ｎ Ｎ型拡散層
４３Ｐ Ｐ型拡散層
５０１ 半導体チップ
５０２ 内部回路
５０３ 回路ブロック
５１１ シフトレジスタ
５１２ データレジスタ
５１３ 第１切り替えスイッチ
５１４ ラッチ
５１５ レベルシフタ
５１６ Ｄ／Ａコンバータ
５１６Ｐ ＰＲＯＭデコーダ
５１６Ｎ ＮＲＯＭデコーダ
５１６ＰＡ，５１６ＮＡ，６１６ＰＡ，６１６ＮＡ 第１分割ＲＯＭデコーダ
５１６ＰＢ，５１６ＮＢ，６１６ＰＢ，６１６ＮＢ 第２分割ＲＯＭデコーダ
５１７ 第２切り替えスイッチ
５１８ ボルテージフォロア出力回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit device having a ROM decoder and an active matrix type liquid crystal display device using the same.
[0002]
[Prior art]
As shown in FIG. 11, the liquid crystal display module of the active matrix type dot inversion driving type liquid crystal display device includes a liquid crystal panel 100 and a driving device 200 arranged on the outer periphery of the liquid crystal panel 100. The liquid crystal panel 100 is composed of two glass substrates arranged to face each other with a liquid crystal interposed therebetween. A TFT (thin film transistor) and a pixel electrode are formed on a rear substrate, and a common electrode and a color filter are formed on a front substrate. Have been. TFTs and pixel electrodes are formed in a matrix on the rear substrate, and these TFTs and pixel electrodes extend in the horizontal direction, and gate lines arranged in a vertical direction. The data lines arranged side by side are connected. The driving device 200 includes a vertical driver 210 connected to a gate line, and a horizontal driver 220 connected to a data line. When a scanning signal is supplied to a certain gate line from the vertical driver 210, a TFT connected to the gate line is turned on, and a display data signal supplied to the data line from the horizontal driver 220 is transmitted through the turned-on TFT. Then, an electric field is applied to the liquid crystal between the pixel electrode and the common electrode to cause an optical change to perform display.
[0003]
Each driver 210, 220 is mounted on a module, for example, in the case of XGA (1024 × 768 pixels) display.
{Circle around (1)} The horizontal driver 220 needs to drive 1024 × 3 = 3072 data lines because data lines for R (red), G (green) and B (blue) are required. Eight horizontal drivers 220 having the same driving capacity are arranged on the upper outer periphery of the liquid crystal panel 100 by cascade connection on one side.
{Circle around (2)} The vertical driver 210 needs to drive 768 gate lines. For example, four vertical drivers 210 having a driving capability of 192 are arranged on the left outer periphery of the liquid crystal panel 100 in one side in a cascade connection. .
The drivers 210 and 220 are each composed of an integrated circuit device composed of a long rectangular semiconductor chip. The integrated circuit device is mounted on a module by mounting each integrated circuit device on a TCP (tape carrier package) and using a liquid crystal display. The semiconductor chip is arranged in parallel on the corresponding side of the panel 100 on the long side of the semiconductor chip.
[0004]
The invention of the present application relates to the horizontal driver 220 among the drivers 210 and 220. Hereinafter, a schematic configuration of the horizontal driver 220 will be described with reference to FIG. The horizontal driver 220 supplies 6-bit display data for each color of R, G, and B as display data, thereby converting the negative and positive gray scale voltages of 64 gray scales into odd and even data lines as negative and positive drive voltages. The polarity of the line is different from that of the line, and the data is output alternately every one horizontal period. As a main circuit, a shift register 221, a data register 222, a latch 223, a level shifter 224, a D / A converter 225, and a voltage follower output circuit 226 are provided. have. The shift register 221 is, for example, 64-bit bidirectional and selects right shift start pulse input / output or left shift start pulse input / output by shift direction switching input, and reads the H level of the start pulse at the edge of the clock input. Control signals for data capture are sequentially generated and output to the data register 222. The data register 222 sequentially reads 6-bit display data every six stages based on a control signal from each stage of the shift register 221, and the latch 223 reads the display data read into the data register 222 at the edge of the latch input, and switches the level shifter 224 to the level shifter 224. The output is collectively output to the D / A converter 225 every horizontal period. The D / A converter 225 receives one of the 64 grayscale negative and positive grayscale voltages generated by the internal grayscale voltage generation circuit by the gamma correction power supply input based on the display data corresponding to each output. , And alternately output each data line as a negative and positive drive voltage via a voltage follower output circuit 226 such that the odd and even lines have different polarities every horizontal period. .
[0005]
Next, a conventional integrated circuit device mounted on a TCP as the horizontal driver 220 will be described with reference to FIG. 6 as having a driving capability for 384 data lines. In the figure, reference numeral 301 denotes a long rectangular semiconductor chip, and the circuit of the above-described horizontal driver 220 is arranged as an internal circuit 302 at the center of the semiconductor chip 301 along the long side. Although not shown, an output pad corresponding to 384 data lines is provided on an outer peripheral portion, which is arranged on the liquid crystal panel side, of both outer peripheral portions along the long side.Internal circuit 302And input pads for start pulse input / output, shift direction switching input, clock input, data input, latch input, etc., and power supply pads for positive power supply, negative power supply, and γ correction power supply. Are connected to the internal circuit 302 and disposed. A part of the output pad may be arranged on the short side or the long side on the input side in addition to the long side on the liquid crystal panel side.
[0006]
Next, the internal circuit 302 will be described with reference to FIG. For the sake of simplicity, only those having six outputs are illustrated and described, and illustration of a common circuit such as a gradation voltage generation circuit and external power supply inputs and signal inputs is omitted. The internal circuit 302 includes a one-stage (64-stage in the case of 384 output) shift register 311 in which one stage corresponds to six outputs, and a six-stage (384-stage in the case of 384 output) data register corresponding to six outputs. 312, a first switch 313 having three stages (192 stages for 384 outputs) of two-input / two-output switches, and a latch 314 having six stages (384 stages for 384 outputs) corresponding to six outputs And a 6-stage (384-stage in the case of 384 output) level shifter 315 corresponding to the 6 outputs, an NROM decoder 316N in a 3-stage (192 stage in the case of 384 output), and a 3-stage (192 stage in the case of 384 output) ) PROM decoder 316P and the D / A converter 316 alternately arranged one by one in the longitudinal direction of the semiconductor chip 301, and a three-stage (38 input / output) switch. The second changeover switch 317 having 192 stages in the case of output, and the voltage follower output circuit 318 having six stages (384 stages in the case of 384 outputs) corresponding to the six outputs are connected to the semiconductor chip 301 by the voltage follower output circuit 318. A line 321 is connected between the shift register 311 and the data register 312, a line 322 is connected between the data register 312 and the first switch 313, and a first switch The wiring 323 between the latch 313 and the latch 314, the wiring 324 between the latch 314 and the level shifter 315, the wiring 325 between the level shifter 315 and the D / A converter 316, and the wiring 326 between the D / A converter 316 and the second switch 317. , Second changeover switch 317 and voltage follower output circuit Between 18 are connected by the wiring 327.
[0007]
The operation of the internal circuit 302 is as follows. When, for example, right shift start pulse input / output is selected by the shift direction switching input in the shift register 311, the shift register 311 is supplied with the start pulse H at the edge of the clock input every one horizontal period. The level is read and output as a right shift start pulse to the internal circuit 302 of the next stage, and a control signal for data capture is output to the first to sixth stages of the data register 312. The data register 312 takes in 6-bit display data in each of the first to sixth stages according to the control signal of the shift register 311 every horizontal period, and the i-th (i = i) The display data taken in the (1,3,5) stage is output to one input side of two inputs of the (i + 1) / 2-th stage of the first changeover switch 313, and is outputted to the even stage of the data register 312. The display data captured at a certain (i + 1) th stage is output to the other input side of the two inputs of the (i + 1) / 2th stage of the first changeover switch 313. The first change-over switch 313 converts the display data supplied to one input side and the other input side of the two inputs of the (i + 1) / 2-th stage every one horizontal period into the i-th stage and the (i + 1) -th stage of the latch 314. The eyes alternately output. The latch 314 converts the display data supplied to the i-th stage and the (i + 1) -th stage every horizontal period into the NROM decoder 316N and the PROM decoder inside the D / A converter 316 via the level shifter 315 at the edge of the latch input. The output is collectively output to each (i + 1) / 2-th stage of 316P. The D / A converter 316 converts one negative gradation voltage out of 64 gradations into a second changeover switch 317 based on the display data supplied to the first to third stages of the internal NROM decoder 316N. One of the two inputs of the (i + 1) / 2-th stage is output to one input side, and based on the display data supplied to the (i + 1) / 2-th stage of the internal PROM decoder 316P, out of 64 gradationsOne-tone positive gradation voltageIs output to the other input side of the two inputs of the (i + 1) / 2-th stage of the second changeover switch 317. The second changeover switch 317 converts the negative gradation voltage supplied to one input side of the (i + 1) / 2th stage and the positive gradation voltage supplied to the other input side into an odd number of the voltage follower output circuit 318. The i-th stage, which is the stage, and the (i + 1) -th stage, which is the even-numbered stage, have different polarities, and are alternately output for each horizontal period. The voltage follower output circuit 318 controls the negative gray scale voltage and the positive gray scale voltage supplied to each of the first to sixth stages so that the polarities of the odd-numbered stages and the even-numbered stages are different from each other. The data is alternately output to the odd data lines and the even data lines for each period.
[0008]
Next, a circuit configuration of the PROM decoder 316P and the NROM decoder 316N included in the D / A converter 316 will be described. As shown in FIG. 8, the PROM decoder 316P has a P-channel enhancement type transistor 1P and a P-channel depletion type transistor 2P (always on) in a matrix at predetermined positions in 64 rows and 12 columns. Each row is a transistor 1P and a transistor 2P (always on) which are connected in series by the drain of the transistor 1P and the source of the transistor 2P or the source of the transistor 1P and the drain of the transistor 2P. This constitutes a series circuit 3P. Each pair in each row constitutes a gate column pair 4P with a gate column 4Pa in which one gate of each pair of transistors is commonly connected in each column and a gate column 4Pb in which the other gate is commonly connected in each column. I have. To the sources of the transistors 1P or 2P in the first column at one end of each transistor series circuit 3P, positive gradation voltages VP1 to VP64 of 64 gradations are supplied one by one from a gradation voltage generation circuit (not shown). Is done. Each gate row pair 4P hasLevel shifter 315, DP6 corresponding to the data lines of the liquid crystal display panel are supplied to the gate row 4Pa in the normal phase DP1, DP2,..., DP6, and the negative row DP1, bar, DP2 are supplied to the gate row 4Pb. , ..., DP6 bar. The drains of the transistors 1P or 2P in the twelfth column at the other end of each transistor series circuit 3P are connected in common, and the second switch 317 at the subsequent stage corresponds to the display data among the positive gradation voltages VP1 to VP64. One gradation voltage is output.
[0009]
As shown in FIG. 9, the NROM decoder 316N has an N-channel enhancement type transistor 1N and an N-channel depletion type transistor 2N (always on) in a matrix at predetermined positions in 64 rows and 12 columns. In each row, a transistor 1N and a transistor 2N (always on) are connected in series with a drain of the transistor 1N and a source of the transistor 2N or a source connected to the source of the transistor 1N and a drain of the transistor 2N. A series circuit 3N is configured. Each pair in each row constitutes a gate column pair 4N by a gate column 4Na in which one gate of each pair of transistors is commonly connected in each column and a gate column 4Nb in which the other gate is commonly connected in each column. I have. eachTransistor series circuit 3NTo the drains of the transistors 1N or 2N in the first column on one end side, negative gradation voltages VN1 to VN64 of 64 gradations are supplied one by one from a gradation voltage generation circuit (not shown). Each gate row pair 4N hasLevel shifter 315, DN6 corresponding to the data lines of the liquid crystal display panel are supplied to the gate row 4Na in the normal phase DN1, DN2,..., DN6 and the gate row 4Nb to the negative phase DN1, , DN6 bar. The drains of the transistors 1N or 2N in the twelfth column on the other end side of each transistor series circuit 3N are commonly connected, and the second switch 317 at the subsequent stage corresponds to the display data among the negative gradation voltages VN1 to VN64. One gradation voltage is output.
[0010]
The operation of the PROM decoder 316P and the NROM decoder 316N having the above configurations will be described. The grayscale voltages VP1 to VP64 and VN1 to VN64 of 64 gray scales are applied to the sources of the transistors 1P, 1N or 2P, 2N in the first column at one end of each of the transistor series circuits 3P, 3N. In this state, the predetermined data signals DP1, DP2,..., DP6, DN1, DN2,..., DN6 of “H (high level)” or “L” are applied to the gate arrays 4P, 4N respectively. , DP6, DN1, DN2,..., And DN6, and are supplied to the gate rows 4Pb and 4Nb in opposite phases DP1, DP2,..., DP6, DN1, and DN2,. When supplied, all of the transistors 1P and 1N of one of the transistor series circuits 3P and 3N selected from among the transistor series circuits 3P and 3N are turned on (the transistors 2P and 2N are always on), and the transistor series circuit is turned on. The gray scale voltages applied to 3P and 3N are extracted.
[0011]
As shown in FIG. 10, the pattern arrangement of the PROM decoder 316P and the NROM decoder 316N having the above circuit configuration on the semiconductor chip 301 is such that the three-stage PROM decoder 316P and the three-stage NROM decoder 316N extend in the longitudinal direction of the semiconductor chip 301. They are arranged alternately one by one. Each PROM decoder 316P has a P-type diffusion layer 13P serving as a source and a drain of transistors 1P and 2P arranged in a matrix of 64 rows and 12 columns in an N-well 12 arranged on a P-type semiconductor substrate 11, and six pairs of gates. And a gate wiring 14P forming a column pair 4P. The P-type diffusion layer 13P serving as a source of the transistor 1P or 2P in each first column is electrically connected in common (shown by a black circle) by a metal wiring 15P for each row, and is supplied from the gray scale voltage generation circuit to each positive polarity transistor. The adjustment voltages VP1 to VP64 are supplied for each gradation. The P-type diffusion layer 13P serving as the drain of the transistor 1P or 2P in each twelfth column is electrically connected (shown by the symbol ■) by the metal wiring 16P for each column, and is connected to the subsequent circuit by the positive gradation voltages VP1 to VP1. One gradation voltage corresponding to the display data among the VP64 is output. Each NROM decoder 316N includes an N-type diffusion layer 13N serving as a source and a drain of transistors 1N and 2N arranged in a matrix of 64 rows and 12 columns in the P-type semiconductor substrate 11 adjacent to the N-well 12 in the chip length direction. , And 6N gate line pairs 4N. The N-type diffusion layer 13N serving as the drain of the transistor 1N or 2N in each first column is electrically connected in common (illustrated by a black circle) by a metal wiring 15N for each row, and is supplied from the grayscale voltage generation circuit to each negative polarity transistor. The adjustment voltages VN1 to VN64 are supplied for each gray scale. The N-type diffusion layer 13N serving as the drain of the transistor 1N or 2N in each twelfth column is electrically connected in common (shown by the symbol ■) by the metal wiring 16N for each column, and is connected to the subsequent circuit by the negative gray scale voltage VN1. One gradation voltage corresponding to the display data in VN64 is output. The P-type diffusion layer 13P and the N-type diffusion layer 13N are arranged so as to be shifted from each other by a half pitch in the chip short direction. In the above pattern arrangement, for example, the wiring pitch of the gate wirings 14P and 14N is about 2 μm, and the metal wirings 15P and 15N are about 5 μm. Also adjacentROM decoders 316P, 316NAtROM decoderIn order to separate them, a distance of about 50 μm is provided between the N well 12 and the N diffusion layer 13N.
[0012]
[Problems to be solved by the invention]
In the liquid crystal display module, a driver is arranged in a peripheral portion (frame) other than the display area, and in order to reduce the size of the liquid crystal display device, it is necessary to make the peripheral portion as small as possible. One means for minimizing this peripheral portion is to reduce the short dimension of the semiconductor chip constituting the driver. Further, in order to reduce the manufacturing cost of the semiconductor chip, it is necessary to reduce the chip area, that is, the dimension of the semiconductor chip in the longitudinal direction and / or the short direction. By the way, the longitudinal dimension of a semiconductor chip is regulated by the pitch of output pads arranged on the outer peripheral portion of the semiconductor chip. If the output pad pitch remains the same as the conventional design standard, the chip area is reduced. In addition, it is necessary to reduce the short dimension of the semiconductor chip. In the integrated circuit device having the above configuration, the PROM decoder 316P and the NROM decoder 316N included in the D / A converter 316 in the internal circuit 302 are configured by arranging transistors in a matrix of 64 rows and 12 columns. As the arrangement of the transistors in the 316P and the NROM decoder 316N, it is sufficient to secure 12 columns of transistors × about 2 μm = about 24 μm in the chip long direction, but 64 transistors × 5 μm = 320 μm in the chip short direction. Must be secured. In recent years, there has been a demand for a higher bit rate for the horizontal driver in order to improve the image quality of the liquid crystal panel. Output gray scale voltage,ROM decoder chip short directionIn this case, there is a problem that 256 rows of transistors must be secured, and the ratio of the chip to the dimension in the short direction is further increased. In the chip length direction,ROM decoderA separation distance of about 50 μm is provided between the N well 12 and the N diffusion layer 13N between the N well 12 and the N diffusion layer 13N.
The present invention has been made in view of the above problems, and an internal circuit on a semiconductor chip is configured by M stages of circuit blocks having L outputs, andCircuit blockThe L / 2-stage one-conductivity-type ROM decoders are arranged adjacently and collectively, and the L / 2-stage other-conductivity-type ROM decoders are arranged adjacently and collectively and arranged adjacent to the one-conductivity-type ROM decoder. Thus, the adjacent portion between the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder is made one in each circuit block to reduce an extra area in the chip length direction, and to reduce the extra area in the chip length direction. An integrated circuit device in which the length of the semiconductor chip in the short direction is reduced and the chip area is reduced by halving the gate row of each ROM decoder twice and storing the ROM decoder in half in the chip short direction. And a liquid crystal display device using the same.
[0013]
[Means for Solving the Problems]
(1) An integrated circuit device according to the present invention includes a circuit block having L (even number) outputs formed of a long rectangular semiconductor chip.In the longitudinal direction ofM-stage arrangement,(L / 2) stages are arranged in a circuit block adjacent to each other in the chip length direction and output one polarity gradation voltage from each stage; and (L / 2) stages Are arranged together adjacently in the chip lengthwise direction, and the other conductivity type ROM decoder which outputs the other polarity gradation voltage from each stage is arranged adjacently in the chip lengthwise direction. The polarity of the second output and that of the even output are different.An integrated circuit device that outputs alternately,Each stage of the one-conductivity-type ROM decoder is supplied with a unipolar gradation voltage of (2 n) gradations and receives one of two (2 n) gradations based on n-bit display data. A polarity gradation voltage is output, and each stage of the other conductivity type ROM decoder is supplied with a (2 n) gradation other polarity gradation voltage and receives (2 n) gradation based on n-bit display data. , And outputs one-polarity gray-scale voltage, and each stage of the one-conductivity ROM decoder supplies one-polarity gray-scale voltage to which half of (2 n) gray-scales are supplied. Divided ROM decoder and a one-conductivity-type second divided ROM decoder to which a unipolar gradation voltage of the other half of (2 n) gradations is supplied. , And each stage of the other-conductivity-type ROM decoder is supplied with a half-polarity gray-scale voltage of half of (2 n) gray-scales. Divided into a first divided ROM decoder of another conductivity type and a second divided ROM decoder of another conductivity type supplied with the other polarity gradation voltage of the other half of (2 n) gradations, respectively. Are juxtaposed in the chip length direction.
According to this means, an increase in the arrangement dimension in the chip long direction by juxtaposing the first divided ROM decoder and the second divided ROM decoder in the chip long direction can be realized by the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder. The adjoining location is set as one location in each circuit block, thereby absorbing as much as possible and increasing the length of the semiconductor chip in the longitudinal direction as much as possible. It can be.
(2) In the integrated circuit device of the present invention, in the above (1), the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder are mirror-arranged in circuit blocks adjacent to each circuit block.
According to this means, in the above (1), there is no adjacent portion between the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder between the adjacent circuit blocks, so that only one portion in each circuit block can be provided. It is easier to absorb an increase in the arrangement size in the chip long direction due to juxtaposition of the first divided ROM decoder and the second divided ROM decoder in the chip long direction than the mirror arrangement.
(3) In the integrated circuit device of the present invention, in the above (1), each stage of the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder includes an enhancement-type transistor and a depletion-type transistor of the respective conductivity type.Is a pair of (2 to the (n-1) th power) rows of 2n pairs of transistors.A matrix arrangement of (2 to the power of (n-1)) rows and 4n columns,Of each conductivity typeThe first divided ROM decoder is arranged in the first to second n-th columns of the matrix arrangement.consists of n pairs of columns,Of each conductivity typeThe second divided ROM decoder is arranged in the (2n + 1) th to 4nth columns of the matrix arrangement.It consists of n pairs of columns.
(4) The integrated circuit device according to (3) above,A first divided ROM decoder of each conductivity type and a second divided ROM decoder;The split ROM decoder is(2 to the power of (n-1)) n pairs of enhancement transistors and depletion transistors in each of the rowsAnd a transistor series circuit connected by a source and a drain,One pair of gates of one pair of transistors connected in common to one pair of gates of one pair of transistors in each of the n pairs of columns and the gates of the other pair of transistors areIt has a gate row pair consisting of the other commonly connected gate row, and one end of each transistor series circuit is connected to a gray scale voltage.EachThe other ends of the transistor series circuits are connected in common and connected to the subsequent stage, and one gate row is connected to the positive phase of the display data and the other gate row is connected to the reverse phase of the display data.
(5) In the integrated circuit device of the present invention, in the above (1), each stage of the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder includes a conduction-type enhancement-type transistor and a depletion-type transistor, respectively.(2 (n-1)) rows and 2 (n-1) pairs of columns, and (2 (n-1) powers) of the enhancement transistors of the respective conductivity types. Of a transistor consisting of two rows and two columnsA matrix arrangement of (2 to the power of (n-1)) rows and 2 (2n-1) columns,Of each conductivity typeThe first divided ROM decoder starts from the first column of the matrix arrangement.The second (n-1) -th column is an (n-1) -th column and the (2n-1) -th column is a single column.,Of each conductivity typeThe second divided ROM decoder is arranged in the second n-th column of the matrix arrangement.And the (n-1) pairs of columns from the (2n + 1) th column to the second (2n-1) th column.
According to this means, in (3), each column of the first and second ROM decoders constituted only by the depression type transistors is omitted, and(3)Rather than placing the first divided ROM decoder and the second divided ROM decoder side by side in the chip length direction, an increase in the arrangement size in the chip length direction can be suppressed.
(6) The integrated circuit device according to the above (5), whereinA first divided ROM decoder of each conductivity type and a second divided ROM decoder;The split ROM decoder isFor each row of (2 to the power of (n-1)), (n-1) pairs of enhancement type transistors and depletion type transistors in columns and one column of enhancement type transistors are provided.Having a transistor series circuit connected by source and drain,(N-1) For each column of the pair, one gate column in which the gates of one pair of transistors in one pair are commonly connected and the gate of the other one column of transistors are connected.A gate row pair consisting of the other commonly connected gate row;One rowEnhancement transistor gateIsAnd one end of each transistor series circuit is connected to a gray scale voltage, and the other end of each transistor series circuit is connected in common and connected to a subsequent stage. The single gate row of the first divided ROM decoder is connected to the normal phase of the display data, and the other gate row and the single gate row of the second divided ROM decoder are connected to the opposite phase of the display data.
(7) The liquid crystal display device of the present invention includes the above (1) to (6).One ofWherein the integrated circuit device is mounted on a tape carrier package for driving data lines of a liquid crystal panel.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an integrated circuit device for a horizontal driver according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5 as an example having a driving capability for 384 data lines S. First, in FIG. 1, reference numeral 501 denotes a long rectangular semiconductor chip. On the semiconductor chip 501, a circuit having the same general configuration as the horizontal driver 220 described with reference to FIG. Have been. Although not shown, output pads corresponding to 384 data lines are connected to the internal circuit 502 and disposed on the outer peripheral portion disposed on the liquid crystal panel side of both outer peripheral portions along the long side. In the section, input pads for start pulse input / output, shift direction switching input, clock input, data input, latch input, etc. and power pads for positive power supply, negative power supply, and γ correction power supply are connected to the internal circuit 502 and arranged. I have. A part of the output pad may be arranged on the short side or the long side on the input side in addition to the long side on the liquid crystal panel side. In the internal circuit 502, circuit blocks 503 having L outputs, for example, 6 outputs, are arranged adjacent to each other in the chip length direction with M stages = S / L = 64 stages in the internal circuit 502, and S = 384 outputs in total. It is constituted so that it may become. The circuit arrangement of the circuit block 503 is partially different between the odd-numbered circuit block 503a and the even-numbered circuit block 503b.
[0015]
Next, the circuit blocks 503a and 503b will be described with reference to FIG. It is to be noted that illustration of a common circuit such as a gradation voltage generation circuit and a power supply input and a signal input from the outside is omitted. Circuit blocks 503a, 503bIs 1One-stage shift register 511 corresponding to six outputsAnd 6Stage data register 512And 2Three-stage first switch 513 with two inputs and two outputsAnd 6Stage Latch 514And 6Step level shifter 515And D /A converter 516And 2Three-stage second switch 517 with two inputs and two outputsAnd 6The voltage follower output circuits 518 of the stages and the voltage follower output circuits 518 are sequentially arranged on the longer side of the semiconductor chip 501 on the liquid crystal panel side.Make up. AndA wire 521 between the shift register 511 and the data register 512, a wire 522 between the data register 512 and the first switch 513, a wire 523 between the first switch 513 and the latch 514, and a wire 523 between the latch 514 and the level shifter 515. The wiring 524, the wiring 525 between the level shifter 515 and the D / A converter 516, the wiring 526 between the D / A converter 516 and the second switch 517, and the wiring 527 between the second switch 517 and the voltage follower output circuit 518. And connected.The shift register 511 generates a control signal for data capture by reading the H level of the start pulse at the edge of the clock input. The data register 512 captures, for example, 6-bit display data as n bits according to the control signal from the shift register 511. The first changeover switch 513 alternately outputs the display data taken in the i-th stage (i = 1, 3, 5) which is an odd-numbered stage and the (i + 1) -th stage which is an even-numbered stage of the data register 512. The latch 514 outputs the display data from the first changeover switch 513 collectively at the edge of the latch input. The level shifter 515 converts the voltage level of the display data from the latch 514 to a level at which the next-stage circuit can be driven. The D / A converter 516 is supplied with a positive polarity gray scale voltage having one polarity of 64 gray scales (2 n) gray scales and receives one of 64 gray scales from each stage based on display data from the level shifter 515. A PROM decoder 516P which is a one-conductivity ROM decoder in which three stages for outputting a positive gradation voltage of the gradation are grouped adjacent to each other in the chip length direction, and a negative gradation which is the other polarity of 64 gradations A voltage is supplied, and three stages for outputting one negative gradation voltage out of 64 gradations from each stage based on the display data from the level shifter 515 are integrated together in the chip lengthwise direction and are of another conductivity type. An NROM decoder 516N, which is a ROM decoder, is arranged adjacent to the semiconductor chip 501 in the longitudinal direction. The second switch 517 alternately outputs the positive and negative gradation voltages from the D / A converter 516 from one output side and the other output side. The voltage follower output circuit 518 outputs the gray scale voltages from one output side and the other output side of the second changeover switch 517 to odd-numbered stages and even-numbered stages, respectively.
[0016]
In the D / A converter 516 of the circuit block 503a, the PROM decoder 516P is arranged on the right side of the NROM decoder 516N as shown in FIG. 2, but in the D / A converter 516 of the circuit block 503b, the PROM decoder 516P is replaced by the NROM decoder 516N. The PROM decoder 516P and the NROM decoder 516N are arranged in a mirror arrangement in the circuit block 503a and the circuit block 503b adjacent to each other on the left side. Therefore, the adjacent arrangement of the PROM decoders 516P and the adjacent arrangement of the NROM decoders 516N alternately occur between the adjacent circuit blocks 503a and 503b.
[0017]
The wiring 521 connects the first to sixth stages of the shift register 511 and the data register 512. The wiring 522 is between the i-th (i = 1, 3, 5) -th stage of the data register 512 and one input side of the (i + 1) / 2-th stage of the first switch 513, and the (i + 1) -th stage of the data register 512. 6) The other input side of the (2) input of the (i + 1) / 2-th stage of the first changeover switch 513 is connected to each of the six stages. The wiring 523 is between the first output of the first switch 513 and the first output of the latch 514, the second output of the second switch 513 and the second output of the latch 514. Between the third stage, one output side of the second output of the third switch of the first changeover switch 513 and the second stage of the latch 514, and the other output side of the second output of the first changeover switch 513 and the latch 514. , The other output side of the second output of the second switch of the first changeover switch 513 and the fourth output of the latch 514, and the other output side of the second output of the third changeover switch 513 And the sixth stage of the latch 514 are connected by six lines. Six wirings 524 connect the j-th stage (j = 1, 2,..., 6) of the latch 514 and the j-th stage of the level shifter 515, respectively. In the case of the circuit block 503a, the wiring 525 is provided between the k-th (k = 1, 2, 3) stage of the level shifter 515, the k-th stage of the NROM decoder 516N, and the (k + 3) -th stage of the level shifter 515 as shown in the figure. The k-th stage of the PROM decoder 516P is connected by twelve lines, and in the case of the circuit block 503b, unlike the drawing, the k-th (k = 1, 2, 3) -th stage of the level shifter 515 and the k-th stage of the PROM decoder 516P are different. Twelve lines are connected between the k-th stage and between the (k + 3) -th stage of the level shifter 515 and the k-th stage of the NROM decoder 516N. In the case of the circuit block 503a, the wiring 526 is connected between the first stage of the NROM decoder 516N and one input side of the two inputs of the first stage of the second switch 517, and the second stage of the NROM decoder 516N as shown in the figure. Between the third stage of the second switch 517 and one input of the second input, between the third stage of the NROM decoder 516N and the second stage of the second input of the second switch 517, the PROM decoder 516P Between the other input side of the first stage and the second input of the second stage of the second switch 517, and the other input of the second stage of the PROM decoder 516P and the first stage of the second stage switch 517 And the other input side of the third stage of the PROM decoder 516P and the second input of the third stage of the second changeover switch 517 are connected by a single line. In this case, different from the figure, between the first stage of the PROM decoder 516P and one input side of the two inputs of the first stage of the second changeover switch 517, the second stage of the PROM decoder 516P and the second changeover switch 517 Between one input side of two inputs of the third stage, between one input side of the third input of the PROM decoder 516P and the second input of the second stage of the second changeover switch 517, and the first stage of the NROM decoder 516N. Between the other input side of the second input of the second switch 517, between the other input side of the second input of the NROM decoder 516N and the first input of the second switch 517N, and the NROM decoder The third input of the third switch 516N and the other input of the second input of the third switch 517 are connected by one. The wiring 527 is provided between the second output of the (i + 1) / 2 (i = 1, 3, 5) th stage of the second changeover switch 517 and the ith stage of the voltage follower output circuit 518, and the second changeover switch. The other output of the (i + 1) / 2-th stage 517 and the (i + 1) -th stage of the voltage follower output circuit 518 are connected by a single line.
[0018]
The operation of the circuit blocks 503a and 503b is such that, for example, when the right shift start pulse input / output is selected by the shift direction switching input in the shift register 511, the start pulse is input to the shift register 511 every horizontal period at the edge of the clock input. Is output as a right shift start pulse of the next-stage circuit blocks 503b and 503a, and a control signal for data acquisition is output from the first stage to the sixth stage of the data register circuit 512. You. The data register 512 fetches 6-bit display data into each of the first to sixth stages according to the control signal of the shift register 511 every horizontal period, and the i-th (i = The display data taken in the (1,3,5) stage is output to one input side of two inputs of the (i + 1) / 2-th stage of the first changeover switch 513, and at the even stage of the data register 512. The display data captured at a certain (i + 1) th stage is output to the other input side of the two inputs of the (i + 1) / 2th stage of the first changeover switch 513. In the circuit block 503a, for example, display data corresponding to the output Si, which is an odd-numbered output, is fetched from the i-th stage, which is an odd-numbered stage of the data register 512, and is output to the output S (i + 1), which is an even-numbered output. Assuming that the corresponding display data is taken from the (i + 1) th stage, which is the even stage of the data register 512, in the circuit block 503b, the display data corresponding to the output Si which is the odd output is stored in the even stage of the data register 512. And the display data corresponding to the output S (i + 1) which is the even-numbered output is taken in from the i-th stage which is the odd-numbered stage of the data register 512. The first changeover switch 513 switches the display data supplied to one input side and the other input side of the two inputs of the first stage alternately in the first stage and the fifth stage of the latch 514 every one horizontal period. The display data supplied to one input side and the other input side of the two inputs of the second stage are alternately applied to the third and fourth stages of the latch 514, and to the two inputs of the third stage. The display data supplied to one input side and the other input side are alternately output to the second and sixth stages of the latch 514, respectively. The latch 514 receives the display data supplied to the k-th (k = 1, 2, 3) -th and (k + 3) -th stages every one horizontal period and outputs the data to the D / A converter 516 via the level shifter 515 at the edge of the latch input. Are collectively output to the k-th stage of the NROM decoder 516N and the PROM decoder 516P inside. Based on the display data supplied to the k-th stage of the internal NROM decoder 516N, the D / A converter 516 changes the negative gradation voltage of one gradation out of the 64 gradations to the first stage and the second stage of the second switch 47. A positive electrode of one gradation out of 64 gradations is output based on the display data supplied to the k-th stage of the internal PROM decoder 516P while being output to one input side of two inputs of the third stage and the second stage. The gray scale voltage is output to the other input side of the second input of the second changeover switch 517, the first input and the third input. The second changeover switch 517 supplies the negative grayscale voltage supplied to one input side of the second input of the (i + 1) / 2 (i = 1, 3, 5) stage and the other input side every horizontal period. The positive polarity gradation voltage thus obtained is output alternately to the i-th stage, which is an odd-numbered stage, and the (i + 1) -th stage, which is an even-numbered stage, of the voltage follower output circuit 518. The voltage follower output circuit 518 controls the negative and positive gray scale voltages supplied to each of the first to sixth stages so that the polarities of the odd and even stages are different from each other, so that one horizontal line is obtained. The data is alternately output to the odd data lines and the even data lines for each period.
[0019]
Hereinafter, an example of one stage of the PROM decoder 516P will be described with reference to FIG. In the figure, one stage of the PROM decoder 516P has a P-channel enhancement type transistor 31P and a P-channel depletion type transistor 32P (always on) in a matrix arrangement of, for example, 32 rows and 24 columns at predetermined positions shown in Table 1. The arrangement of 32 rows and 12 columns from the first column to the twelfth column of the half is the first divided PROM decoder 516PA, and the arrangement of 32 rows and 12 columns from the 13th to the 24th column of the other half is the same. It is a two-part PROM decoder 516PB. In each of the divided PROM decoders 516PA and 516PB, each row includes a pair in which the transistor 31P and the transistor 32P (always on) are connected in series by the drain of the transistor 31P and the source of the transistor 32P or the source of the transistor 31P and the drain of the transistor 32P. 6 are further combined to form the transistor series circuits 33PA and 33PB. In each pair of each row, one gate of each pair of transistors is commonly connected to each column.Gate rows 34PAa, 34PBaAnd the other gate is connected in common for each columnGate row 34PAb, 34PBbAnd constitute a gate row pair 34PA, 34PB. Sources of the transistors 31P or 32P in the first and 24th columns at one end of each of the transistor series circuits 33PA and 33PB are connected to a positive-polarity gradation voltage VP1 to VP32 of 64 gradations from a gradation voltage generation circuit (not shown). , VP33 to VP64 are supplied one gradation at a time. Each gate row pair 34PA, 34PBLevel shifter 5156-bit display data DP1, DP2,..., DP6 corresponding to the data lines of the liquid crystal display panel are supplied to the gate rows 34PAa, 34PBa in the normal phases DP1, DP2,. , And DP6 bar. The drains of the transistors 31P and 32P in the twelfth and thirteenth columns on the other end side of the transistor series circuits 33PA and 33PB are commonly connected,Second changeover switch 517The gray scale voltage of one gray scale corresponding to the display data among the positive gray scale voltages VP1 to VP64 is output.
[0020]
[Table 1]

[0021]
The operation of one stage of the PROM decoder 516P having the above configuration will be described. Positive gradation voltages VP1 to VP32 and VP33 to VP64 of 64 gradations are applied to the sources of the transistors 31P and 32P in the first and 24th columns on one end side of each of the transistor series circuits 33PA and 33PB. In this state, predetermined data signals DP1, DP2,..., DP6 shown in Table 2 of "H (high level)" or "L" are applied to the gate arrays 34PA, 34PB, respectively, and the normal phases DP1, DP2 are applied to the gate arrays 34PAa, 34PBa. ,..., DP6, and supplied to the gate rows 34PAb, 34PBb by the inverse phase DP1, DP2,..., DP6 bar, respectively, one of the transistor series circuits 33PA, 33PB is selected. , 33PB are all turned on (the transistor 32P is always turned on), and the gray scale voltage applied to the transistor series circuits 33PA, 33PB is extracted. Note that the configuration and operation of one stage of the NROM decoder 516N are the same except that the polarity and conductivity type are changed, and thus the description is omitted.
[0022]
[Table 2]

[0023]
Next, the pattern arrangement on the semiconductor chip 501 of the PROM decoder 516P and the NROM decoder 516N of the D / A converter 516 in the circuit block 503a shown in FIG. A PROM decoder 516P is arranged adjacent to the NROM decoder 516N in which three stages are integrated in the chip length direction (the right side in the drawing). The PROM decoder 516P includes a P-type diffusion layer 43P serving as a source and a drain of transistors 31P and 32P arranged in a matrix of 32 rows and 24 columns in an N-well 42 arranged on a P-type semiconductor substrate 41, and 24 P-type diffusion layers in each stage. The gate lines 44PAa, 34PAb, 34PBa, and 34PBb constitute a gate row 44P for three stages. The gate line 44P commonly connects the i-th (i = 1, 2,..., Twelfth) and (25-i) -th gate columns in each stage. The P-type diffusion layer 43P serving as the source of the transistor 31P or 32P in the first column on the first column in the first stage, the 24th column in the second stage, and the first column in the third stage is connected to the metal wiring 45PA for each row. Are electrically connected in common (indicated by a black circle), and each of the positive polarity gray scale voltages VP1 to VP32 is supplied from the gray scale voltage generation circuit for each gray scale. The P-type diffusion layer 43P serving as the source of the transistor 31P or 32P in the 24th column of the first stage, the first column of the second stage, and the 24th column of the third stage is a metal wiring 45PB for each row. Are electrically connected in common (illustrated by a black circle) so that each of the positive-polarity gray-scale voltages VP33 to VP64 is supplied one by one from the gray-scale voltage generation circuit. The P-type diffusion layer 43P serving as the drain of the transistor 31P or 32P in each of the twelfth and thirteenth columns is electrically commonly connected to each other by a wiring 46P made of polysilicon and metal or metal (indicated by a triangle). ), And outputs a gradation voltage of one gradation corresponding to the display data among the positive polarity gradation voltages VP1 to VP64 to the subsequent stage circuit. The NROM decoder 516N is adjacent to the N-well 42 in the chip longitudinal direction (left side in the drawing) and is formed in the P-type semiconductor substrate 41 in the P-type semiconductor substrate 41 in the form of a source and a drain of the transistors 31N and 32N arranged in a matrix of 32 rows and 24 columns. It is configured to include three stages of the diffusion layer 43N and the gate wiring 44N which becomes 24 gate rows 34NAa, 34NAb, 34NBa, 34NBb in each stage. The gate line 44N commonly connects the i-th (i = 1, 2,..., Twelfth) and (25-i) -th gate columns in each stage. The N-type diffusion layer 43N serving as the drain of the transistor 31N or 32N in the first column of the first stage, the 24th column of the second stage, and the first column of the third stage has a metal wiring 45NA for each row. Are electrically connected in common (illustrated by a black circle) so that each of the negative gradation voltages VN1 to VN32 is supplied from the gradation voltage generation circuit for each gradation. The N-type diffusion layer 43N serving as the drain of the transistor 31N or 32N in the 24th column of the first stage, the first column of the second stage, and the 24th column of the third stage is formed of a metal wiring 45NB for each row. Are electrically connected to each other (shown by a black circle) so that each of the negative gradation voltages VN33 to VN64 is supplied one gradation at a time from the gradation voltage generation circuit. The N-type diffusion layers 43N, which are the sources of the transistors 31N or 32N in the twelfth and thirteenth columns, are electrically connected in common by a wiring 46N made of polysilicon and metal or metal for each column (illustrated by a triangle). ), The negative gradation voltage of one gradation corresponding to the display data among the negative gradation voltages VN1 to VN64 is output to the subsequent stage circuit. The P-type diffusion layer 43P and the N-type diffusion layer 43N are arranged so as to be shifted from each other by a half pitch in the chip short direction. In the case of the circuit block 503b, contrary to FIG. 5, a PROM decoder 516P in which three stages are integrated is adjacent to an NROM decoder 516N in which three stages are integrated in the chip long direction (left side in the drawing). It is arranged in the same configuration as that described above. In the adjacent circuit blocks 503a and 503b, the PROM decoder 516P and the NROM decoder 516N are mirror-arranged, so that the adjacent arrangement of the PROM decoders 516P and the adjacent arrangement of the NROM decoders 516N alternately occur between them. The adjacent arrangement of the PROM decoders 516P is performed by integrating the N well 42 of the circuit block 503a and the N well 42 of the circuit block 503b into one.
[0024]
As described above, 64 stages of circuit blocks 503 having six outputs are arranged in the chip length direction as the internal circuit 502 on the semiconductor chip 501, and three stages of the PROM decoder 516P are provided for each circuit block 503 unit. The NROM decoder 516N and the PROM decoder 516N are grouped adjacent to each other in the direction of the chip and the three stages of the NROM decoder 516N are grouped adjacent to each other in the chip long direction and are arranged adjacent to the PROM decoder 516P in the chip long direction. 516P is located at one place in each circuit block 503, and since the PROM decoder 516P and the NROM decoder 516N are mirrored between the adjacent circuit blocks 503, the NROM decoder 516N is located between the circuit blocks 503. The place adjacent to the PROM decoder 516P is Not raw, whole distance between the N-type diffusion layer 43N and the N-well 42 is reduced, it is possible to reduce the chip long dimension of the D / A converter 516. In the case of the conventional 384-output semiconductor chip 501, there are 383 adjacent locations of the NROM decoder 316N and the PROM decoder 316P, and the total separation distance between the N-type diffusion layer 13N and the N well 12 needs to be 383 × 50 μm ≒ 19 mm. On the other hand, in the semiconductor chip 501 of the present embodiment, the NROM decoder 516N and the PROM decoder 516P are adjacent to one another in the circuit block 503 × 64 = 64, and the N-type diffusion layer 43N and the N-well 42 Is 64 × 50 μm ≒ 3 mm, and the total separation distance is reduced by about 80%. Further, in the conventional integrated circuit device, the transistors of each stage of the PROM decoder 316P and the NROM decoder 316N are arranged in a matrix of 64 rows and 12 columns, but in the integrated circuit device of this embodiment, the PROM decoder 516P and the NROM decoder 516N The transistors in each stage are arranged in a matrix of 32 rows and 24 columns. In the chip length direction, the region where the arrangement of the transistors is doubled from 12 columns to 24 columns is the above-mentioned N-type diffusion layers 43N and N The absorption is almost or completely absorbed by the decrease in the total separation distance from the well 42, the arrangement of the transistors is reduced by half from 64 rows to 32 rows in the chip short direction, and the size of the semiconductor chip 501 in the long direction is almost reduced. Alternatively, the dimension in the short direction can be reduced without any increase. For example, when the cell pitch in the chip length direction of the transistors 31P, 32P, 31N, and 32N is 5 μm, the size can be reduced by 160 μm from the conventional 64 rows × 5 μm = 320 μm to 32 rows × 5 μm = 160 μm. The size of each stage of the ROM decoders 516P and 516N in the chip long direction is doubled, but as described above, the adjacent portions of the NROM decoder 516N and the PROM decoder 516P are reduced in the chip long direction. It can be absorbed with little increase in size. Therefore, when the short dimension of the conventional semiconductor chip 1 is, for example, 1.5 mm, the short dimension and the chip area of the semiconductor chip 41 can be reduced by about 10%.
[0025]
In the above-described embodiment, in the PROM decoder shown in FIG. 3, when the gate rows are doubled, the twelfth gate row 34PAb and the fourteenth gate row 34PBa are all depletion type as shown in Table 1. Since there is no need to input a data signal to these gate rows 34PAb and 34PBa because of the transistor 32P, these gate rows 34PAb and 34PBa can be omitted, and the first and second divided PROMs as shown in FIG. Each of the decoders 616PA and 616PB is a series of 32 transistors in which a source and a drain are connected to five pairs each including two of the enhancement transistor 31P and the depletion transistor 32P for each row and the single enhancement transistor 31P. Circuit 53PA, 53PB, One of the gate columns 34PAa and 34PBa in which the gates of the transistors 31P and 32P are commonly connected in each column, and the other gate columns 34PAb and 34PBb in which the gates of the other transistors 31P and 32P in each pair are commonly connected in each column. And a single gate array 54PAa, 54PBb in which the gates of the single enhancement type transistors 31P are commonly connected to the column, and one end of each transistor series circuit 53PA, 53PB has a positive polarity floor. The other end of each of the transistor series circuits 53PA and 53PB is connected in common and connected to a subsequent circuit, and one of the gate rows 34PAa and 34PBa and the first divided PROM decoder are connected to the control circuits VP1 to VP32 and VP33 to VP64. A single gate row 53PAa of 616PA is , DP6 connected to the normal phases DP1, DP2,..., DP6 of the display data, and the other gate row 54PBb of the second divided PROM decoder 616PBb connected to the other gate rows 34PAb, 34PBb. Since the configuration is connected to the bar, the width of two rows of transistors can be reduced, and the size of the PROM decoder in the chip length direction can be further reduced as compared with the PROM decoder 516P of FIG. Similarly, the NROM decoder 516N can reduce the number of gate rows by two, but the description is omitted.
[0026]
Further, in the above embodiment, the P-type as one conductivity type, the N-type as another conductivity type, the positive polarity as one polarity, and the negative polarity as the other polarity have been described. The mold may have a negative polarity as one polarity and a positive polarity as the other polarity.
Further, in the above embodiment, the arrangement of the PROM decoder and the NROM decoder in the odd-numbered circuit block and the even-numbered circuit block has been described as a mirror arrangement, but they may be the same arrangement. In this case, if the number of outputs of the circuit blocks is as small as six as in the above-described embodiment, and if the number of circuit blocks is as large as 64, the number of adjacent portions of the PROM decoder and the NROM decoder between the circuit blocks increases. This is suitable when the number of outputs is as large as 96 outputs and the number of circuit blocks is as small as four stages.
In the above embodiment, the metal wiring for supplying the positive gradation voltage to supply the positive gradation voltage and the negative gradation voltage with one gradation voltage generating circuit is provided via the NROM decoder. Although a metal wiring for supplying a negative gradation voltage is arranged on the PROM decoder, a gradation voltage generation circuit is arranged between the PROM decoder and the NROM decoder in the circuit block or between the circuit blocks. The metal wiring for supplying the positive gradation voltage can be arranged without passing over the NROM decoder, and the metal wiring for supplying the negative gradation voltage can be arranged without passing over the PROM decoder. In this case, as in the above embodiment, when the number of outputs of the circuit blocks is as small as six, and when the number of circuit blocks is as large as 64, the number of gradation voltage generation circuits increases. It is good to apply when the number of circuit blocks is as small as four. In this case, the arrangement relationship between the P-type diffusion layer of the PROM decoder and the N-type diffusion layer of the NROM decoder is not restricted, and the cell pitch of the transistor in the chip short direction is not restricted by the metal wiring.
[0027]
【The invention's effect】
According to the present invention, M stages of circuit blocks having L outputs are arranged as internal circuits on a semiconductor chip in the longitudinal direction of the chip, and (L / 2) stages of one conductivity type ROM decoder are provided for each circuit block unit. The (L / 2) stage of the other conductivity type ROM decoder is united adjacently in the chip length direction while being integrated together in the chip length direction and adjacent to the one conductivity type ROM decoder in the chip length direction. After arranging, the gate row of each ROM decoder is expanded twice in the horizontal direction, so that the size of the gate row doubled in the horizontal direction is set to the size of the one conductivity type ROM decoder and the other conductivity type ROM decoder. The number of rows of the ROM decoder can be reduced by half with little or no increase in the length of the semiconductor chip by absorbing the reduced amount of the adjacent portion, reducing the length of the semiconductor chip in the short direction, One chip area it is possible to provide a liquid crystal display device using the integrated circuit device and the same reduction. Further, by expanding the gate row of the ROM decoder in the horizontal direction by omitting the gate row composed of only the depletion type transistors by expanding the gate row of the ROM decoder in the horizontal direction, the size of the gate row of the ROM decoder in the horizontal direction can be further increased by one conductor. It becomes easier to absorb the reduced portion of the adjacent type ROM decoder and the other conductive type ROM decoder.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a semiconductor chip as an integrated circuit device according to one embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a circuit block arranged on the semiconductor chip of FIG. 1;
FIG. 3 is a circuit diagram of a PROM decoder according to an embodiment included in the D / A converter of the circuit block of FIG. 2;
FIG. 4 is a circuit diagram of a PROM decoder according to another embodiment included in the D / A converter of the circuit block of FIG. 2;
5 is a schematic plan pattern diagram on a semiconductor chip of a PROM decoder and an NROM decoder included in the D / A converter of the circuit block of FIG. 2;
FIG. 6 is a schematic plan view of a semiconductor chip as a conventional integrated circuit device.
FIG. 7 is a schematic configuration diagram of a circuit block arranged on the semiconductor chip of FIG. 6;
8 is a circuit diagram of a PROM decoder included in the D / A converter of the circuit block of FIG.
9 is a circuit diagram of an NROM decoder included in the D / A converter of the circuit block of FIG.
10 is a schematic plan pattern diagram on a semiconductor chip of a PROM decoder and an NROM decoder included in the D / A converter of the circuit block of FIG. 7;
FIG. 11 is a schematic structural view of a liquid crystal display module.
FIG. 12 is a block diagram illustrating a schematic configuration of a horizontal driver of the liquid crystal display module of FIG. 11;
[Explanation of symbols]
31P P-channel enhancement type transistor
31N N-channel enhancement type transistor
32P P-channel depletion type transistor
32N N-channel depletion type transistor
33PA, 33PB, 53PA, 53PB Transistor series circuit
34PA, 34PB Gate row pair
34PAa, 34PAb, 34PBa, 34PBb, 54PAa, 54PBb gate row
41 Semiconductor substrate
42 N-well
43N N-type diffusion layer
43P P-type diffusion layer
501 semiconductor chip
502 Internal circuit
503 circuit block
511 shift register
512 data register
513 1st changeover switch
514 Latch
515 level shifter
516 D / A converter
516P PROM decoder
516N NROM decoder
516PA, 516NA, 616PA, 616NA First divided ROM decoder
516PB, 516NB, 616PB, 616NB Second divided ROM decoder
517 Second changeover switch
518 Voltage follower output circuit

Claims (7)

Circuit blocks having L (even number) outputs are arranged in M stages in the longitudinal direction of a long rectangular semiconductor chip,
(L / 2) stages in which the (L / 2) stages are collectively arranged adjacent to each other in the chip length direction to output a unipolar gradation voltage from each stage; and (L / 2) The stages are arranged adjacently in the chip longitudinal direction and are collectively arranged, and the other conductive type ROM decoder that outputs the other polarity gradation voltage from each stage is arranged adjacent to the chip longitudinal direction,
An integrated circuit device , wherein, as each of the L outputs, an odd-numbered output and an even-numbered output have different polarities, and output the one-polarity grayscale voltage and the other-polarity grayscale voltage alternately,
Each stage of the one-conductivity-type ROM decoder is supplied with a unipolar gradation voltage of (2 n) gradations and receives one bit of (2 n) gradations based on n-bit display data. Each stage of the other-conductivity-type ROM decoder outputs a unipolar gradation voltage, and each stage of the other-conductivity-type ROM decoder is supplied with a (2 n) gradation other polarity gradation voltage and (2 n) based on n-bit display data. Outputting the other polarity gradation voltage of one of the gradations,
Each stage of the one-conductivity-type ROM decoder includes a first-conduction-type first divided ROM decoder to which a half-polarity gradation voltage of half of (2 n) gradations is supplied; And 2) one-conductivity-type second divided ROM decoder to which a unipolar gradation voltage of the other half of the gradation is supplied, each divided in the longitudinal direction of the chip, and The stage comprises a first divided ROM decoder of the other conductivity type to which a half-polarity gray scale voltage of half of (2 n) gray levels is supplied, and the other half of (2 n) gray scales And a second divided ROM decoder of the other conductivity type to which a gray scale voltage of the other polarity is supplied, each of which is arranged side by side in the chip length direction . 2. The integrated circuit device according to claim 1, wherein the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder are arranged in a mirror in a circuit block adjacent to each circuit block. In each row of the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder , two pairs of the respective conduction-type enhancement-type transistors and depletion-type transistors are used as a pair (2 to the power of (n-1)). A matrix arrangement of (2 to the (n-1) th power) rows and 4n columns of transistors having 2n pairs of columns ;
The first divided ROM decoders of the respective conductivity types include n pairs of columns from the first column to the second n-th column of the matrix arrangement, and the second divided ROM decoders of the respective conductivity types correspond to the first and second columns of the matrix arrangement. 2. The integrated circuit device according to claim 1, comprising n pairs of columns from the (2n + 1) th column to the fourth nth column . The first divided ROM decoder and the second divided ROM decoder of the respective conductivity types each include the n-type enhancement transistor and the depletion transistor in each of the (2 (n−1) power) rows. A transistor series circuit connected by a source and a drain, and a gate of one of the pair of transistors connected to one of the columns and a transistor of the other column connected in common to each of the n pairs of columns. A gate line pair including a gate line and a gate line commonly connected to each other, and one end of each of the transistor series circuits is connected to the gradation voltage, and the other end of each of the transistor series circuits is commonly connected to a subsequent stage. 請 which is connected, connected to the other gate array to the positive phase of the the one gate array the display data is connected to the opposite phase of the display data on the Integrated circuit device of claim 3, wherein. In each row of the one-conductivity-type ROM decoder and the other-conductivity-type ROM decoder , two pairs of the respective conduction-type enhancement-type transistors and depletion-type transistors are used as a pair (2 to the power of (n-1)). (2 (n-1)) rows of transistors consisting of 2 (n-1) pairs of columns, (2 (n-1)) rows and 2 columns of enhancement transistors of the respective conductivity types ; 2 (2n-1) columns matrix arrangement,
The first divided ROM decoders of the respective conductivity types are arranged in the (n-1) th column and the (2n-1) th column of the first to second (n-1) th columns of the matrix arrangement. And the second divided ROM decoders of the respective conductivity types are arranged in the matrix arrangement in the first column of the 2nth column and the (nn + 1) th column to the (nn-1) th column of the second (2n-1) th column. 1) The integrated circuit device according to claim 1, wherein the integrated circuit device comprises a pair of columns . Each of the first divided ROM decoder and the second divided ROM decoder of the conductivity type includes an enhancement transistor and a depletion transistor of the (n-1) pairs of columns for each of the (2 (n-1)) rows. A transistor series circuit in which the source transistor and the one column of the enhancement type transistor are connected by a source and a drain, and the gate of one of the one row of the transistors is connected to each of the (n-1) pairs of columns. alone and gate array pair gates of transistors commonly connected one gate array and the other in one column is made of a commonly connected other gate array, a gate of the enhancement mode transistor of the first column are connected common One end of each of the transistor series circuits is connected to the gradation voltage, and one end of each of the transistor series circuits is connected to one end of each of the transistor series circuits. Are connected in common and connected to the subsequent stage, and the one gate row and the single gate row of the first divided ROM decoder are connected to the positive phase of the display data, and the other gate row and the second divided ROM are connected. 6. The integrated circuit device according to claim 5, wherein a single gate row of the decoder is connected to the opposite phase of the display data. A liquid crystal display device, wherein the integrated circuit device according to claim 1 is mounted on a tape carrier package for driving a data line of a liquid crystal panel.

Images