JP3546693B2 - Audio fade circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an audio fade circuit suitable for use in a DVC (digital video camera), an MD (mini disc player), and the like.
[0002]
[Prior art]
In recent years, audio processing circuits such as DVC and MD have provided audio fade functions such as a fade-in function in which the sound gradually increases and a fade-out function in which the sound gradually decreases in order to effectively record and reproduce the sound. Have more.
[0003]
Hereinafter, a conventional audio fade circuit will be described.
Conventionally, an audio fade circuit described in Japanese Patent Publication No. 7-12130 has been known. FIG. 6 shows the audio fade circuit. FIG. 6 shows a block diagram of a conventional audio fade circuit, and FIG. 7 shows a signal waveform at each point in FIG. In FIG. 6, reference numeral 1 denotes an audio input terminal to which an audio signal is input, and 5 denotes an amplifier circuit for amplifying the audio signal input from the audio signal input terminal 1, and an automatic gain control function for controlling the gain of the input audio signal. It has. Reference numeral 2 denotes an audio output terminal for outputting an audio signal output from the amplifier circuit 5 to the outside, reference numeral 3 denotes a DC voltage addition terminal to which a DC voltage (for example, +5 V) is input, and reference numeral 4 denotes an audio fade control signal input by a user operation. The audio fade control signal input terminal is operated by a user to operate a fade switch provided in a video camera, for example, to input a control signal. 8 is a switch circuit for creating an audio fade signal from the audio fade control signal from the audio fade control signal input terminal 4 and the DC voltage from the DC voltage adding element 3, and 7 is only a low frequency band of the audio fade signal from the switch circuit 8. A low-pass filter (hereinafter, referred to as LPF) 6 that passes therethrough is a voltage limit circuit that controls the gain in the amplifier circuit 5 based on the audio fade signal from the LPF 7.
[0004]
The operation of the conventional audio fade circuit configured as described above will be described below.
[0005]
First, when the audio fade control signal is not input (between waveforms A and B in FIG. 7C and after point E), the potential at point S4 in FIG. Since it is not provided, the audio signal (the waveform of FIG. 7A) input to the audio input terminal 1 is amplified by the gain by the amplifier circuit 5 and output to the audio output terminal 2 (FIG. 7). (Between waveforms A and B in (b) and after point E).
[0006]
Next, when an audio fade control signal is input to the audio fade control terminal 4 (point B in FIG. 7C), the DC voltage applied to the DC voltage addition terminal 3 and the audio fade control signal As a result, an audio fade signal having a waveform as shown in FIG. This audio fade signal changes as shown in the waveform of FIG. 7E by passing through the LPF 7. The time during which the DC voltage is applied is determined by the time constant in the LPF 7. The applied voltage is applied to the automatic gain control circuit of the amplifier circuit 5 to operate the automatic gain control. Therefore, the voltage applied to the point S5 in FIG. 6 is determined by the voltage limit circuit 6, but it is necessary to have a level sufficient to sufficiently operate the automatic gain control circuit of the amplifier circuit 5. Automatic gain control is gradually performed in the automatic gain control circuit by the voltage applied to the point S5 in FIG. 6, and the amplitude of the audio signal output from the amplifier circuit gradually decreases (FIG. 7B ) Waveforms B to C). As described above, the time during which the amplitude of the output audio signal is reduced and faded out is determined by the time constant in the LPF 7.
[0007]
When the input of the audio fade control signal is stopped after the input of the audio fade control signal (point D in FIG. 7C), the potential at the point S4 in FIG. Therefore, the DC voltage applied to the point S5 in FIG. 6 gradually falls to the ground level mainly through the voltage limit circuit 6, and the automatic gain control circuit does not operate. As a result, the automatic gain control circuit gradually stops automatic gain control, and the amplitude of the audio signal output from the amplifier circuit gradually increases (between waveforms D to E in FIG. 7B). Therefore, the time during which the amplitude of the audio signal increases (fade-in) is determined by the voltage held by the voltage limit circuit 6 and the amount of current when the voltage is discharged. The audio fade operation is performed as described above.
[0008]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, since the audio signal is faded when the audio signal is an analog signal, circuits such as an automatic gain control circuit and a voltage limit circuit as described in the conventional configuration are required, There is a problem that it is disadvantageous for downsizing the circuit.
[0009]
An object of the present invention is to solve the above-mentioned conventional problems and to provide an audio fade circuit having a characteristic equivalent to that of performing an audio fade operation using an analog signal by using a simple circuit configuration.
[0010]
[Means for Solving the Problems]
To achieve this object, an audio fade circuit of the present invention is an audio fade circuit capable of fading in and out an input digital audio signal, and a multiplying means for multiplying the input digital audio signal by a multiplication coefficient. , and a multiplication coefficient generating means how changes in coefficients to be input to the multiplication means for generating a set multiplication coefficient to vary by a straight line having at least two slopes, the multiplication coefficient generating circuit, the multiplication factor , A timing generator for generating a clock of a counter included in the multiplication coefficient generator, a first counter that operates based on the clock generated by the timing generator, and the first counter. When the value of the first counter reaches a predetermined value, an enable signal allowing the operation of the counter or the first counter is reset. A first decoder for generating a signal to be output, an up / down counter for increasing or decreasing a multiplication coefficient by an enable signal from the first decoder and a clock from the timing generation means, and a multiplication generated by the up / down counter. A second decoder for controlling the operation of the first decoder according to the value of the coefficient, wherein the up / down counter operates as a down counter for gradually decreasing the coefficient from the maximum multiplication coefficient at the time of fading out, and at the time of fading in. The multiplication coefficient is generated so as to operate as an up counter that gradually increases the coefficient from the minimum multiplication coefficient .
[0011]
With such a configuration, it is possible to obtain an audio fade circuit having a characteristic equivalent to that of performing an audio fade operation with an analog signal using a simple circuit configuration.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
According to a first aspect of the present invention, there is provided an audio fade circuit capable of fading in and out an input digital audio signal, wherein the multiplication means multiplies the input digital audio signal by a multiplication coefficient, and Multiplying coefficient generating means for generating a multiplying coefficient set so that the way of changing the coefficient input to the means changes with a straight line having at least two slopes , wherein the multiplying coefficient generating circuit generates the multiplying coefficient Timing generating means for generating a clock of a counter included in the multiplication coefficient generating means by taking timing, a first counter operating based on the clock generated from the timing generating means, and a value of the first counter being When a predetermined numerical value is reached, an enable signal for permitting the operation of the counter and a signal for resetting the first counter are generated. A first decoder, an up / down counter for increasing or decreasing a multiplication coefficient by an enable signal from the first decoder and a clock from the timing generation means, and a multiplication coefficient generated by the up / down counter according to a value of the multiplication coefficient. A second decoder for controlling the operation of the first decoder, wherein the up / down counter operates as a down counter for gradually decreasing the coefficient from a maximum multiplication coefficient when fading out, and a coefficient from a minimum multiplication coefficient when fading in. , Which generates a multiplication coefficient that operates as an up-counter that gradually increases the audio fade-out circuit. Using a simple circuit configuration, it is possible to obtain an audio fade circuit having the same characteristics as the case of performing an audio fade operation with an analog signal. Has an action.
[0016]
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 5.
(Embodiment 1)
FIG. 1 is a block diagram of an audio fade circuit of the present embodiment. In FIG. 1, 1 is a digital audio input terminal for inputting a digital audio signal, 2 is an audio fade control input terminal for inputting an audio fade control command signal, Reference numeral 3 denotes a multiplication coefficient generation circuit which is a multiplication coefficient generation means for determining a time constant and a characteristic gradient of an audio fade. 4 denotes a digital audio signal input from the digital audio input terminal 1 and a multiplication coefficient generated by the multiplication coefficient generation circuit 3. This is a multiplication circuit which is a multiplication means for multiplying the multiplication by, for example, a multiplication circuit used for a digital filter or the like. Reference numeral 5 denotes a digital audio output terminal for outputting the digital audio signal output from the multiplication circuit 4 to the outside.
[0017]
FIG. 2 is a block diagram showing an example of the multiplication coefficient generation circuit 3 of FIG. In FIG. 2, reference numeral 11 denotes a timing generation circuit for generating a clock of a counter included in the multiplication coefficient generation circuit 3 at a timing for generating a multiplication coefficient, and 12 a counter operating based on the clock generated from the timing generation circuit 11. , 13 is a first decoder that generates an enable signal that allows the operation of the counter 12 when the value of the counter 12 reaches a certain value, and a signal that resets the counter 12, and 14 is a coefficient that is used to fade out the largest multiplication coefficient during fade-out. An up / down counter that operates as a down counter that gradually decreases, and generates a multiplication coefficient so as to operate as an up counter that gradually increases the coefficient from the minimum multiplication coefficient at the time of fade-in. Of the first decoder 13 according to the value of Second decoder for constant, 16 is a multiplier coefficient output terminal for outputting a multiplication coefficient generated by the up-down counter 14.
[0018]
3 and 4 are timing charts of each signal in the present embodiment, and the continuation of the timing chart of FIG. 3 is the timing chart of FIG. FIG. 5 is a characteristic diagram showing characteristics of a multiplication coefficient that changes with time.
[0019]
The operation of the audio fade circuit of the present embodiment configured as described above will be described with reference to FIGS.
[0020]
First, the fade-out operation of the audio fade circuit according to the present embodiment will be described.
[0021]
In the timing generation circuit 11 of FIG. 2, a clock signal as shown in FIG. 3A is adjusted so that the digital audio signal input from the digital audio input terminal 1 of FIG. Has been output. The counter 12 is set so that the counter value increases for each clock output from the timing generation circuit 11. In the second decoder 15, which monitors the output of the multiplication coefficient from the up / down counter 14, the multiplication coefficient (here, X) is outside the range indicated as α and β in the characteristic diagram of the multiplication coefficient in FIG. For example, "0" is output when (X> α, X <β), and "1" is output when it is within the range indicated by α and β (β ≦ X ≦ α). It works like this.
[0022]
Further, the first decoder 13 operates so as to enable the up-down counter 14 (permit operation) and control the reset of the counter 12 by watching the output value from the second decoder 15. For example, like the timing of t2 in FIG. 3, the output value from the second decoder 15 is “0” (when the multiplication coefficient X is out of the range of α to β, for example, M in FIG. 5). When the output value of the counter 12 shown in (b) becomes "3", the first decoder 13 outputs a "1" signal as shown in FIG. Operate to output. Also, as shown at the timing t1 in FIG. 4, the output value from the second decoder 15 is "1" (when the multiplication coefficient X is in the range of α to β, for example, N in FIG. 5). Is "0", the first decoder 13 is set to operate to output the signal of "1" and output the enable signal and the reset signal as shown in FIG. ing.
[0023]
In this case, if the output value from the second decoder 15 is “0”, the output value of the counter 12 is “3”, and the first decoder 13 operates so as to output the enable signal and the reset signal, 3 (b), the output signal of the counter 12 operates so as to repeatedly output "0" to "3". If the output value of the second decoder 15 is “1”, the output value of the counter 12 is “0”, and the first decoder 13 operates to output the enable signal and the reset signal, As shown in the counter output after t1 in FIG. 4B, the output of the counter 12 operates so as to repeatedly output “0”.
[0024]
When performing the fade-out operation, the fade-down signal input from the audio fade control input terminal 2 is received, and the up-down counter 14 of FIG. 2 operates as a gradually decreasing down counter.
[0025]
During the fade-out operation, if the multiplication coefficient is outside the range indicated by α and β on the characteristic diagram of the multiplication coefficient in FIG. 5, the output value of the counter 12 becomes “3” as shown in FIG. When this happens, the up / down counter 14 operates so as to gradually decrease by one from the maximum value of the multiplication coefficient (here, M). When the multiplication coefficient is within the range indicated by α and β, the output of the counter 12 becomes “0” in the entire range as shown after t1 in FIG. The enable signal is input to the counter 14 in all ranges. As a result, in the up / down counter 14, each time a clock signal is input, the multiplication coefficient decreases, for example, by 1 from the value when X = α (here, N).
[0026]
As described above, the multiplication coefficient output from the multiplication coefficient generation circuit 3 in FIG. 1 and the digital audio input from the digital audio input terminal 1 are multiplied by the multiplication circuit 4, and as a result, the digital audio output terminal 5 Performs a fade-out operation on an approximate straight line as shown in the characteristic diagram of the multiplication coefficient in FIG.
[0027]
Further, in the case of the fade-in operation, the operation of the multiplication coefficient generation circuit 3 performs an operation completely opposite to that in the case of the fade-out operation, and the up / down counter 14 operates as an up counter that gradually increases by one from the minimum multiplication coefficient. . The multiplication coefficient generated in this way is output to the multiplication circuit 4, and the multiplication circuit 4 multiplies the multiplication coefficient with the digital audio input from the digital audio input terminal 1, thereby obtaining the digital audio output from the digital audio output terminal 5. A fade-in operation can be performed.
[0028]
As described above, according to the present embodiment, a multiplication circuit 4 that multiplies an input digital voice by a multiplication coefficient to perform fade-in and fade-out, and a multiplication coefficient generation circuit that generates a multiplication coefficient to be multiplied by the multiplication circuit 4 3, the number of circuits and components used can be reduced by, for example, using the same as a multiplication circuit used in a digital filter, and the multiplication coefficients generated by the multiplication coefficient generation circuit 3 are shown in FIG. By changing with such characteristics, it is possible to obtain the same audio fade characteristics as the analog audio fade operation.
[0029]
In the above description, the switching range of the second decoder 15 in FIG. 2 is set to two points α and β. However, control may be performed with three or more switching ranges. Further, the values of the enable and reset control of the first decoder 13 in FIG. 2 are set to “0” and “3”, but it is of course possible to set other values.
[0030]
Further, in the above description, the increase / decrease value of the up / down counter 14 is set to “1”. Further, in the above description, a straight line having the same inclination is used for the fade-out and the fade-in, but a different line may be used for the fade-out and the fade-in.
[0031]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the number of configured circuits and components, it is easy to incorporate into an integrated circuit, etc., and by changing the multiplication coefficient in a polygonal manner, the same as the analog audio fade operation is performed. An excellent effect that a fade characteristic can be obtained is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram of an audio fade circuit according to a first embodiment of the present invention; FIG. 2 is a block diagram showing a configuration of a multiplication coefficient generation circuit according to the first embodiment; FIG. FIG. 4 is an operation waveform diagram for explaining the operation of the circuit. FIG. 4 is an operation waveform diagram for explaining the operation of the audio fade circuit according to the first embodiment. FIG. 5 is a characteristic of a multiplication coefficient in the audio fade circuit according to the first embodiment. FIG. 6 is a block diagram of a conventional audio fade circuit. FIG. 7 is a signal waveform diagram for explaining an operation of the conventional audio fade circuit.
1 digital audio input terminal 2 audio fade control input terminal 3 multiplication coefficient generation circuit 4 multiplication circuit 5 digital audio output terminal

Claims (1)

An audio fade circuit capable of fading in and out of an input digital audio signal, wherein the multiplication means multiplies the input digital audio signal by a multiplication coefficient, and the coefficient input to the multiplication means changes at least two times. Multiplication coefficient generation means for generating a multiplication coefficient set so as to change with a straight line having two slopes , wherein the multiplication coefficient generation circuit takes a timing to generate the multiplication coefficient and includes a counter included in the multiplication coefficient generation means Timing generating means for generating a clock signal, a first counter operating based on the clock generated from the timing generating means, and an operation of the counter when the value of the first counter reaches a predetermined value. A first decoder for generating an enable signal to be allowed and a signal for resetting the first counter; An up / down counter for increasing or decreasing a multiplication coefficient by an enable signal from a decoder and a clock from the timing generation means, and controlling an operation of the first decoder in accordance with a value of the multiplication coefficient generated by the up / down counter. The up / down counter operates as a down counter that gradually decreases the coefficient from the maximum multiplication coefficient when fading out, and operates as an up counter that gradually increases the coefficient from the minimum multiplication coefficient when fading in. An audio fade circuit for generating such a multiplication coefficient .

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