JP3541498B2 - Data processing device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a data processing device used in a microcomputer (microcomputer) or a digital signal processor (DSP).
[0002]
[Prior art]
When speeding up processing in a data processing device, the speed of reading data from a memory often becomes a bottleneck. One means for speeding up data reading is referred to as "double speed reading" and will be described below. The double-speed reading is a method of reading data corresponding to two addresses of an even address and an odd address at a time in one machine cycle when reading data from a memory.
[0003]
A conventional data processing device using the double-speed reading will be described with reference to the drawings.
[0004]
FIG. 7 shows a configuration of a data processing unit of a conventional data processing device. In FIG. 1, reference numerals 101 and 102 denote memories which store original data to be operated. Reference numerals 103 to 105 denote multiplexers, which function as selection means for selecting a path from the memory 101 to the arithmetic unit and a path from the memory 102 to the arithmetic unit. Latch circuits 106 to 108 temporarily hold the data output from the memory 101 and the memory 102. Note that these three latch circuits have the same data holding time, and are set to a time corresponding to a half cycle of a machine cycle (basic cycle). An arithmetic unit 109 operates on two data output simultaneously from the latch circuits 107 and 108 and outputs the operation result.
[0005]
The data output from the memory 101 and the memory 102 becomes new data sequentially by address update by an address pointer (not shown), and this data is read. In particular, in the case of double-speed reading, the address pointer does not update the address by “1”, but sequentially updates only the even-numbered addresses, for example, addresses 2m, 2m + 2, 2m + 4,. Alternatively, the addresses are sequentially updated using only odd addresses such as addresses 2m + 1, 2m + 3, addresses 2m + 5, and so on. When the address pointer designates one address (for example, an even address) to the memory in this way, data corresponding to the two addresses of the even address and the next odd address are set and read. For example, data corresponding to addresses 2m and 2m + 1 are sequentially read from the memory in response to the address specification of address 2m, and data corresponding to addresses 2m + 2 and 2m + 3 are read from the memory in response to the address specification of address 2m + 2. It is. When an address is specified at an odd address, two data corresponding to the odd address and the previous even address are output. For example, data corresponding to addresses 2m and 2m + 1 are sequentially read from the memory in response to the address specification of address 2m + 1. As described above, if double-speed reading is used, two data can be read for one address specification, so that the data processing speed is doubled.
[0006]
The use of double-speed reading in this way has the effect of doubling the data processing speed, but it is necessary to adjust the timing of data input to the arithmetic unit 109 in order to sequentially execute correct calculations. That is, when two data are calculated, these two data must be input to the arithmetic unit 109 at the same timing. However, in double-speed reading, two data are read from one memory by one address designation. The timing control differs depending on which data is to be calculated. For this timing control, multiplexers 103 to 105 and latch circuits 106 to 108 are provided.
[0007]
The operation of the data processing device that performs timing control will be described with reference to FIGS. 8 and 9 are timing charts showing the timing of data output from the memory and the timing of input to the arithmetic unit. In the following description, an example will be described in which data processing is performed with an even address first and an odd address later in one machine cycle.
[0008]
FIG. 8 is a timing chart in a case where data output from two memories is processed without shifting the input timing to the arithmetic unit 109. The data of the even addresses stored in each of the memory 101 and the memory 102 are output at the same time, and are input to the arithmetic unit 109 at the same timing and are calculated. The data of the odd addresses stored in the memory 101 and the memory 102 at the next timing are also input to the arithmetic unit 109 at the same timing and calculated. Further, in this data processing, a case is shown in which an arithmetic operation is performed using data from address 2m of memory 101 to address 2m + 5 consecutively, and data from address 2n to address 2n + 5 of memory 102. Note that m and n are integers.
[0009]
First, at the start of the data processing, the following control is performed on the data processing device of FIG. 7 by a control unit (not shown). That is, the multiplexer 104 selects the output of the memory 101, and the multiplexer 105 selects the output of the memory 102. At this time, the multiplexer 103 may be in any control state (irrelevant).
[0010]
Data reading is performed under such a control state. When an address pointer (not shown) of the memory 101 designates one even address (even address) 2m, the data of the even address 2m is read from the memory 101 in the first half of the machine cycle (basic cycle), and the odd address is read in the second half. 2m + 1 data is read. Since the multiplexer 104 selects the output of the memory 101, these data are sequentially taken into the latch circuit 107 and output. On the other hand, when the address pointer of the memory 102 designates one even address 2n, the data of the even address 2n is read from the memory 102 in the first half of the machine cycle, and the data of the odd address 2n + 1 is read in the second half. In the multiplexer 105, the output of the memory 102 is selected, and the data is captured and output to the latch circuit 108. As described above, since both the output from the memory 101 and the output from the memory 102 are input to the arithmetic unit 109 via one latch circuit, they are input to the arithmetic unit 109 at the same timing. Thereafter, similarly, the data at address 2m + 2 and the data at address 2n + 2, the data at address 2m + 3 and the data at address 2n + 3, the data at address 2m + 4 and the data at address 2n + 4, and the data at address 2m + 5 and data at address 2n + 5 are input to the arithmetic unit 109. Is calculated. When data of even addresses and data of odd addresses are operated on each other as described above, data of the memory 101 is input to the latch circuit 107 and data of the memory 102 is input to the latch circuit 108. Can be input to the computing unit 109 at the same timing to perform the computation.
[0011]
Next, FIG. 9 shows an operation in a case where the calculation of the data of the even address and the data of the odd address are executed. Here, an example will be described in which data of an even address is read from the memory 101 and data of an odd address is read from the memory 102 in the first reading. At the start of data processing, address pointers (not shown) for the memories 101 and 102 indicate even and odd addresses, respectively. Based on the values of these address pointers, the following control is performed by the control means (not shown) on the data processing device of FIG. The multiplexer 103 selects the output of the memory 101, and the multiplexer 104 selects the output of the latch circuit 106. The multiplexer 105 selects the output of the memory 102. As a result, the data output from the memory 101 is input to the arithmetic unit 109 through the latch circuit 106 and the latch circuit 107, and the data output from the memory 102 is input to the arithmetic unit 109 through the latch circuit 108. That is, the output data of the memory 101 passes through one more latch circuit than the output data from the memory 102, so that the input timing to the arithmetic unit 109 is delayed. This delay time is a half cycle of the machine cycle.
[0012]
When data is read under such a control state, the data at address 2m and the data at address 2n are first read from the memories 101 and 102 at the same timing, but the output data from the memory 101 is According to the selection of the multiplexers 103 and 104, the data is input to the arithmetic unit 109 via the latch circuit 106 and the latch circuit 107. The output from the memory 102 is input to the arithmetic unit 109 via the latch circuit 108 by the selection of the multiplexer 105. As a result, the output of the memory 101 is input to the arithmetic unit 109 with a delay of 1/2 cycle as compared with the output of the memory 102. Therefore, as shown in FIG. 9, in the first half of the first cycle of the machine cycle, the data at the address 2n, which is the first output of the memory 102, has no data to be input to the arithmetic unit 109 at the same timing. Not calculated. Next, in the latter half of the first cycle of the machine cycle, the data at the address 2m output from the memory 101 and the data at the address 2n + 1 output from the memory 102 are supplied from the latch circuits 107 and 108 at the same timing. Input to 109. Similarly, data of address 2m + 1 and data of address 2n + 2, data of address 2m + 2 and data of address 2n + 3, data of address 2m + 3 and data of address 2n + 4, data of address 2m + 4 and data of address 2n + 5, and data of address 2m + 5 The arithmetic unit 109 calculates the data and the data at the address 2n + 6. As described above, when calculating the data of the even address and the data of the odd address, the calculation is performed by shifting the timing of the data of the two systems.
[0013]
Although FIG. 9 shows an example in which the output data of the memory 101 is delayed by １ ／ cycle, the operation of delaying the output of the memory 102 by サ イ ク ル cycle is only a symmetric operation. Description is omitted because there is.
[0014]
[Problems to be solved by the invention]
In the above-described conventional configuration, even when the data of the even address and the data of the odd address are calculated, an appropriate calculation can be performed by changing the control state of the multiplexer before the start of the data processing. However, if the data input timing to the arithmetic unit needs to be changed during the data processing, not before the start of the data processing, the conventional configuration cannot cope. That is, conventionally, if the control state of the multiplexer is determined at the start of the data processing, the data processing can only be performed in the same control state thereafter. However, for example, when the address indicated by the address pointer circulates in a certain area, or when cyclic addressing is used, the data timing is not aligned in the second cycle or later depending on the range of the area. There is a problem that can not be.
[0015]
An example will be described with reference to FIG. FIG. 10 shows an operation timing when a normal address is used as an address pointer of the memory 101 and a cyclic address is used as an address pointer of the memory 102. The memory 101 uses data from address 2m to address 2m + 5, the memory 102 uses addresses circulating between address 2n and address 2n + 4, and uses data from address 2n to address 2n in the second cycle. At the start of the operation, the address pointer of the memory 101 indicates the address 2m, and the address pointer of the memory 102 indicates the address 2n. These address pointers sequentially indicate 2m + 2 and 2n + 2, 2m + 4 and 2n + 4. The control state of the multiplexer at the start of the operation is the same as in the operation shown in FIG. That is, at the start of the data processing, the multiplexer 104 selects the output of the memory 101 and the multiplexer 105 selects the output of the memory 102 by a control unit (not shown) for the data processing apparatus of FIG. Further, the multiplexer 103 may have any control.
[0016]
When data reading from the memory is started in such a control state, as shown in FIG. 10, data up to the first half of the third machine cycle (addresses 2m to 2m + 4, addresses 2n to 2n + 4) is the operation shown in FIG. It is calculated at the same timing as. However, the operation must be performed between the address 2m + 5 and the address 2n in the second cycle. However, if the address pointer indicates the address 2n + 4 due to the limitation of double-speed reading of the memory, the data at the addresses 2n + 4 and 2n + 5 Address data is output as a set. That is, the data at the address 2n + 5 is always output in the latter half of the cycle for outputting the data at the address 2n + 4. For this reason, the data at addresses 2m + 5 and 2n + 5 are input to the arithmetic unit 109 at the same timing, and the desired operation (the operation of the data at addresses 2m + 5 and 2n) cannot be performed. That is, when double-speed reading is used, even-numbered address data and odd-numbered address data are always read as a set, so that it is impossible to finish reading only even-numbered addresses. For this reason, in the above case, the data input timing to the arithmetic unit is shifted in the second and subsequent cycles of the cyclic address, so that an erroneous operation is performed.
[0017]
The present invention solves the above-described problems, and provides a data processing device that can accurately perform an operation even when both double-speed reading and cyclic addressing are used.
[0018]
The data processing device according to claim 1 stores data to be operated, and stores an even address in the first half and the second half of one cycle, respectively. Odd address A first memory and a second memory that successively output data corresponding to two addresses; , The first memory is read by a cyclic address In the data processing device, a computing unit that computes data output from the first memory and the second memory, and an output of either the first memory or the second memory is input to the computing unit. Delay means for delaying the timing of the operation, and whether the outputs of the first memory and the second memory are input to the arithmetic unit via the delay means or to the arithmetic unit without passing through the delay means Selecting means, a first address holding means functioning as an address pointer of the first memory, and a second address holding means functioning as an address pointer of the second memory, The selecting means operates according to any one of three operation modes. In the first mode, the operation unit outputs both the output of the first memory and the output of the second memory without passing through the delay means. In the second mode, the output of the first memory is input to the arithmetic unit via the delay means without passing the output of the first memory through the delay means, In the mode, the output of the first memory is input to the arithmetic unit via the delay means and the output of the second memory is not passed through the delay means, and the cyclic address is changed from the last address to the first address. When the last address of the cyclic address is an odd address, the operation mode is not converted in any operation mode, the last address of the cyclic address is an even address, and the operation mode is the second address. 2 The first mode when the over-de, when the operation mode is the third mode to the first mode, when the operation mode is the first mode into a second mode It is characterized by the following.
[0021]
[Action]
According to the above configuration, the data processing device not only selects the data input timing to the arithmetic unit when starting to read data from the memory, but also performs the arithmetic operation after reading the data of the last address of the cyclic address from the memory. It is possible to select the data input timing to the container. Therefore, it is possible to use the cyclic address in the data processing device for double-speed reading.
[0022]
【Example】
A data processing apparatus using double-speed reading according to an embodiment of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 shows the configuration of the data processing device of the present embodiment. In the figure, reference numeral 1 denotes a data processing unit. The data processing unit 1 has the same configuration as the conventional one shown in FIG. 7, and includes a memory 2, a memory 3, multiplexers 4 to 6, latch circuits 7 to 9, and an operation unit. It comprises a vessel 10. The multiplexer 4 functions as a selection unit for selecting either the output of the memory 2 or the output of the memory 3, and the output data of the multiplexer 4 is input to the latch circuit 7 and held. The output of the memory 2 and the output of the latch circuit 7 are input to the multiplexer 5, and one of the outputs is selected and input to the latch circuit 8 and held. The output of the memory 3 and the output of the latch circuit 7 are input to the multiplexer 6, and one of the outputs is selected and input to the latch circuit 9 and held. The output data of the latch circuit 8 and the output data of the latch circuit 9 are input to the arithmetic unit 10 in synchronization, and two data are calculated and output. The arithmetic unit 10 is an arithmetic unit such as an adder / subtracter, a logical operation unit, and a multiplier. Note that a register serving as an output destination of the arithmetic unit 10 is omitted in FIG.
[0024]
Reference numeral 11 denotes control means typified by a central processing unit (CPU) and the like. Reference numerals 12 and 13 denote address holding registers which function as address pointers of the memories 2 and 3, respectively. Reference numeral 14 denotes a register that holds the start address of the cyclic register when the register 13 holds the cyclic register, and reference numeral 15 denotes a register that holds the last address of the cyclic register. Reference numeral 16 denotes a comparator which compares the address value held in the register 13 with the address value held in the register 15 and outputs a match signal to the control means 11 and the adder 17 when they match. The comparator 16 compares the address value of the register 13 with the address value of the register 15 except for the least significant bit of each address value (binary number). That is, comparison is made without distinguishing even addresses and odd addresses in the same cycle. Therefore, the address value of the register 13 is incremented by "2" and always indicates only the even address. On the other hand, even if the final address held in the register 15 is an odd number, the address is read in the same machine cycle. If so, a match signal is output. Adders 17 and 18 increment the address value held in the register 13 or the register 12 every machine cycle and input the incremented value to the register 13 again. That is, the adders 17 and 18 sequentially update the value of the address pointer. When the adder 17 receives the coincidence signal from the comparator 16, it inputs the value of the start address of the cyclic address held in the register 14 to the register 13 without incrementing the value of the register 13. This allows cyclic addressing.
[0025]
The address values held by the registers 12, 13, and 15 are also input to the control unit 11 as signals s12, s13, and s15. If these address values are held in binary form, only the information of the least significant bit may be input to the control means 11. That is, the address is input to the control means 11 in order to determine whether these address values are even or odd. The coincidence signal s16 output from the comparator 16 is also input to the control means 11. When receiving the coincidence signal s16, the control means 11 determines whether the last address of the cyclic address is an even number or an odd number based on the signal s15 from the register 15, and according to the determination result, the control signals c and d. , E to control the multiplexers 4, 5, and 6 of the data processing unit 1.
[0026]
In this embodiment, at least three types of operation modes are enabled by changing the control states of the multiplexers 4, 5, and 6 using the data processing device having the above-described configuration. FIG. 2 shows the three types of operation modes.
[0027]
In FIG. 2, mode 1 is a mode in which the output of the memory 2 and the output of the memory 3 are input to the arithmetic unit 10 at the same timing without delaying the timing. That is, the multiplexer 5 in FIG. 1 selects the output of the memory 2, and the multiplexer 6 selects the output of the memory 3.
[0028]
Mode 2 is a case where the output of the memory 2 is processed with a delay of 1/2 machine cycle from the output of the memory 3 for processing. That is, in mode 2, the multiplexer 4 of FIG. 1 selects the output of the memory 2 and the multiplexer 5 selects the output of the latch circuit 7. The multiplexer 6 selects the output of the memory 3.
[0029]
Mode 3 is a case in which the output of the memory 3 is processed after being delayed by a half cycle of a machine cycle from the output of the memory 2. That is, in mode 3, the multiplexer 4 in FIG. 1 selects the output of the memory 3, and the multiplexer 6 selects the output of the latch circuit 7. The multiplexer 5 selects the output of the memory 2.
[0030]
Note that the code shown in FIG. 2 is a code assigned to specify each mode in the present embodiment, and is represented by a binary number. Mode 1 is “001”, mode 2 is “010”, and mode 3 is “100”.
[0031]
Next, a specific circuit example of the control means 11 in FIG. 1 will be described. 3 and 4 show a specific circuit inside the control means 11 and a part of the data processing apparatus shown in FIG. The same components and signals as those in FIG. 1 are denoted by the same reference numerals. The circuits shown in FIG. 3 and FIG. 4 enable mode switching even in the middle of data processing, instead of mode selection which was conventionally only possible at the start of data processing. The circuit is configured to select an appropriate mode.
[0032]
The relationship between the modes obtained by the circuit configurations shown in FIGS. 3 and 4 and the address values and signal values at that time will be described below. The start pulse used in the following description is a pulse for inputting a logical value “1” into the control unit 11 only at the start of data processing.
[0033]
・ Conditions for selecting mode 1 (any one of (1) to (5) must be satisfied)
(1) When the values of the registers 12 and 13 are even (ie, the output signals s12 and s13 of the registers 12 and 13 are both “0”) and the start pulse is received
(2) In the mode 2 mode, the match signal s16 of the comparator 16 is “1” (matching), and the last address of the cyclic address is an even number (that is, the output signal s15 of the register 15 is “0”). When
(3) When the coincidence signal s16 of the comparator 16 is “1” in the mode 3 mode and the last address of the cyclic address is an even number
(4) When the coincidence signal s16 of the comparator 16 is "1" and the last address of the cyclic address is an odd number (that is, the output signal s15 of the register 15 is "1") in the mode 1 mode
(5) When the coincidence signal s16 of the comparator 16 is “0” (not coincident) in the mode 1 state
-Conditions for selecting mode 2 (any one of (1) to (4) must be satisfied)
(1) When the value of the register 12 is even and the value of the register 13 is odd and the start pulse is received
(2) When the coincidence signal s16 of the comparator 16 is “1” in the mode 1 and the last address of the cyclic address is an even number
(3) When the coincidence signal s16 of the comparator 16 is “1” in the mode 2 state and the last address of the cyclic address is an odd number
(4) When the coincidence signal s16 of the comparator 16 is “0” in the mode 2 mode
-Conditions for selecting mode 3 (one of (1) to (3) should be satisfied)
(1) When the value of the register 12 is odd and the value of the register 13 is even and the start pulse is received
(2) When the coincidence signal s16 of the comparator 16 is "1" in the mode 3 mode and the last address of the cyclic address is an odd number
(3) When the coincidence signal s16 of the comparator 16 is "0" in the mode 3 mode
Switching from mode 1 to mode 3 is performed based on the above selection conditions, and can be specifically realized by the circuits shown in FIGS.
[0034]
First, FIG. 3 shows a logic circuit configured according to the above mode switching condition. In the figure, reference numeral 20 (20a, 20b, 20c) denotes a register holding the current mode in binary code, and each of 20a, 20b, 20c holds information of a total of 3 bits, one bit each. This code is the same as that shown in FIG. 2, and mode 1 is represented by a code of (20a, 20b, 20c) = “001”, mode 2 is represented by “010”, and mode 3 is represented by a code of “100”. These register values are input to the data processing unit 1 as the signals c, d, and e shown in FIG. 1 through the logic circuit shown in FIG. 4 and used for controlling the multiplexers 4 to 6 in the data processing unit 1. It is also used as data for changing the value of the register 20 (mode switching) and is input to the AND circuits M1, M2, and M3. In mode 1, that is, when the code is "001", the AND circuit M1 outputs "1". In the mode 2, that is, when the code is "010", the AND circuit M2 outputs "1". In the mode 3, that is, when the code is "100", the AND circuit M3 outputs "1".
[0035]
The signals input to each of the registers 20a to 20c include a start pulse, the least significant bit output s12 of the register 12, the least significant bit output s13 of the register 13, the least significant bit output s15 of the register 15, and the coincidence signal s16 of the comparator 16. , And a logical combination of the outputs of the AND circuits M1, M2, and M3, and a signal is formed so as to satisfy the mode selection condition described above.
[0036]
That is, when the condition for selecting the mode 1 is satisfied, only the output of the OR circuit 28 becomes “1”, and when the condition for selecting the mode 2 is satisfied, only the output of the OR circuit 24 becomes “1”. Is satisfied, only the output of the OR circuit 21 becomes “1”.
[0037]
For example, when the comparator 16 outputs the coincidence signal s16 in the state of the mode 2 and the last address of the cyclic address is an even number (that is, s15 is “0”), since the mode is the mode 2, the AND circuit M2 outputs “1”. Then, since s15 outputs "0" and s16 outputs "1", the AND circuit 35 outputs "1". Therefore, the AND circuit 31 outputs “1”, and “1” is input to the register 20 c via the OR circuit 28 and held. The other registers 20a and 20b are "0". As a result, the code held by the register 20 becomes “001”, which means that the mode 2 has been switched to the mode 1.
[0038]
With respect to other mode switching, the circuit shown in FIG. 3 can be switched as described above.
[0039]
FIG. 4 shows a specific circuit configuration for controlling the multiplexer in the data processing unit 1 according to the mode. FIG. 1 shows only a part of the data processing unit 1 for simplicity. As shown in the figure, the multiplexer 4 selects the left side (memory 2 side) when the control signal c is “1”, and selects the right side (memory 3 side) when the control signal c is “0”. I do. When the control signal d is "0", the multiplexer 5 selects the left side (memory 2 side) in the figure, and when the control signal d is "1", selects the right side (latch circuit 7 side) in the figure. Further, the multiplexer 6 selects the left side (the latch circuit 7 side) in the figure when the control signal e is "1", and selects the right side (the memory 3 side) in the figure when the control signal e is "0".
[0040]
Reference numeral 36 denotes an AND circuit that outputs “1” when the value of the register 20 is “010” (ie, mode 2), and 37 denotes “AND” when the value of the register 20 is “100” (ie, mode 3). This is an AND circuit that outputs "1".
[0041]
The operation of the circuit having the above configuration will be described. In the mode 1, the value of the register 20 is "001" and the output values of the AND circuits 36 and 37 are both "0". , D, and e are all “0”. Therefore, the multiplexer 5 selects the left side (that is, the memory 2 side) in the figure, and the multiplexer 6 selects the right side (that is, the memory 3 side) in the figure. With this control, in mode 1, the output data of the memory 2 and the memory 3 are input to the arithmetic unit without delay.
[0042]
In the mode 2, the value of the register 20 is “010”, the output value of the AND circuit 36 is “1”, and the output value of the AND circuit 37 is “0”, so that the control signals c and d are “1”. Thus, e is "0". Therefore, the multiplexer 4 selects the left side (ie, the memory 2 side) in the figure, the multiplexer 5 selects the right side (ie, the latch circuit 7 side) in the figure, and the multiplexer 6 selects the right side (ie, the memory 3 side) in the figure. I do. Thus, in mode 2, the data in the memory 2 is input to the arithmetic unit with a delay of 1/2 cycle.
[0043]
In the mode 3, the value of the register 20 is “100”, the output value of the AND circuit 36 is “0”, and the output value of the 37 is “1”, so that the control signals c and d are “0”. Thus, e is "1". Therefore, the multiplexer 4 selects the right side (ie, the memory 3 side) in the figure, the multiplexer 5 selects the left side (ie, the memory 2 side) in the figure, and the multiplexer 6 selects the left side (ie, the latch circuit 7 side). I do. Thus, in mode 3, the data in the memory 3 is input to the arithmetic unit with a delay of 1/2 cycle.
[0044]
As described above, the multiplexer can be controlled according to the mode switching, and the data input timing to the arithmetic unit 10 can be changed.
[0045]
Next, the operation of the above data processing apparatus in the case where a cyclic address is used for the memory 3 and a normal address is used for the memory 2 to read each data and perform an operation will be described.
[0046]
FIG. 5 is a timing chart of output data when normal addressing is used for the memory 2 and cyclic addressing is used for the memory 3. The memory 2 uses data from addresses 2m to 2m + 11, the memory 3 uses addresses circulating between addresses 2n to 2n + 4, and uses data from addresses 2n to 2n + 1 in the third cycle.
[0047]
First, at the start of the data processing, the start address 2n of the cyclic address is held in the register 13 of FIG. 1, and the last address 2n + 4 of the cyclic address is held in the register 15. Further, a register 12 serving as an address pointer holds an address 2m, and a register 13 holds an address 2n. The least significant bits of the address value held in the registers 12 and 13 are input to the control means 11 as signals s12 and s13. The control means 11 controls the multiplexers 4, 5, and 6 based on these signals. Here, since the addresses held in the two registers 12 and 13 are both even numbers and a start pulse indicating the start of data processing is output, the control means 11 selects mode 1 in FIG. That is, the data at the address 2m of the memory 2 is selected by the multiplexer 5 and input to the arithmetic unit 10 via the latch circuit 8, and the data at the address 2n of the memory 3 is selected by the multiplexer 6 and transmitted through the latch circuit 9. To the arithmetic unit 10 to calculate two data. Similarly, up to the first half of the third cycle of the machine cycle (basic cycle), as shown in FIG. The data is input to the calculator 10 and calculated.
[0048]
In the first half of the third machine cycle, data of address 2n + 4 is output from the memory 3. Since this address 2n + 4 is the last address of the cyclic address, the value of the register 13 matches the value of the register 15. , The comparator 16 outputs the coincidence signal s16. This coincidence signal s16 is input to the control means 11 and the adder 17. When receiving the coincidence signal s16 from the comparator 16, the control means 11 determines whether the address value of the register 15 is even or odd. In this embodiment, the address value of the register 15 (that is, the final address 2n + 4 of the cyclic address) is an even number. In the mode 1 state, when the coincidence signal s16 becomes “1” and the address value of the register 15 is an even number, the AND circuit M1 in FIG. 3 outputs “1”, and the AND circuit 35 outputs “1”. Output. As a result, the OR circuit 24 outputs “1” via the AND circuit 26, and the value of the register 20 becomes “010”. Since this code means mode 2, the control means 11 has switched the operation mode from mode 1 to mode 2. In FIG. 4, the control means 11 controls the multiplexer 4 to select the output of the memory 2 by the control signal c, and controls the multiplexer 5 to select the output of the latch circuit 7 by the control signal d. In addition, the control signal e controls the multiplexer 6 to select the output of the memory 3. As a result, a control state of mode 2 in which the data in the memory 2 is delayed by サ イ ク ル cycle can be realized.
[0049]
As described in the above mode selection condition, if the last address of the cyclic address is an odd number, the mode is not switched. In the case of double-speed reading in which an even address and an odd address are read in this order within one cycle, if the last address is an odd number, no extra data is read out next, so that the circuit smoothly goes around and reads the next top address. This is because the address can be read. For this reason, there is no need to delay by サ イ ク ル cycle, so that the mode is not switched.
[0050]
However, although different from this embodiment, when reading is performed in the order of an odd address and an even address within one cycle, the mode is switched when the last address of the cyclic address is an odd number, and the mode is switched when the last address is an even number. Is controlled so as not to switch.
[0051]
To explain the continuation of the operation, since the comparator 16 also outputs the coincidence signal to the adder 17, when the adder 17 receives the coincidence signal, it stops incrementing the address value of the register 13 and holds it in the register 14. The input address value (that is, the starting address 2n of the cyclic address) is input to the register 13. Thus, the address value of the register 13 can be circulated from the last address to the first address.
[0052]
In the second half of the third machine cycle in FIG. 3, since the operation mode has been switched to mode 2 as described above, the output of the memory 2 is input to the arithmetic unit 10 with a delay of 1/2 cycle. That is, the data at the address 2n + 5 in the memory 3 is input to the arithmetic unit 10 in the latter half of the third cycle of the machine cycle, but the data at the address 2m + 5 in the memory 2 is delayed by 1/2 cycle in the first half of the fourth cycle. Enter 10 Therefore, the data at address 2m + 5 in the memory 2 is input to the arithmetic unit 10 in synchronization with the data at address 2n in the memory 3, so that the data at the address 2m + 5 in the memory 2 and the data at address 2n in the memory 3 can be calculated. It becomes. In the second half of the third cycle of the machine cycle, only the data at address 2m + 5 of the memory 2 is input to the arithmetic unit 10, and the data is not aligned. Therefore, the arithmetic operation is stopped for a half cycle.
[0053]
Similarly, up to the first half of the six machine cycles, data of addresses 2m + 6 and 2n + 1, 2m + 7 and 2n + 2, 2m + 8 and 2n + 3, 2m + 9 and 2n + 4 are sequentially input to the arithmetic unit 10, It is calculated.
[0054]
In the first half of the sixth cycle, the address becomes the last address of the cyclic address again and is an even address. At this time, the mode is switched from the mode 2 to the mode 1, and the updating of the address pointer of the memory 2 from the sixth cycle to the seventh cycle is stopped, whereby the operation is stopped by １ ／ cycle. At the beginning of the seventh cycle, an operation is performed using data at addresses 2m + 10 and 2n. Since the seventh and subsequent cycles are in the mode 1 state, and the selection of each multiplexer is the same as at the start, the subsequent calculations can be continued in this manner.
[0055]
FIG. 6 shows a specific circuit configuration for stopping the updating of the address pointer of the memory 2 when shifting from the sixth cycle to the seventh cycle in FIG. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. Reference numeral 18 denotes an adder that increments and updates the address pointer of the memory 2. The signal a is input to the adder 18 to temporarily stop the increment operation to stop updating the address pointer. A register 15 holds the value of the least significant bit of the last address of the cyclic address and outputs this value as a signal s15. A comparator 16 outputs a coincidence signal s16 when the cyclic address of the register 13 becomes the last address. , 20 (20a, 20b, 20c) are registers holding the current mode state with the code shown in FIG. For example, in the case of mode 2, since the code is “010” as shown in FIG. 2, “0” is stored in the register 20a, “1” is stored in the register 20b, and “0” is stored in the register 20c. An AND circuit 39 receives the values of the registers 20a to 20c as inputs, and receives the inverted value of 20a, the value of 20b, and the inverted value of 20c. An AND circuit 38 receives the output value of the AND circuit 39, the coincidence signal s16 of the comparator 16, and the inverted value of the output signal s15 of the register 15.
[0056]
The register 20 and the AND circuits 38 and 39 among the circuits having the above configuration are provided in the control unit 11 in FIG. Hereinafter, the operation of this circuit will be described. In the first half of the sixth cycle in FIG. 5, since the state is the mode 2, "010" is held in the registers 20a, 20b, and 20c in order. Therefore, the AND circuit 39 outputs the logical value “1”. In the first half of the sixth cycle, since the address pointer indicates the last address 2n + 4 of the cyclic address, the comparator 16 outputs the coincidence signal s16 as the logical value “1”. Further, since the last address 2n + 4 held in the register 15 is an even number, the least significant bit is always "0" and the signal s15 is "0". Therefore, the AND circuit 38 inputs the signal of the logical value “1” to the adder 18 as the signal a. The adder 18 stops the increment operation while the signal a has the logical value “1”. At the next cycle (7th cycle), since the adder 18 has stopped operating, the register 12 in FIG. 1 does not update the address pointer. On the other hand, the address value of the register 13 in FIG. When the address of the register 13 is updated, the start address 2n of the cyclic address is reached, so that the comparator 16 stops outputting the coincidence signal, and s16 becomes "0". Therefore, the output signal a of the AND circuit 38 outputs a logical value “0”, so that the stop of the operation of the adder 18 is released, and the increment operation is restarted from the next cycle. As described above, when the address pointer indicates the even last address of the cyclic address in the mode 2 mode, the next address pointer update can be stopped for one cycle. As a result, as shown in FIG. 5, data at addresses 2m + 10 and 2n can be calculated in the first half of the seventh cycle, and normal calculations can be performed thereafter.
[0057]
【The invention's effect】
As described above, according to the present invention, even when a cyclic address is used for a data processing device for double-speed reading, data to be operated is not input to an arithmetic unit with a delay, and an accurate operation is always performed. Therefore, data processing can be executed efficiently.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a data processing device according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of each mode in the embodiment.
FIG. 3 is a configuration diagram of a mode switching circuit in the embodiment.
FIG. 4 is a configuration diagram of a multiplexer control circuit in the embodiment.
FIG. 5 is an operation timing chart of the data processing device in the embodiment.
FIG. 6 is a configuration diagram of an address pointer update stop circuit in the embodiment.
FIG. 7 is a configuration diagram of a conventional data processing device.
FIG. 8 is an operation timing chart of a conventional data processing device.
FIG. 9 is an operation timing chart of a conventional data processing device.
FIG. 10 is an operation timing chart of a conventional data processing device.
[Explanation of symbols]
1 Data processing unit
2,3 memory
4-6 multiplexer
7-9 Latch circuit
10 arithmetic unit
11 control means
12-15 registers
16 Comparators
17, 18 adder
20 registers
21, 24, 28, 33 OR circuit
22, 23, 25 to 27, 29 to 32, 34, 35 AND circuit
M1, M2, M3 AND circuit
36, 37 AND circuit
38, 39 AND circuit
101, 102 memory
103-105 multiplexer
106-108 Latch circuit
109 arithmetic unit

Claims (1)

First and second memories for storing data to be operated and continuously outputting data corresponding to two addresses of an even address and an odd address in the first half and the second half of one cycle, respectively ; In the data processing device in which the memory is read by the cyclic address ,
A computing unit that computes data output from the first memory and the second memory;
Delay means for delaying the timing at which either the output of the first memory or the second memory is input to the arithmetic unit;
Selecting means for selecting whether to input the output of the first memory and the second memory to the arithmetic unit via the delay means or to input to the arithmetic unit without passing through the delay means;
First address holding means functioning as an address pointer of the first memory;
A second address holding means functioning as an address pointer of the second memory;
The selecting means operates according to one of three operation modes,
In the first mode, both the output of the first memory and the output of the second memory are input to the arithmetic unit without passing through the delay means,
In the second mode, the output of the first memory is input to the arithmetic unit via the delay unit without passing the output of the first memory through the delay unit;
In a third mode, the output of the first memory is input to the arithmetic unit via the delay unit, and the output of the second memory is input to the arithmetic unit without passing through the delay unit;
When the cyclic address circulates from the last address to the first address,
When the last address of the cyclic address is an odd address, the operation mode is not converted in any operation mode,
When the last address of the cyclic address is an even address and the operation mode is the second mode, the operation mode is the first mode, when the operation mode is the third mode, the operation mode is the first mode, and the operation mode is the first mode. A data processing device, wherein the mode is converted to the second mode when in the mode .

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