JP3539528B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- JP3539528B2 JP3539528B2 JP1548296A JP1548296A JP3539528B2 JP 3539528 B2 JP3539528 B2 JP 3539528B2 JP 1548296 A JP1548296 A JP 1548296A JP 1548296 A JP1548296 A JP 1548296A JP 3539528 B2 JP3539528 B2 JP 3539528B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】
【発明の属する技術分野】
本発明は、半導体チップを有機プリント配線基板に搭載した半導体装置及びその製造方法に関し、ＭＰＵなど高周波動作特性の要求されるＬＳＩの実装に好適で、温度サイクルに対する信頼性が高く、かつ安価な多ピンパッケージ構造を提供する半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
従来、ＭＰＵやゲートアレイに用いる多ピンのＬＳＩパッケージには、半導体チップのボンデイングパッド部に共晶はんだのバンプを形成し、フェスダウンにて、対向するセラミックス基板の端子部とを溶融接合するフリップ実装方式が採用されてきた。
しかし、この方式によるパッケージは、セラミックス基板を用いるとマザーボードである有機プリント配線基板との線膨張係数の違いにより、温度サイクル時にセラミックス基板裏面にマトリックス状に配列されたはんだボールの外部端子と有機プリント基板端子部との接続部に応力が集中して破断し易いという問題があり、パッケージの大きさに限界があった。 これに、対処するためにセラミックス基板に替えて有機プリント基板を用いると、フリップチップボンディングされた半導体チップと有機プリント基板端子部とのバンプ接合部が温度サイクル時に破断し易いという問題があった。
【０００３】
これを避けるために、フェイスダウンで接続されたチップ表面全面と対向する有機プリント配線基板との間隙に液状の熱硬化性樹脂材料（アンダーフィル材）を含浸し、はんだバンプ接合部全面を被覆して、はんだバンプに集中する熱応力を分散させるという提案が、例えば特公昭63-64055、特公平5-66024などにてなされている。しかし、はんだバンプ接合部の高さ、すなはち、半導体チップと対向する基板との隙間は５０〜８０μｍと小さく、含浸すべきアンダーフィル材の含浸工程はボイドを発生させないようにするには工程時間がかかること、バッチ処理で多数個を同時に処理するにはその他の箇所をアンダーフィル材で汚さないようにするのが困難なこと、含浸性とアンダーフィル材の粘度には深い相関があるがアンダーフィル材の製造ロット毎の粘度の管理が煩雑なこと、さらに、接着すべきチップ表面と対向する基板表面がフリップチップボンディング時にフラックス等からのアウトガスで汚染されていて、汚染表面にも接着性に優れるアンダーフィル材を選定する必要のあること、その汚染物を洗浄するとすると微細な間隙を洗浄しなければならず煩雑な工程を追加する必要があること、など製造工程が増えること、かつ工程管理が煩雑なことなどの問題を残していた。
【０００４】
【発明が解決しようとする課題】
本発明が解決しようとする課題は、上記した従来技術の問題点を解決することにあり、はんだバンプによるフリップチップ実装方法による有機プリント配線基板を用いた多ピンパッケージの耐温度サイクル性および耐リフロー性を向上させるとともに、従来の液状のアンダーフィル材の含浸プロセスよりもより簡素なプロセスにより、高密度実装が可能で、かつ信頼性の高い半導体装置の構造およびその製造方法を提供することにある。
【０００５】
【課題を解決するための手段】
本発明は、半導体チップをフェイスダウンで有機プリント配線基板に搭載してなる半導体装置において、前記半導体チップの接続パッドとそれと対向する前記有機プリント配線基板の端子部とははんだで接合されており、前記半導体チップ表面と対向する有機プリント配線基板表面とは前記はんだ接合部より内側のみを有機接着性フィルムにて接着されており、前記はんだ接合部の全面と半導体チップの少なくとも端部が絶縁性有機封止材料で被覆されたおり、前記端子部と導通する外部端子を前記有機プリント配線基板の裏面にマトリックス状に配置してなる半導体装置である。
【０００６】
本発明の半導体装置の製造方法は、有機接着性フィルムを半導体チップの接続パッドの配列がなすＸＹ寸法より小さい寸法に切断する工程と、切断した前記有機接着性フィルムを有機プリント配線基板に加熱圧着する工程と、前記接続パッド部にあらかじめはんだによるバンプが形成されている半導体チップをフェイスダウンで対向する有機プリント配線基板端子部に位置合わせし加熱圧着して接合すると同時に前記有機接着性フィルムにより前記半導体チップと前記有機プリント配線基板表面とを接着する工程と、前記はんだ接合部の全面と半導体チップの少なくとも端部を有機絶縁性封止材料で封止する工程からなることを特徴とするものである。
【０００７】
すなわち本発明は、ボンディングパッド部に共晶はんだバンプが形成されている半導体チップを対向する有機プリント配線基板端子部にフリップチップボンディングした後に液状の熱硬化性樹脂を含浸するのではなく、予め、半導体チップのボンディングパッド部に形成されたはんだバンプ部の配列がなすＸＹ寸法より小さい寸法に切断された有機接着性フィルムをチップ搭載部に加熱圧着して仮圧着した有機プリント配線基板に、はんだバンプ付の半導体チップをフェイスダウンで対向する基板端子部に位置合わせし加熱圧着して、はんだバンプと基板端子部とを溶融接合すると同時にチップ表面と対向する基板面とを接着する、そして、チップ裏面全面もしくは１部を絶縁性有機封止材にて封止して、はんだバンプと基板端子部とのはんだ接合部の全面を被覆する構成とするものである。
【０００８】
【発明の実施の形態】
本発明に於いて、半導体チップを有機プリント配線基板に接着するために使用される有機接着性フィルムは、常温でフィルム状であり、はんだ溶融温度での加熱により溶融し強固な接着性をもち、高温時でも熱変形しにくい熱可塑性樹脂あるいは熱可塑性樹脂望と熱硬化性樹脂との複合体であることが好ましい。
【０００９】
はんだ溶融温度で短時間に硬化し、キュアー後には高温時の熱変形の少ない性能を持つ液状熱硬化性樹脂を予め基板に塗布してチップを熱圧着する方法も試みたが、この方法では塗布時に定量供給しても形状を揃えることが困難であり、チップの熱圧着時にボイドを巻き込むこと、熱圧着時に熱硬化性樹脂の流動を制御するのが困難であり、はんだバンプ接合部にまで流動してはんだ接合を阻害する場合がある。
一方、熱変形温度の高い熱可塑性樹脂を溶媒に溶かした接着剤を用いて予め基板に塗布し、乾燥工程をへて、チップ加熱圧着時の樹脂粘度を高粘度化する方法をも試みたが、残存溶媒を少なくすることが困難であり熱可塑性樹脂とチップパッシベーション膜との接着界面ないしは熱可塑性樹脂と基板表面との界面にボイドないしは部分剥離を形成しやすい。 残存溶媒が３重量％以上あり、ボイドないしは剥離面が接着面積比で１０％以上あると、吸湿したパッケージをはんだリフロー方式による面付け実装すると、ボイドないしは剥離面が起点となりクラックを生じる可能性が大きいことなどの問題がある。
【００１０】
したがって、本発明の有機接着性フィルムとしては、予めフィルム状に成形する工程で残存溶媒を極少化でき、膜厚が均一で、それ自体の吸湿率が小さい熱可塑性樹脂フィルムが使用される。さらに、はんだ溶融温度でのチップ接着時の加熱によるキュアーで３次元架橋が進行し強固な接着力が高温時でも保持できるという特徴をもつ、熱可塑性樹脂と熱硬化性樹脂を基材とする有機接着フィルムであることが望ましい。２００℃、２ｈｒ加熱後の残存揮発分が３重量％以下、８５℃、８５％ＲＨでの飽和吸湿率が１．０容量％以下、チップ加熱圧着後のＴｇ（ガラス転移温度）が１２０℃以上〜はんだ溶融温度２３０℃以下の、エポキシ樹脂を配合したアルキレンビストリメリテート系ポリイミド（アルキレンビストリメリテートと芳香族ジアミンとから合成されるポリイミド）フィルム、もしくは該基材にシリカなどの無機充填材料を配合・分散してなるフィルム状接着材料を構成材料とすることが望ましい。
【００１１】
使用する有機接着性フィルムの膜厚は、半導体チップに形成されたはんだバンプの高さ（パッシベーション膜の平面からバンプ先端部との距離）とするか、あるいは、チップの熱圧着時にはんだバンプと基板端子部との接触を十分に起こさせる目的で５μｍほど薄くしてもよい。しかし、はんだバンプ高さと同じ膜厚か、逆に５μｍ厚くすることが望ましい。このように設計することにより、チップの加熱圧着時には有機接着性フィルムは弾性変形してバンプ先端部と基板端子部との接触が可能であり、加熱圧着完了後のフィルムのスプリングバックにより、形成されるはんだバンプが球状から引き延ばされた柱状により近い形状になるので、はんだバンプ接続部にかかる熱応力に対してより強い接続部構造となることがわかった。
【００１２】
チップ表面に接着する有機接着性フィルムのＸＹ寸法は、チップのボンディングパッド部に形成されているはんだバンプの配列のなすＸＹ寸法よりも小さくする必要があるが、チップ端部よりＸ、Ｙ寸法ともに０．５ｍｍ以上小さくするとチップの実装工程の後に実施する封止工程での封止材の間隙への含浸が不十分になるので、 ０．１〜０．５ｍｍの範囲で小さくすることが望ましい。この有機接着性フイルムはチップ表面および基板表面と強固に接着して剪断方向の力に対向する働きを生じ、チップ表面を基板側に押しつける応力を発生し（硬化収縮含む）、温度サイクル時のはんだバンプにかかる集中応力を分散する働きがある。
【００１３】
有機接着性フィルムはチップ表面と基板との間隙を全部を充填せず、チップのボンディングパッド部と基板端子部を接合しているはんだバンプ部は、絶縁性有機封止材で被覆する構成とする。これに用いる封止材は、汎用のトランスファーモールド用のエポキシモールディングコンパウンドでもよいが、フィラーであるシリカの充填量が６５〜８０容量％ の範囲にあり、シリコン樹脂などのエラストマーが配合され、線膨張係数α１が１０から１７ｐｐｍで、ガラス転移温度Ｔｇが１２０℃以上の特性を持つ封止材で構成することが望ましい。特に５０μｍ程度の薄い間隙に充填させるために、フィラーのシリカの２５μｍ粒度以上がカットされた溶融シリカを用いた封止材がより望ましい。間隙に充填され、かつチップ裏面の全面もしくは１部を被覆した封止材は、チップ中央部を接着している有機接着性フィルムの熱変形を押さえ込み、ひいてははんだバンプにかかる集中応力を分散させる働きがある。
すなわち、はんだ接合部の全面と半導体チップの少なくとも端部は絶縁性有機封止材料で封止する。半導体チップの裏面部、端部、はんだ接合部の全面を含む半導体チップの全表面を絶縁性有機封止材料で封止するようにしても良い。
【００１４】
本発明による半導体装置を製造する方法は、従来のフリップチップボンディング後に液状のアンダーフィル材を含浸する方法とは違い、チップの基板への接着とチップと基板端子部へのはんだ接合を同時に実施するところに特徴がある。有機接着性フィルムを所定の寸法に切断し（切断工程）、該フィルムを有機プリント配線基板のチップ搭載部に熱プレスにて熱圧着する（仮圧着工程）。適切なフラックスを接続部に塗布したのち、フリップチップボンダーを用いて、はんだバンプ付きの半導体チップをフェイスダウンにして、バンプ位置と対向する基板端子部とを位置合わせして、熱圧着する（本圧着工程）。この本圧着工程にて、有機接着フィルムによるチップ表面と基板表面との接着とチップのバンプと基板端子部とのはんだ接合を同時に実施する。本圧着工程の後、通常のはんだリフロー装置にてはんだをリフローさせ、初期の接合部の位置ズレをはんだの表面張力の働きにより補正できる（リフロー工程）。その後、通常のトランスファーモールド設備・金型とモールデイングコンポウンドを用いて、もしくは、液状封止材にてチップ裏面全面もしくは一部を封止する（封止工程）。この段階で、はんだ接合部の全面が封止材で被覆される。ヒートシンクを取り付ける必要のあるデバイスについては、チップ中央部の裏面以外を封止して、形成されるキャビティー部に高熱伝導性接着剤にてヒートシンクを接着、固定する。
【００１５】
本発明で、残存揮発分、飽和吸湿率は次の方法で測定する。
残存揮発分測定方法
５０×５０ｍｍの大きさの有機接着性フィルムをサンプルとし、サンプルの重量を測定しＭ１とし、サンプルを熱風循環恒温槽中で２００℃２時間加熱後、秤量してＭ２とする。
［（Ｍ２−Ｍ１）／Ｍ１］×１００＝残存揮発分（重量％）
として、残存揮発分を算出した。
飽和吸湿率測定方法
直径１００ｍｍの円形有機接着性フィルムをサンプルとし、サンプルを真空乾燥機中で、１２０℃、３時間乾燥させ、デシケータ中で放冷後、乾燥重量を測定しＭ１とする。サンプルを８５℃、８５％ＲＨの恒温恒湿槽中で吸湿してから取り出し、すばやく秤量して秤量値が一定になったとき、その重量をＭ２とする。
［（Ｍ２−Ｍ１）／（Ｍ１／ｄ）］×１００＝飽和吸湿率（容量％）
として、飽和吸湿率を算出した。ｄは有機接着性フィルムの密度である。
【００１６】
【実施例】
実施例１
図１は、本発明による半導体装置の第１の実施例を示す縦断面図であり、図１に於いて、１ー１ははんだバンプ、１ー２は半導体チップ、１ー３は有機接着性フィルム、１ー４は封止材、１ー５は有機プリント配線基板の端子部、１ー６はスルーホール、１ー７はソルダレジスト、１ー８ははんだボールを示す。
図１に示した半導体装置を、図３ａ〜ｅに示した方法により製造した。図３ａ〜ｅに於いて、３ー１は有機プリント配線基板の端子部（１次側）、３ー２はソルダレジスト、３ー３はスルーホール、３ー４は有機プリント配線基板の端子部（２次側）、３ー５は有機接着性フイルム、３ー６ははんだバンプ、３ー７は半導体チップ、３ー８は封止材、３ー９ははんだボールを示す。
日立化成工業（株）製のＥ−６７９基材（ＦＲ−５相当品）をベースにして、Ｃｕ配線工程、スルーホールめっき、およびソルダレジスト工程を終えた基板（４層板、図３ａ）のチップ搭載部に、チップ面積（１５ｍｍ角）よりも小さくプレス切断した（１４．５ｍｍ角）、有機接着性フィルム（アルキレンビストリメリテート系ポリイミドフィルム、残存溶媒量３重量％以下、８５℃、８５％ＲＨでの飽和吸湿率が１容量％以下）を搭載し、温度２２０℃、加圧力３００ｇ／チップ、加圧時間５秒で仮圧着した（図３ｂ）。 該有機接着性フィルムの仮圧着された基板の端子部にフラックスを塗布・乾燥したのち、該基板および、高融点はんだバンプ付きの半導体チップをフリップチップボンダーに設置し、該チップをフェイスダウンにてはんだバンプ部と対向する基板端子部とを位置調整し、温度２３０℃、加圧力１０ｋｇ、加圧時間５秒で本圧着した。この時点で、はんだバンプと基板端子部との接合、および、チップ表面と基板との接着が同時に完了し、はんだバンプが柱状に引き延ばされているのが確認された。その後、通常のＩＲリフロー炉にて、２３０℃ ２０秒の条件ではんだをリフローした。この工程を経ることにより、フェイスダウンボンディングでの位置ズレが補正されていて、しかも柱状のはんだバンプ形状が維持されていることを確認した（図３ｃ
）。
その後、日立化成工業（株）製の封止材（エポキシモールディングコンパウンド：ＣＥＬ９２００）を用いて、通常のトランスファーモールド（成形温度１８０℃、成形圧力１５０ｋｇ／ｃｍ２）にてチップ裏面全面を被覆した封止品を得た（図３ｄ）。その後、はんだボール形成設備を用いて、はんだボールを基板裏面にアレイ状に形成して、完成品を得た（図３ｅ）。
この完成品のー６５℃〜１５０℃の耐温度サイクル性を評価した結果、１５００サイクル後のサンプルにおいても導通結果に異常はなく、はんだバンプの破断は認められなかった。サンプルを切断して、はんだバンプ部周辺を観察した結果、各はんだバンプの周辺全面、および、接着フィルムが被覆していないチップの外周部にまで封止材が充填・被覆されていることを確認した。さらに、３０℃、８５％ＲＨの条件で７２ｈｒ吸湿させた後、ＩＲリフロー（２３０℃、２０秒）したサンプルを超音波探査探傷設備で観察しても、接着フィルムと基板ソルダレジスト界面および接着フィルムとチップパッシベーション表面との界面での剥離やクラックの存在は認められなかった。
【００１７】
実施例２
図２は、本発明による半導体装置の第２の実施例を示す縦断面図であり、図２に於いて、２ー１ははんだバンプ付き半導体チップ、２ー２は有機接着性フィルム、２ー３は封止材、２ー４は高熱伝導接着剤、２ー５はヒートシンク板、２ー６は有機プリント配線基板の端子部、２ー７は有機プリント配線基板、２ー８ははんだボールを示す。
図２に示した半導体装置を図３のａ〜ｃおよびｆ〜ｈに示した方法により製造した。図３のａ〜ｃおよびｆ〜ｈに於いて、３ー１は有機プリント配線基板の端子部（１次側）、３ー２はソルダレジスト、３ー３はスルーホール、３ー４は有機プリント配線基板の端子部（２次側）、３ー５は有機接着性フイルム、３ー６ははんだバンプ、３ー７は半導体チップ、３ー８は封止材、３ー９ははんだボール、３ー１０は高熱伝導接着剤、３ー１１はヒートシンクを示す。
実施例１に記載したのと同じ方法で、４層基板にエポキシ樹脂を配合したアルキレンビストリメリテート系ポリイミドフィルムを仮接着し、チップをフェイスダウンボンディングするとともに対向する基板に本圧着した（図３ａ〜ｃ）。
上型のキャビティ部に突起を持つトランスファーモールド金型に、チップ搭載した基板を設置し、実施例１で用いたのと同じ封止材で封止してチップの裏面中央部がキャビティ状の封止成形品を得た（図３ｆ）。その後、このキャビティ部にヒートシンク板を高熱伝導接着剤にて接着固定した（図３ｇ）。その後、実施例１と同じはんだボール形成工程をへて半導体装置を得た（図３ｈ）。
【００１８】
比較例１
実施例１に記載した有機基板（４層板）のチップ搭載部に、液状の熱硬化エポキシ樹脂（アンダーフィル材、５０Ｐ（２５℃））を滴下し、７０℃、３０分加熱した後、温度２３０℃、加圧力１０ｋｇ、加圧時間５秒の条件でフリップチップボンディングした。フリップチップボンディング時に多くのガスの発生が認められ、断面を切断してはんだ接続部を観察した結果、１部はんだ接合部にまで樹脂が流れており、はんだ接合が出来ていない箇所があるとともに、基板界面でのボイドおよび剥離箇所が多いことが確認された。
【００１９】
比較例２
実施例１に記載した有機基板（４層板）のチップ搭載部に、熱可塑性のポリイミドアミド樹脂を溶剤に溶かしたタイプの液状接着剤を滴下し、７０℃ ３０分加熱、乾燥し、塗膜がチップのボンディングパッドの配列のなすＸＹ寸法よりも小さいことを確認したのち、温度２３０℃、加圧力１０ｋｇ、加圧時間５秒の条件でフリップチップボンディングした。比較例１と同様に、フリップチップボンディング時に多くのガスの発生が認められ、断面を切断してはんだ接続部を観察した結果、基板およびチップ界面での剥離箇所が多いことが確認された。
【００２０】
【発明の効果】
本発明の半導体装置およびその製造方法（請求項１、７、８、９）によると、熱可塑性樹脂系の有機接着フィルムを用いることにより、チップの基板への接着と基板端子部へのはんだ接合を同時に実施した構成をとっているので、従来の液状熱硬化性樹脂のアンダーフィル材を用いる方法に比べて、含浸工程にかかわる工程時間、洗浄工程および粘度管理などの煩雑な管理工程が不要となる。さらに、チップ裏面の全面もしくは外周部の１部、および、はんだバンプ全面が封止材で被覆される構造であるが故に、チップ表面と基板表面との間隙のみを充填する従来の構造よりも縦方向の応力の緩和を阻害するので、パッケージの温度サイクル時のはんだバンプに集中する応力を分散する働きをより保持し、耐温度サイクル性が優れる。
さらに、構成材料である有機接着性フィルムは、従来の液状アンダーフィル材と違って、フィルム化する工程で溶媒を乾燥させ残存溶媒の量を３重量％以下に制御していること（請求項２、３、１０、１１）、および接着性に優れるアルキレンビストリメリテート系ポリイミドを用いているために（請求項４、１２）、チップのパッシベーション膜および基板のソルダレジスト面への接着性が優れ、接着剥離やボイドの発生はなく、パッケージの吸湿耐リフロークラック性が優れる。
【図面の簡単な説明】
【図１】本発明の第１の実施例の半導体装置の断面図である。
【図２】本発明の第２の実施例の半導体装置の断面図である。
【図３】本発明の半導体装置の製造法を示す断面図である。
【符号の説明】
１ー１．はんだバンプ
１ー２．半導体チップ
１ー３．有機接着性フィルム
１ー４．封止材
１ー５．有機プリント配線基板の端子部
１ー６．スルーホール
１ー７．ソルダレジスト
１ー８．はんだボール
２ー１．はんだバンプ付き半導体チップ
２ー２．有機接着性フィルム
２ー３．封止材
２ー４．高熱伝導接着剤
２ー５．ヒートシンク板
２ー６．有機プリント配線基板の端子部
２ー７．有機プリント配線基板
２ー８．はんだボール
３ー１．有機プリント配線基板の端子部（１次側）
３ー２．ソルダレジスト
３ー３．スルーホール
３ー４．有機プリント配線基板の端子部（２次側）
３ー５．有機接着性フイルム
３ー６．はんだバンプ
３ー７．半導体チップ
３ー８．封止材
３ー９．はんだボール
３ー１０．高熱伝導接着剤
３ー１１．ヒートシンク[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor chip is mounted on an organic printed wiring board and a method of manufacturing the same, which is suitable for mounting an LSI requiring high frequency operation characteristics such as an MPU, has high reliability with respect to a temperature cycle, and is inexpensive. The present invention relates to a semiconductor device providing a pin package structure and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, in multi-pin LSI packages used for MPUs and gate arrays, eutectic solder bumps are formed on the bonding pads of semiconductor chips, and flip-down is performed by means of meltdown between the terminals of the opposing ceramic substrate at the festival time. Mounting methods have been adopted.
However, when a package using this method is used, the external terminals of the solder balls arranged in a matrix on the back surface of the ceramic substrate during temperature cycling and the organic printed circuit are different due to the difference in the coefficient of linear expansion from the organic printed wiring board that is the motherboard when the ceramic substrate is used. There is a problem that stress concentrates on a connection portion with the board terminal portion and the connection portion is easily broken, and the size of the package is limited. If an organic printed circuit board is used instead of the ceramic substrate to cope with this, there is a problem that the bump joint between the flip-chip bonded semiconductor chip and the organic printed circuit board terminal section is easily broken during a temperature cycle.
[0003]
In order to avoid this, a liquid thermosetting resin material (underfill material) is impregnated into the gap between the entire surface of the chip connected face down and the organic printed wiring board facing it, and the entire surface of the solder bump joint is covered. For example, proposals for dispersing the thermal stress concentrated on the solder bumps have been made, for example, in Japanese Patent Publication Nos. 63-64055 and 5-66024. However, the height of the solder bump joint, that is, the gap between the semiconductor chip and the opposing substrate is as small as 50 to 80 μm, and the step of impregnating the underfill material to be impregnated is a step for preventing generation of voids. Although it takes time, it is difficult to treat other parts with the underfill material in batch processing at the same time, and there is a deep correlation between the impregnation property and the viscosity of the underfill material. Viscosity management for each production lot of underfill material is complicated, and the substrate surface facing the chip surface to be bonded is contaminated by outgas from flux etc. during flip chip bonding, and adhesion to the contaminated surface It is necessary to select an underfill material that is excellent in quality, and when cleaning contaminants, fine gaps must be cleaned and complicated That extent there is a need to add, such as that the manufacturing process is increased, and process management had left a problem such as that complicated.
[0004]
[Problems to be solved by the invention]
The problem to be solved by the present invention is to solve the above-mentioned problems of the prior art, and the temperature cycle resistance and reflow resistance of a multi-pin package using an organic printed wiring board by a flip-chip mounting method using solder bumps It is an object of the present invention to provide a highly reliable semiconductor device structure capable of high-density mounting by a process simpler than a conventional liquid underfill material impregnation process, and a method for manufacturing the same, while improving reliability. .
[0005]
[Means for Solving the Problems]
According to the present invention, in a semiconductor device in which a semiconductor chip is mounted face down on an organic printed wiring board, a connection pad of the semiconductor chip and a terminal portion of the organic printed wiring board facing the connection pad are joined by solder, The surface of the organic printed wiring board facing the semiconductor chip is adhered only with an organic adhesive film on the inner side from the solder joint, and the entire surface of the solder joint and at least the end of the semiconductor chip are made of an insulating organic material. A semiconductor device in which external terminals covered with a sealing material and electrically connected to the terminal portions are arranged in a matrix on the back surface of the organic printed wiring board.
[0006]
The method of manufacturing a semiconductor device according to the present invention includes a step of cutting the organic adhesive film into dimensions smaller than the XY dimensions formed by the arrangement of the connection pads of the semiconductor chip, and heat-pressing the cut organic adhesive film to an organic printed wiring board. And a step of aligning the semiconductor chip, in which solder bumps are formed in advance on the connection pad portion, face-to-face with the opposing organic printed wiring board terminal portion, and bonding by heating and pressing at the same time with the organic adhesive film. A step of bonding a semiconductor chip to the surface of the organic printed wiring board, and a step of sealing at least an end of the semiconductor chip and the entire surface of the solder joint with an organic insulating sealing material. is there.
[0007]
That is, the present invention does not impregnate a liquid thermosetting resin after flip-chip bonding a semiconductor chip having a eutectic solder bump formed on a bonding pad portion to an opposing organic printed wiring board terminal portion. An organic adhesive film cut into dimensions smaller than the XY dimensions formed by the arrangement of the solder bumps formed on the bonding pads of the semiconductor chip is heat-pressed onto the chip mounting part and temporarily pressed on the organic printed wiring board to form an organic printed wiring board. The semiconductor chip attached is positioned face-down to the opposing substrate terminal and heated and press-bonded to melt-bond the solder bump and the substrate terminal and simultaneously bond the chip surface to the opposing substrate surface. Seal the entire surface or a part with an insulating organic sealing material, and solder the solder bumps to the board terminals. It is an arrangement which covers the entire surface of the joint.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, the organic adhesive film used for bonding the semiconductor chip to the organic printed wiring board is a film at room temperature, has a strong adhesive property when melted by heating at a solder melting temperature, It is preferable to use a thermoplastic resin which is hardly thermally deformed even at a high temperature or a composite of a thermoplastic resin and a thermosetting resin.
[0009]
Attempts have been made to apply a liquid thermosetting resin, which cures in a short time at the solder melting temperature and has little thermal deformation at high temperature after curing, to the substrate in advance and heat-compress the chip. It is difficult to make the shape uniform even when supplying a fixed amount sometimes, and it is difficult to control the flow of the thermosetting resin during the thermocompression bonding due to the inclusion of voids at the time of thermocompression bonding of the chip. In some cases, solder joining may be hindered.
On the other hand, a method of applying a thermoplastic resin having a high heat deformation temperature to a substrate in advance using an adhesive obtained by dissolving the same in a solvent, and then performing a drying process to increase the resin viscosity at the time of heat-press bonding of the chip was also attempted. It is difficult to reduce the residual solvent, and it is easy to form voids or partial peeling at the adhesive interface between the thermoplastic resin and the chip passivation film or at the interface between the thermoplastic resin and the substrate surface. When the residual solvent is 3% by weight or more and the void or the peeled surface is 10% or more in the bonding area ratio, when the moisture-absorbed package is mounted and mounted by the solder reflow method, the void or the peeled surface may be a starting point and a crack may occur. There is a problem such as being large.
[0010]
Therefore, as the organic adhesive film of the present invention, a thermoplastic resin film which can minimize the residual solvent in the step of forming into a film in advance, has a uniform thickness, and has a low moisture absorption rate per se is used. Furthermore, organic materials based on thermoplastic resin and thermosetting resin have the characteristic that three-dimensional crosslinking progresses by curing by heating at the time of chip bonding at the solder melting temperature, and a strong adhesive force can be maintained even at high temperatures. Desirably, it is an adhesive film. Residual volatile matter after heating at 200 ° C. for 2 hours is 3% by weight or less, saturation moisture absorption at 85 ° C. and 85% RH is 1.0% by volume or less, and Tg (glass transition temperature) after chip heating and pressing is 120 ° C. or more ~ An epoxy resin-blended alkylene bis trimellitate-based polyimide (polyimide synthesized from alkylene bis trimellitate and aromatic diamine) film having a solder melting temperature of 230 ° C or less, or an inorganic filler material such as silica as the base material It is desirable to use a film-like adhesive material that is blended and dispersed as a constituent material.
[0011]
The thickness of the organic adhesive film used should be the height of the solder bumps formed on the semiconductor chip (the distance from the plane of the passivation film to the tip of the bumps), or the solder bumps and the substrate should be used when the chip is thermocompressed. The thickness may be reduced by about 5 μm in order to cause sufficient contact with the terminal portion. However, it is desirable that the thickness be the same as the height of the solder bumps or 5 μm thick. By designing in this way, the organic adhesive film is elastically deformed at the time of thermocompression bonding of the chip, and the contact between the tip of the bump and the terminal of the substrate is possible, and the film is formed by springback of the film after completion of thermocompression bonding. It has been found that since the solder bumps have a shape closer to the columnar shape extended from the spherical shape, the connection structure has a stronger resistance to the thermal stress applied to the solder bump connection portion.
[0012]
The XY dimensions of the organic adhesive film that adheres to the chip surface must be smaller than the XY dimensions of the arrangement of the solder bumps formed on the bonding pad portion of the chip. If the thickness is reduced by 0.5 mm or more, the impregnation of the gap of the sealing material in the sealing step performed after the chip mounting step becomes insufficient. Therefore, it is desirable to reduce the diameter in the range of 0.1 to 0.5 mm. This organic adhesive film adheres firmly to the chip surface and the substrate surface, and acts to oppose the force in the shear direction, generating stress that presses the chip surface to the substrate side (including curing shrinkage), and the solder during the temperature cycle. It has the function of dispersing the concentrated stress applied to the bump.
[0013]
The organic adhesive film does not completely fill the gap between the chip surface and the substrate, and the solder bumps joining the chip bonding pad and substrate terminals are covered with an insulating organic sealing material. . The sealing material used for this may be an epoxy molding compound for general-purpose transfer molding, but the filler as a filler is in the range of 65 to 80% by volume, and an elastomer such as a silicone resin is compounded, and linear expansion is performed. It is desirable to use a sealing material having a coefficient α1 of 10 to 17 ppm and a glass transition temperature Tg of 120 ° C. or more. In particular, in order to fill a gap as thin as about 50 μm, a sealing material using fused silica in which the filler silica has a particle size of 25 μm or more is more preferably used. The sealing material filled in the gap and covering the entire surface or a part of the back surface of the chip suppresses the thermal deformation of the organic adhesive film bonding the central portion of the chip, thereby dispersing the concentrated stress applied to the solder bumps. There is.
That is, the entire surface of the solder joint and at least the end of the semiconductor chip are sealed with an insulating organic sealing material. The entire surface of the semiconductor chip, including the back surface, the end, and the entire surface of the solder joint, may be sealed with an insulating organic sealing material.
[0014]
The method of manufacturing a semiconductor device according to the present invention is different from the conventional method of impregnating a liquid underfill material after flip chip bonding, in which the bonding of the chip to the substrate and the solder bonding of the chip and the terminal of the substrate are simultaneously performed. There is a characteristic. The organic adhesive film is cut into a predetermined size (cutting step), and the film is thermocompression-bonded to a chip mounting portion of an organic printed wiring board by a hot press (temporary pressure bonding step). After applying an appropriate flux to the connection part, the semiconductor chip with solder bumps is face down using a flip chip bonder, the bump position and the opposing board terminal part are aligned, and thermocompression bonding is performed. Crimping process). In the final pressure bonding step, the bonding between the chip surface and the substrate surface by the organic adhesive film and the solder bonding between the chip bumps and the substrate terminal are simultaneously performed. After the final pressure bonding step, the solder is reflowed by a normal solder reflow device, and the initial positional deviation of the joint can be corrected by the function of the surface tension of the solder (reflow step). Thereafter, the whole or a part of the back surface of the chip is sealed using a normal transfer molding equipment / mold and a molding compound, or with a liquid sealing material (sealing step). At this stage, the entire surface of the solder joint is covered with the sealing material. For a device that requires a heat sink to be attached, a portion other than the back surface of the central portion of the chip is sealed, and the heat sink is bonded and fixed to the cavity to be formed with a high thermal conductive adhesive.
[0015]
In the present invention, the remaining volatile components and the saturated moisture absorption are measured by the following methods.
Residual volatile content measuring method An organic adhesive film having a size of 50 × 50 mm was used as a sample, and the weight of the sample was measured to be M1. The sample was heated in a hot-air circulating thermostat at 200 ° C. for 2 hours and weighed to be M2. .
[(M2-M1) / M1] × 100 = remaining volatile matter (% by weight)
Was calculated as the residual volatile matter.
Saturation Moisture Absorption Measurement Method A circular organic adhesive film having a diameter of 100 mm was used as a sample, the sample was dried in a vacuum drier at 120 ° C. for 3 hours, and allowed to cool in a desiccator. The sample is taken out after absorbing the moisture in a constant temperature and humidity chamber of 85 ° C. and 85% RH, and is quickly weighed. When the weighed value becomes constant, the weight is defined as M2.
[(M2-M1) / (M1 / d)] × 100 = saturated moisture absorption (volume%)
The saturation moisture absorption was calculated as follows. d is the density of the organic adhesive film.
[0016]
【Example】
Example 1
FIG. 1 is a longitudinal sectional view showing a first embodiment of a semiconductor device according to the present invention. In FIG. 1, 1-1 denotes a solder bump, 1-2 denotes a semiconductor chip, and 1-3 denotes an organic adhesive. Film 1-4, a sealing material, 1-5 a terminal portion of an organic printed wiring board, 1-6 a through hole, 1-7 a solder resist, and 1-8 a solder ball.
The semiconductor device shown in FIG. 1 was manufactured by the method shown in FIGS. 3A to 3E, 3-1 is a terminal portion (primary side) of the organic printed wiring board, 2-2 is a solder resist, 3-3 is a through hole, and 3-4 is a terminal portion of the organic printed wiring board. (Secondary side), 3-5 indicates an organic adhesive film, 3-6 indicates a solder bump, 3-7 indicates a semiconductor chip, 3-8 indicates a sealing material, and 3-9 indicates a solder ball.
Based on an E-679 base material (FR-5 equivalent) manufactured by Hitachi Chemical Co., Ltd., a substrate (four-layer plate, FIG. 3A) that has been subjected to the Cu wiring process, through-hole plating, and solder resist processes The chip mounting portion was press-cut (14.5 mm square) smaller than the chip area (15 mm square), an organic adhesive film (alkylene bis trimellitate-based polyimide film, residual
).
Thereafter, using a sealing material (epoxy molding compound: CEL9200) manufactured by Hitachi Chemical Co., Ltd., the entire back surface of the chip was covered with a normal transfer mold (molding temperature 180 ° C., molding pressure 150 kg / cm 2). A product was obtained (FIG. 3d). Thereafter, the solder balls were formed in an array on the back surface of the substrate by using a solder ball forming equipment to obtain a finished product (FIG. 3E).
As a result of evaluating the temperature cycling resistance of the completed product at -65 ° C to 150 ° C, even in the sample after 1500 cycles, there was no abnormality in the conduction result, and no breakage of the solder bump was observed. After cutting the sample and observing the area around the solder bumps, it was confirmed that the sealing material was filled and covered all over the periphery of each solder bump and the outer periphery of the chip not covered with the adhesive film. did. Furthermore, even if the sample subjected to IR reflow (230 ° C., 20 seconds) after absorbing moisture for 72 hours under the conditions of 30 ° C. and 85% RH was observed with an ultrasonic inspection equipment, the interface between the adhesive film and the substrate solder resist and the adhesive film No peeling or cracks were found at the interface between the chip and the chip passivation surface.
[0017]
Example 2
FIG. 2 is a longitudinal sectional view showing a second embodiment of the semiconductor device according to the present invention. In FIG. 2, 2-1 is a semiconductor chip with solder bumps, 2-2 is an organic adhesive film, 3 is a sealing material, 2-4 is a high thermal conductive adhesive, 2-5 is a heat sink plate, 2-6 is a terminal portion of an organic printed wiring board, 2-7 is an organic printed wiring board, and 2-8 is a solder ball. Show.
The semiconductor device shown in FIG. 2 was manufactured by the method shown in FIGS. In FIGS. 3A to 3C and 3F to 3H, 3-1 is a terminal portion (primary side) of the organic printed wiring board, 3-2 is a solder resist, 3-3 is a through hole, and 3-4 is an organic layer. Terminal part (secondary side) of printed wiring board, 3-5 is an organic adhesive film, 3-6 is a solder bump, 3-7 is a semiconductor chip, 3-8 is a sealing material, 3-9 is a solder ball, Reference numeral 3-10 denotes a high thermal conductive adhesive, and reference numeral 3-11 denotes a heat sink.
In the same manner as described in Example 1, an alkylenebistrimellitate-based polyimide film containing an epoxy resin was temporarily bonded to a four-layer substrate, and the chip was face-down bonded and fully press-bonded to the opposing substrate (FIG. 3a). ~ C).
The substrate on which the chip is mounted is placed in a transfer mold having projections in the cavity of the upper mold, and sealed with the same sealing material as used in Example 1, and the center of the back surface of the chip is sealed with a cavity. A molded product was obtained (FIG. 3f). Thereafter, a heat sink plate was bonded and fixed to the cavity with a high thermal conductive adhesive (FIG. 3g). Thereafter, the semiconductor device was obtained through the same solder ball forming process as in Example 1 (FIG. 3H).
[0018]
Comparative Example 1
A liquid thermosetting epoxy resin (underfill material, 50P (25 ° C.)) was dropped on the chip mounting portion of the organic substrate (four-layer plate) described in Example 1, and heated at 70 ° C. for 30 minutes. Flip chip bonding was performed under the conditions of 230 ° C., a pressure of 10 kg, and a pressing time of 5 seconds. A lot of gas was generated during flip chip bonding, and the cross section was cut and the solder connection was observed.As a result, the resin flowed to the first solder joint, and there were places where solder bonding was not possible, It was confirmed that there were many voids and peeling points at the substrate interface.
[0019]
Comparative Example 2
A liquid adhesive of a type obtained by dissolving a thermoplastic polyimide amide resin in a solvent was dropped on the chip mounting portion of the organic substrate (four-layer plate) described in Example 1, and heated and dried at 70 ° C. for 30 minutes to form a coating film. Was confirmed to be smaller than the XY dimensions formed by the array of bonding pads on the chip, and then flip-chip bonding was performed at a temperature of 230 ° C., a pressure of 10 kg, and a pressing time of 5 seconds. As in Comparative Example 1, a large amount of gas was generated at the time of flip chip bonding, and the cross section was cut to observe the solder connection portion. As a result, it was confirmed that there were many peeled portions at the interface between the substrate and the chip.
[0020]
【The invention's effect】
According to the semiconductor device of the present invention and the method of manufacturing the same (claims 1, 7, 8, and 9), by using a thermoplastic resin-based organic adhesive film, the chip is bonded to the substrate and the solder is bonded to the terminal of the substrate. Since the configuration is implemented at the same time, compared to the conventional method using an underfill material of liquid thermosetting resin, there is no need for complicated management processes such as the process time related to the impregnation process, the cleaning process and the viscosity management. Become. Furthermore, since the entire surface of the chip back surface or a part of the outer peripheral portion and the entire surface of the solder bumps are covered with a sealing material, the structure is more vertical than the conventional structure in which only the gap between the chip surface and the substrate surface is filled. Since the relaxation of the stress in the direction is impeded, the function of dispersing the stress concentrated on the solder bumps during the temperature cycle of the package is further maintained, and the temperature cycle resistance is excellent.
Furthermore, unlike the conventional liquid underfill material, the organic adhesive film as a constituent material is obtained by drying the solvent in the step of forming a film and controlling the amount of the remaining solvent to 3% by weight or less. , 3, 10, 11) and the use of an alkylenebistrimellitate-based polyimide having excellent adhesiveness (claims 4 and 12), the adhesiveness to the passivation film of the chip and the solder resist surface of the substrate is excellent, There is no adhesion peeling or voids, and the package has excellent moisture absorption and reflow crack resistance.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
[Explanation of symbols]
1-1. Solder bump 1-2. Semiconductor chip 1-3. Organic adhesive film 1-4. Sealing material 1-5. Terminal part of organic printed wiring board 1-6. Through hole 1-7. Solder resist 1-8. Solder ball 2-1. Semiconductor chip with solder bump 2-2. Organic adhesive film 2-3. Sealant 2-4. High thermal conductive adhesive 2-5. Heat sink plate 2-6. Terminal part of organic printed wiring board 2-7. Organic printed wiring board 2-8. Solder ball 3-1. Terminal part of organic printed wiring board (primary side)
3-2. Solder resist 3-3. Through hole 3-4. Terminal part of organic printed wiring board (secondary side)
3-5. Organic adhesive film 3-6. Solder bump 3-7. Semiconductor chip 3-8. Sealing material 3-9. Solder ball 3-10. High thermal conductive adhesive 3-11. heatsink
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1548296A JP3539528B2 (en) | 1996-01-31 | 1996-01-31 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1548296A JP3539528B2 (en) | 1996-01-31 | 1996-01-31 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09213741A JPH09213741A (en) | 1997-08-15 |
| JP3539528B2 true JP3539528B2 (en) | 2004-07-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1548296A Expired - Lifetime JP3539528B2 (en) | 1996-01-31 | 1996-01-31 | Semiconductor device and manufacturing method thereof |
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| JP (1) | JP3539528B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998046811A1 (en) | 1997-04-17 | 1998-10-22 | Sekisui Chemical Co., Ltd. | Conductive particles and method and device for manufacturing the same, anisotropic conductive adhesive and conductive connection structure, and electronic circuit components and method of manufacturing the same |
| US6159721A (en) * | 1997-08-20 | 2000-12-12 | Hercules Incorporated | Amine modified polysaccharides |
| JP2012009713A (en) * | 2010-06-25 | 2012-01-12 | Shinko Electric Ind Co Ltd | Semiconductor package and method of manufacturing the same |
| JP5384443B2 (en) | 2010-07-28 | 2014-01-08 | 日東電工株式会社 | Flip chip type semiconductor back film, dicing tape integrated semiconductor back film, semiconductor device manufacturing method, and flip chip type semiconductor device |
| TW201341199A (en) | 2011-12-12 | 2013-10-16 | Nitto Denko Corp | Laminated sheet and method for manufacturing semiconductor device using laminated sheet |
| CN105895539B (en) * | 2016-06-08 | 2018-08-10 | 华进半导体封装先导技术研发中心有限公司 | Flip-chip encapsulates intermediate structure and flip-chip packaged structure and flip-chip packaged method |
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1996
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