JP3534879B2 - Semiconductor device using three-dimensional quantum confinement - Google Patents
Semiconductor device using three-dimensional quantum confinementInfo
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- JP3534879B2 JP3534879B2 JP6101895A JP6101895A JP3534879B2 JP 3534879 B2 JP3534879 B2 JP 3534879B2 JP 6101895 A JP6101895 A JP 6101895A JP 6101895 A JP6101895 A JP 6101895A JP 3534879 B2 JP3534879 B2 JP 3534879B2
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Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、3次元的に量子閉じ込めを行う量子箱構造により量
子力学的効果を有する半導体装置に関する。なお、本明
細書中で量子箱とは、3次元的に量子閉じ込めを行うこ
とができる構造を有するものをいい、必ずしも箱状の形
状を有するもののみならず楕円球状等その他の形状を有
するものも含む。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a quantum mechanical effect due to a quantum box structure which three-dimensionally confine quantum confinement. In the present specification, the quantum box means one having a structure capable of performing quantum confinement three-dimensionally, and not only one having a box shape, but also another shape such as an elliptic sphere. Also includes.
【0002】半導体プロセスの進歩に伴い、半導体装置
の作製にナノスケールの薄膜成長技術、微細加工技術が
利用されるようになった。この薄膜成長技術、微細加工
技術によって回路の集積度を上げ、量子力学的効果を利
用した歪量子井戸レーザ等を実用化してきた。With the progress of semiconductor processes, nanoscale thin film growth technology and microfabrication technology have come to be used for manufacturing semiconductor devices. The thin film growth technology and the microfabrication technology have increased the degree of circuit integration, and have put into practical use strained quantum well lasers and the like utilizing the quantum mechanical effect.
【0003】[0003]
【従来の技術】従来の半導体装置は、フォトリソグラフ
ィ技術による微細加工の限界や、多くの電子が移動する
ために生じる発熱により、集積度の限界が指摘されてい
る。また、半導体レーザの特性に対する要求も厳しくな
っており、近年では大きな温度変化に対して安定動作可
能な半導体レーザが要求されている。歪量子井戸レーザ
では、この厳しい要求に応えることは困難である。2. Description of the Related Art It has been pointed out that a conventional semiconductor device has a limit of degree of integration due to a limit of fine processing by a photolithography technique and heat generation caused by movement of many electrons. Further, the demands on the characteristics of the semiconductor laser have become strict, and in recent years, a semiconductor laser capable of operating stably against a large temperature change has been demanded. It is difficult for strained quantum well lasers to meet this strict requirement.
【0004】これらの要求は、理論的に、3次元的に量
子閉じ込めを行う量子箱構造により解決されるものと考
えられている。1つの量子箱の中には電子が2個(場合
によっては数個)しか入ることができない。その状態密
度は、理想的にはデルタ関数的に、ある波数ベクトルに
局在する。例えば、光半導体装置においては、そのデル
タ関数的状態密度によって高効率の光変調器の作製が可
能になる。半導体レーザについても、キャリアの温度分
布が抑制されるため微分利得が向上して温度特性が改善
できると考えられる。It is considered that these requirements are theoretically solved by a quantum box structure that performs quantum confinement in three dimensions. Only two electrons (sometimes several) can enter one quantum box. The density of states is localized in a wave vector, ideally in a delta function. For example, in an optical semiconductor device, a highly efficient optical modulator can be manufactured due to its delta function density of states. With respect to the semiconductor laser as well, it is considered that since the temperature distribution of carriers is suppressed, the differential gain is improved and the temperature characteristics can be improved.
【0005】量子箱構造を実現する方法として、従来の
微細加工技術をさらに発展させた各種の方法が提案され
ている。例えば、電子線を用いたリソグラフィによる方
法、マスクパターン上に積み上げたピラミッド型の結晶
の頂上付近を量子箱構造とする方法、微傾斜基板上にお
ける成長初期の横方向成長を利用する方法、STM技術
を応用した原子マニピュレーションによる方法等であ
る。As a method for realizing a quantum box structure, various methods which have further developed conventional fine processing techniques have been proposed. For example, a method using lithography using an electron beam, a method of forming a quantum box structure near the top of a pyramid-shaped crystal stacked on a mask pattern, a method of utilizing lateral growth in the initial stage of growth on a sloping substrate, and an STM technique. Is a method based on atomic manipulation applied to.
【0006】[0006]
【発明が解決しようとする課題】量子箱構造特有の量子
力学的効果を生かすためには、量子箱のサイズを原子ス
ケールまで均一化することが重要となる。しかし、従来
の微細加工技術を発展させた量子箱の形成方法では、人
為的に結晶を加工するため、加工サイズのばらつきを原
子スケールまで抑えることが困難である。In order to take advantage of the quantum mechanical effect peculiar to the quantum box structure, it is important to make the size of the quantum box uniform up to the atomic scale. However, it is difficult to suppress variations in processing size to the atomic scale because the crystal is artificially processed by the method of forming a quantum box, which is a development of the conventional fine processing technology.
【0007】また、装置が複雑となり、多段階の加工プ
ロセスが必要であるため、工業的生産に適さない。さら
に、多段階の加工プロセスにより、不純物の混入、転
位、原子空孔等の結晶欠陥の発生等による結晶品質の低
下が避けられない。Further, the apparatus is complicated and requires a multi-step processing process, which is not suitable for industrial production. Further, due to the multi-step processing process, deterioration of crystal quality due to inclusion of impurities, generation of crystal defects such as dislocations and atomic vacancies is unavoidable.
【0008】本発明の目的は、比較的簡便な製造工程で
作製できる量子箱構造を有する半導体装置を提供するこ
とである。An object of the present invention is to provide a semiconductor device having a quantum box structure which can be manufactured by a relatively simple manufacturing process.
【0009】[0009]
【課題を解決するための手段】本発明の半導体装置は、
半導体表面を有する基板と、前記半導体表面の上に形成
され、面内方向の格子歪を有する半導体結晶からなるバ
ッファ層と、前記バッファ層の上に散点状に配置され、
面内方向の格子歪を有する半導体結晶からなる微結晶体
とを有し、前記バッファ層の格子歪と前記微結晶体の格
子歪のうち一方は伸び歪、他方は縮み歪である。The semiconductor device of the present invention comprises:
A substrate having a semiconductor surface, a buffer layer formed on the semiconductor surface and made of a semiconductor crystal having an in-plane lattice distortion, and arranged in a scattered manner on the buffer layer,
A microcrystal body made of a semiconductor crystal having a lattice strain in the in-plane direction, wherein one of the lattice strain of the buffer layer and the lattice strain of the microcrystal body is extension strain and the other is contraction strain.
【0010】さらに、前記微結晶体が配置された面を覆
い、伸び歪及び縮み歪のうち前記微結晶体と同じ格子歪
を有し、その大きさが前記微結晶体の格子歪の大きさよ
りも小さい半導体結晶からなる半導体層を形成してもよ
い。Further, it covers the surface on which the microcrystalline body is arranged and has the same lattice strain as that of the microcrystalline body among extension strain and shrinkage strain, and the magnitude thereof is larger than the lattice strain of the microcrystalline body. A semiconductor layer made of a small semiconductor crystal may be formed.
【0011】本発明の他の半導体装置は、半導体表面を
有する基板と、前記半導体表面の上に形成され、面内方
向の応力が加わっている半導体結晶からなるバッファ層
と、前記バッファ層の上に散点状に配置され、面内方向
の応力が加わっている半導体結晶からなる微結晶体とを
有し、前記バッファ層内の面内方向の応力と前記微結晶
体内の面内方向の応力のうち一方は圧縮応力、他方は引
張り応力である。Another semiconductor device according to the present invention is a substrate having a semiconductor surface, a buffer layer formed on the semiconductor surface and made of a semiconductor crystal under in-plane stress, and a buffer layer on the buffer layer. And a microcrystal body made of a semiconductor crystal, which is arranged in a scattered manner in the in-plane direction stress, and in-plane direction stress in the buffer layer and in-plane direction stress in the microcrystal body. One is compressive stress and the other is tensile stress.
【0012】さらに、前記微結晶体が配置された面を覆
い、内部に圧縮応力及び引張り応力のうち前記微結晶体
と同じ応力が加わっており、その大きさが前記微結晶体
内の応力よりも小さい半導体結晶からなる半導体層を形
成してもよい。Furthermore, the same stress as that of the microcrystalline body is applied to the inside of the microcrystalline body covering the surface on which the microcrystalline body is arranged, and the magnitude thereof is larger than the stress in the microcrystalline body. You may form the semiconductor layer which consists of a small semiconductor crystal.
【0013】本発明の他の半導体装置は、無歪時に第1
の格子定数を有する半導体結晶からなる半導体表面を有
する基板と、前記半導体表面の上に形成され、無歪時に
第2の格子定数を有する半導体結晶からなるバッファ層
と、前記バッファ層の上に散点状に配置され、無歪時に
第3の格子定数を有する半導体結晶からなる微結晶体と
を有し、前記第1の格子定数が前記第2の格子定数と前
記第3の格子定数との中間の大きさである。Another semiconductor device of the present invention is the first semiconductor device when no distortion occurs.
A substrate having a semiconductor surface made of a semiconductor crystal having a lattice constant of, a buffer layer made of a semiconductor crystal having a second lattice constant when the semiconductor surface is free of strain, and a buffer layer formed on the buffer layer. A microcrystal body made of a semiconductor crystal arranged in a dot shape and having a third lattice constant in the absence of strain, wherein the first lattice constant is the second lattice constant or the third lattice constant. It is a medium size.
【0014】さらに、前記微結晶体が配置された面を覆
い、無歪時に前記第1の格子定数と前記第3の格子定数
の間の格子定数を有する半導体結晶からなる半導体層を
形成してもよい。Further, a semiconductor layer made of a semiconductor crystal having a lattice constant between the first lattice constant and the third lattice constant in the absence of strain is formed so as to cover the surface on which the microcrystalline body is arranged. Good.
【0015】[0015]
【作用】半導体表面の上に、格子不整合のバッファ層を
堆積すると、バッファ層内に歪が生ずる。この歪はバッ
ファ層内において、半導体表面から遠ざかるに従って緩
和する。すなわち、バッファ層の格子定数は無歪時の格
子定数に近づく。When a buffer layer having a lattice mismatch is deposited on the semiconductor surface, strain occurs in the buffer layer. This strain is relaxed in the buffer layer as the distance from the semiconductor surface increases. That is, the lattice constant of the buffer layer approaches the lattice constant when there is no strain.
【0016】この上に、バッファ層上面と格子不整合の
半導体結晶を堆積すると、格子不整合が成長面内の弾性
限界を超える場合には、周囲よりも大きな歪を有する微
結晶体を散点状に含む半導体層が堆積するか、もしくは
微結晶体が散点状に堆積する。微結晶体の大きさは量子
サイズになるため、微結晶体のバンドギャップが周囲の
バンドギャップよりも小さい場合には、微結晶体が量子
箱として作用する。When a semiconductor crystal lattice-mismatched with the upper surface of the buffer layer is deposited on this, if the lattice mismatch exceeds the elastic limit in the growth plane, microcrystals having a strain larger than that of the surroundings are scattered. The semiconductor layer containing the microcrystals is deposited, or the microcrystalline bodies are scattered in a scattered manner. Since the size of the microcrystalline body is a quantum size, when the bandgap of the microcrystalline body is smaller than the surrounding bandgap, the microcrystalline body functions as a quantum box.
【0017】半導体表面の格子定数が、微結晶体の無歪
時の格子定数とバッファ層の無歪時の格子定数との間に
ある場合には、微結晶体とバッファ層表面との格子不整
合は、微結晶体と半導体表面との格子不整合よりも大き
くなる。このとき、バッファ層の格子歪と微結晶体の格
子歪は、一方が伸び歪であれば他方が縮み歪になる。ま
た、バッファ層内の面内方向の応力と微結晶体内の面内
方向の応力は、一方が圧縮応力であれば他方は引張り応
力になる。When the lattice constant of the semiconductor surface is between the strain-free lattice constant of the microcrystalline body and the lattice constant of the buffer layer without strain, the lattice mismatch between the microcrystalline body and the buffer layer surface. The match is greater than the lattice mismatch between the microcrystal and the semiconductor surface. At this time, with respect to the lattice strain of the buffer layer and the lattice strain of the microcrystalline body, if one is extension strain, the other is contraction strain. In addition, if one of the in-plane stress in the buffer layer and the in-plane stress in the microcrystal body is a compressive stress, the other becomes a tensile stress.
【0018】バッファ層の上に微結晶体を形成すると、
半導体表面上に直接微結晶体を形成する場合よりも格子
不整合が大きくなるため、微結晶体の内部歪が大きくな
る。微結晶体の内部歪が大きくなると、より小さい微結
晶体が多く形成されるようになると考えられる。なお、
これは実験により確かめることができた。When microcrystals are formed on the buffer layer,
Since the lattice mismatch becomes larger than in the case where the microcrystalline body is directly formed on the semiconductor surface, the internal strain of the microcrystalline body becomes large. It is considered that when the internal strain of the microcrystalline body becomes large, many smaller microcrystalline bodies are formed. In addition,
This could be confirmed by experiments.
【0019】[0019]
【実施例】まず、図1を参照して本願発明者らが特願平
6−222107号に開示した先の提案について説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the previous proposal disclosed by the inventors of the present invention in Japanese Patent Application No. 6-222107 will be described with reference to FIG.
【0020】図7は、先の提案による量子箱構造を有す
る半導体積層構造の断面図を示す。GaAs基板31上
にGaAsバッファ層32、InGaAs層33、及び
GaAsキャップ層34がそれぞれエピタキシャル成長
されている。InGaAs層33は、バッファ層32に
対して、成長面内の弾性限界を超える格子不整合を持っ
た組成のInGaAs成長条件で形成されたものであ
る。FIG. 7 shows a sectional view of a semiconductor laminated structure having a quantum box structure according to the above proposal. A GaAs buffer layer 32, an InGaAs layer 33, and a GaAs cap layer 34 are epitaxially grown on a GaAs substrate 31. The InGaAs layer 33 is formed on the buffer layer 32 under an InGaAs growth condition of a composition having a lattice mismatch that exceeds the elastic limit in the growth plane.
【0021】本願発明者らは、このような条件でInG
aAs層をエピタキシャル成長させると、周囲とは組成
の異なる微結晶体35が散点状に形成されることを見出
した。この微結晶体35は、厚さ方向に押しつぶされた
偏平球状になっている。微結晶体35及びその周囲のI
nGaAs層33の組成から、微結晶体35内に歪が集
中し、その周囲の歪は比較的小さいことがわかった。The inventors of the present invention have confirmed that InG
It has been found that, when the aAs layer is epitaxially grown, the microcrystals 35 having a different composition from the surroundings are formed in scattered points. The microcrystalline body 35 has a flat spherical shape crushed in the thickness direction. Microcrystal 35 and I around it
From the composition of the nGaAs layer 33, it was found that strain was concentrated in the microcrystalline body 35 and the strain around it was relatively small.
【0022】InGaAs層33内に微結晶体35が形
成されることで、全体の歪エネルギを安定状態にしてい
るものと考えられる。この微結晶体35のエネルギギャ
ップが周辺領域のエネルギギャップよりも小さければ、
微結晶体35は、3次元的に量子閉じ込めを行う量子箱
となる。It is considered that the formation of the microcrystalline body 35 in the InGaAs layer 33 stabilizes the entire strain energy. If the energy gap of the microcrystalline body 35 is smaller than the energy gap of the peripheral region,
The microcrystal body 35 serves as a quantum box that performs quantum confinement three-dimensionally.
【0023】この微結晶体35は人為的な加工によって
形成されるものではなく、物理的なエネルギバランスを
保つように自己形成される。このため、その大きさはほ
ぼ一様であり、微結晶体35周辺の結晶性も極めて良好
に保たれる。The microcrystals 35 are not formed by artificial processing, but are self-formed so as to maintain a physical energy balance. Therefore, the size thereof is substantially uniform, and the crystallinity around the microcrystalline body 35 is also kept extremely good.
【0024】上記先の提案では量子箱を自己形成するこ
とができるが、より顕著な量子効果を得るためには、量
子箱の大きさをさらに縮小することが望まれる。このと
き、量子箱の面内占有率を低下させないためには、量子
箱の密度を高める必要がある。以下、量子箱の面内占有
率を低下させることなく、量子箱の大きさを縮小するこ
とができる本発明の実施例について説明する。In the above proposal, the quantum box can be self-formed, but in order to obtain a more remarkable quantum effect, it is desired to further reduce the size of the quantum box. At this time, in order to prevent the in-plane occupation rate of the quantum boxes from decreasing, it is necessary to increase the density of the quantum boxes. Hereinafter, an embodiment of the present invention will be described in which the size of the quantum box can be reduced without reducing the in-plane occupancy of the quantum box.
【0025】図1は、本発明の実施例による半導体積層
構造の断面図及び各層の無歪時の格子定数を概略的に示
す。図1の左図に示すようにGaAs基板1の上に、I
nGaAsPバッファ層2、InGaAsP下層3、I
nGaAs量子箱層4、InGaAsP上層5がこの順
番に積層されている。InGaAs量子箱層4内には、
散点状に量子箱4aが形成されている。FIG. 1 schematically shows a cross-sectional view of a semiconductor laminated structure according to an embodiment of the present invention and lattice constants of the respective layers when there is no strain. On the GaAs substrate 1, as shown in the left diagram of FIG.
nGaAsP buffer layer 2, InGaAsP lower layer 3, I
The nGaAs quantum box layer 4 and the InGaAsP upper layer 5 are laminated in this order. In the InGaAs quantum box layer 4,
Quantum boxes 4a are formed in a dotted pattern.
【0026】InGaAsPバッファ層2、InGaA
sP下層3、InGaAs量子箱層4、及びInGaA
sP上層5の膜厚は、それぞれ500nm、100n
m、10nm、及び100nmである。InGaAsP buffer layer 2, InGaA
sP lower layer 3, InGaAs quantum box layer 4, and InGaA
The film thickness of the sP upper layer 5 is 500 nm and 100 n, respectively.
m, 10 nm, and 100 nm.
【0027】各層は、有機金属気相成長法(MOVP
E)でエピタキシャル成長されたものである。InGa
AsPバッファ層2、InGaAsP下層3及びInG
aAsP上層5堆積時の原料ガスとして、トリメチルイ
ンジウム(TMI)、トリエチルガリウム(TEG)、
ホスフィン(PH3 )、及びアルシン(AsH3 )を用
い、量子箱層4堆積時の原料ガスとして、トリメチルイ
ンジウムジメチルエチルアミンアダクト(In(C
H3 )3 N(CH3 )2 (C2 H5 ))、トリメチルガ
リウム(TMG)及びアルシンを用いた。Each layer is formed by metal organic vapor phase epitaxy (MOVP).
It was epitaxially grown in E). InGa
AsP buffer layer 2, InGaAsP lower layer 3 and InG
Trimethylindium (TMI), triethylgallium (TEG), as a source gas at the time of depositing the aAsP upper layer 5,
Using phosphine (PH 3 ) and arsine (AsH 3 ), trimethylindiumdimethylethylamine adduct (In (C
H 3) 3 N (CH 3 ) 2 (C 2 H 5)), was used trimethylgallium (TMG) and arsine.
【0028】図2は、図1に示す半導体積層構造のバッ
ファ層の歪量に対する量子箱4aの面内直径を示す。横
軸はバッファ層2の歪量を単位%で表し、縦軸は量子箱
4aの面内直径を単位nmで表す。なお、バッファ層の
歪量は、GaAs基板1の格子定数をa、InGaAs
Pバッファ層2の無歪時の格子定数をbとしたとき、
(b−a)/aと定義した。量子箱の直径は透過型電子
顕微鏡(TEM)で観測した。FIG. 2 shows the in-plane diameter of the quantum box 4a with respect to the strain amount of the buffer layer of the semiconductor laminated structure shown in FIG. The horizontal axis represents the strain amount of the buffer layer 2 in%, and the vertical axis represents the in-plane diameter of the quantum box 4a in nm. The strain amount of the buffer layer is a lattice constant of the GaAs substrate 1 is a, InGaAs
When the lattice constant of the P buffer layer 2 without strain is b,
It was defined as (ba) / a. The diameter of the quantum box was observed with a transmission electron microscope (TEM).
【0029】バッファ層2の歪量が0のとき、量子箱の
直径は約22nmである。歪量が正の方向に大きくなる
と、量子箱の直径は大きくなり、歪量が0.7%のとき
量子箱の直径は約32nmになる。歪量が負の方向に大
きくなると、量子箱の直径は小さくなり、歪量が−0.
8%のとき量子箱の直径は約16nmになる。When the strain amount of the buffer layer 2 is 0, the diameter of the quantum box is about 22 nm. When the strain amount increases in the positive direction, the diameter of the quantum box increases, and when the strain amount is 0.7%, the diameter of the quantum box becomes about 32 nm. When the strain amount increases in the negative direction, the diameter of the quantum box decreases, and the strain amount becomes −0.
At 8%, the quantum box diameter is about 16 nm.
【0030】バッファ層の歪量が負の方向に大きくなる
と量子箱の直径が小さくなり、歪量が正の方向に大きく
なると量子箱の直径が大きくなる理由は、以下のように
考察される。The reason why the diameter of the quantum box becomes smaller when the strain amount of the buffer layer increases in the negative direction and becomes larger when the strain amount increases in the positive direction is considered as follows.
【0031】歪量が負のときは、バッファ層2の面内方
向に伸び歪が発生する。バッファ層2内においてGaA
s基板1表面から離れるに従って歪は徐々に緩和され
る。このため、バッファ層2の上面の格子定数はその無
歪時の格子定数に近づき、GaAs基板1の格子定数よ
りも小さくなる。When the strain amount is negative, extension strain occurs in the in-plane direction of the buffer layer 2. GaA in the buffer layer 2
s The strain gradually relaxes as the distance from the surface of the substrate 1 increases. Therefore, the lattice constant of the upper surface of the buffer layer 2 approaches the lattice constant when there is no strain, and becomes smaller than the lattice constant of the GaAs substrate 1.
【0032】InGaAsP下層3は、InGaAs量
子箱層4とInGaAsPバッファ層2の格子定数の中
間の無歪時の格子定数を有するような組成とされてい
る。InGaAsP下層3においても歪が徐々に緩和さ
れ、InGaAsP下層3の上面の格子定数は、GaA
s基板1の格子定数よりも小さくなる。The InGaAsP lower layer 3 has such a composition that it has a lattice constant in the absence of strain, which is between the lattice constants of the InGaAs quantum box layer 4 and the InGaAsP buffer layer 2. The strain is gradually relaxed also in the InGaAsP lower layer 3, and the lattice constant of the upper surface of the InGaAsP lower layer 3 is GaA.
It is smaller than the lattice constant of the s substrate 1.
【0033】InGaAs量子箱層4の格子定数はGa
Asの格子定数よりも大きいため、InGaAsP下層
3の上面の格子定数とInGaAsの格子定数との不整
合は、GaAsとInGaAsのそれよりも大きくな
る。格子不整合が大きくなるため、InGaAs量子箱
層4に、より大きな歪エネルギが発生する。この歪エネ
ルギを低下させるために、量子箱4aの大きさが小さく
なるものと考えられる。The lattice constant of the InGaAs quantum box layer 4 is Ga.
Since it is larger than the lattice constant of As, the mismatch between the lattice constant of the upper surface of the InGaAsP lower layer 3 and the lattice constant of InGaAs is larger than that of GaAs and InGaAs. Since the lattice mismatch becomes large, a larger strain energy is generated in the InGaAs quantum box layer 4. It is considered that the size of the quantum box 4a becomes smaller in order to reduce the strain energy.
【0034】逆に、バッファ層2の歪量を正の方向に大
きくすると、バッファ層2の上面及びInGaAsP下
層3の上面の格子定数は、GaAs基板1の格子定数よ
りも大きくなる。従って、InGaAsP下層3の上面
の格子定数とInGaAsの格子定数との不整合は小さ
くなる。このため、量子箱4aが大きくなるものと考え
られる。On the contrary, when the strain amount of the buffer layer 2 is increased in the positive direction, the lattice constants of the upper surface of the buffer layer 2 and the lower surface of the InGaAsP lower layer 3 become larger than the lattice constant of the GaAs substrate 1. Therefore, the mismatch between the lattice constant of the upper surface of the InGaAsP lower layer 3 and the lattice constant of InGaAs becomes small. Therefore, it is considered that the quantum box 4a becomes large.
【0035】図1の右図は、バッファ層2の歪量が負の
場合の各層の無歪時の格子定数を示す。横軸はGaAs
基板1の格子定数を基準(0)とした格子定数の相対値
を任意目盛りで示す。InGaAsPバッファ層2の無
歪時の格子定数の相対値は負であり、InGaAsP下
層3の無歪時の格子定数は、GaAs基板1の格子定数
とバッファ層2の格子定数の中間の値である。InGa
As量子箱層4の無歪時の格子定数の相対値は正であ
る。The right diagram of FIG. 1 shows the lattice constant of each layer when the strain amount of the buffer layer 2 is negative and there is no strain. The horizontal axis is GaAs
The relative value of the lattice constant with the lattice constant of the substrate 1 as a reference (0) is shown on an arbitrary scale. The relative value of the lattice constant of the InGaAsP buffer layer 2 without strain is negative, and the lattice constant of the InGaAsP lower layer 3 without strain is an intermediate value between the lattice constant of the GaAs substrate 1 and the lattice constant of the buffer layer 2. . InGa
The relative value of the lattice constant of the As quantum box layer 4 when there is no strain is positive.
【0036】また、InGaAs量子箱層4の無歪時の
格子定数の相対値が負の場合は、InGaAsPバッフ
ァ層の無歪時の格子定数の相対値を正にすることによ
り、InGaAs量子箱層とInGaAsP下層3との
格子不整合を大きくすることができる。If the relative value of the lattice constant of the InGaAs quantum box layer 4 without strain is negative, by making the relative value of the lattice constant of the InGaAsP buffer layer without strain positive, the InGaAs quantum box layer It is possible to increase the lattice mismatch between the InGaAsP lower layer 3 and the InGaAsP lower layer 3.
【0037】このように、基板と量子箱層との間にバッ
ファ層を設け、バッファ層の無歪時の格子定数の相対値
が量子箱層の無歪時の格子定数の相対値と逆符号になる
ようにすることにより、量子箱層とその下層表面との格
子不整合を大きくすることができる。格子不整合が大き
くなると、上記考察から量子箱の面内直径を小さくする
ことができると考えられる。なお、量子箱の面内直径を
小さくする効果を得るためには、バッファ層の面内方向
の歪が1×10-3以上であることが好ましい。As described above, the buffer layer is provided between the substrate and the quantum box layer, and the relative value of the lattice constant of the buffer layer without strain is opposite in sign to the relative value of the lattice constant of the quantum box layer without strain. The lattice mismatch between the quantum box layer and the surface of the layer below it can be increased. From the above consideration, it is considered that the in-plane diameter of the quantum box can be reduced when the lattice mismatch becomes large. In order to obtain the effect of reducing the in-plane diameter of the quantum box, the strain in the in-plane direction of the buffer layer is preferably 1 × 10 −3 or more.
【0038】この場合、バッファ層の格子歪と量子箱層
の格子歪は、一方が伸び歪であれば他方は縮み歪とな
り、相互に逆方向の歪になる。また、バッファ層内の面
内方向の応力と量子箱層内の面内方向の応力は、一方が
圧縮応力であれば他方は引張り応力になる。In this case, with respect to the lattice strain of the buffer layer and the lattice strain of the quantum box layer, if one is an extension strain, the other is a contraction strain, and the strains are in mutually opposite directions. In addition, if one of the in-plane stress in the buffer layer and the in-plane stress in the quantum box layer is a compressive stress, the other is a tensile stress.
【0039】図3は、図1に示す積層構造の量子箱4a
からのフォトルミネッセンス(PL)の発光波長のバッ
ファ層歪量依存性を示す。横軸はバッファ層の歪量を単
位%で表し、縦軸は発光波長を単位μmで表す。なお、
励起光には波長6471ÅのKrレーザ光を使用した。FIG. 3 shows a quantum box 4a having the laminated structure shown in FIG.
3 shows the dependence of the emission wavelength of photoluminescence (PL) on the buffer layer strain amount. The horizontal axis represents the strain amount of the buffer layer in%, and the vertical axis represents the emission wavelength in μm. In addition,
Kr laser light having a wavelength of 6471Å was used as the excitation light.
【0040】バッファ層の歪量が0のときは、発光波長
は約1.3μmである。バッファ層の歪量が負の方向に
大きくなると、発光波長は短くなり、歪量が−0.8%
のとき約1.16μmになる。バッファ層の歪量が正の
方向に大きくなると、発光波長は長くなり、歪量が0.
75%のとき約1.46μmになる。When the strain amount of the buffer layer is 0, the emission wavelength is about 1.3 μm. When the amount of strain in the buffer layer increases in the negative direction, the emission wavelength becomes shorter, and the amount of strain is -0.8%.
At that time, it becomes about 1.16 μm. When the amount of strain in the buffer layer increases in the positive direction, the emission wavelength becomes longer, and the amount of strain becomes 0.
It becomes about 1.46 μm at 75%.
【0041】量子箱が小さくなれば、その量子箱内の電
子のエネルギ準位相互の間隔が広がり発光波長は短くな
る。従って、図3からも、バッファ層の歪量が負の方向
に大きくなると、量子箱が小さくなることが示唆され
る。As the quantum box becomes smaller, the spacing between the electron energy levels in the quantum box becomes wider and the emission wavelength becomes shorter. Therefore, also from FIG. 3, it is suggested that the quantum box becomes smaller when the strain amount of the buffer layer increases in the negative direction.
【0042】図4は、図1に示す積層構造の量子箱4a
からのPLの発光強度のバッファ層歪緩和量依存性を示
す。横軸はバッファ層の歪緩和量を単位%で表し、縦軸
はPL発光強度を任意目盛りで表す。FIG. 4 shows a quantum box 4a having the laminated structure shown in FIG.
3 shows the dependence of PL emission intensity on the buffer layer strain relaxation amount. The abscissa represents the strain relaxation amount of the buffer layer in the unit of%, and the ordinate represents the PL emission intensity on an arbitrary scale.
【0043】ここで、バッファ層の歪緩和量は、GaA
s基板1の格子定数をa、無歪時のバッファ層2の格子
定数をb0 、バッファ層2上面の格子定数をb1 とした
とき、|a−b1 |/|a−b0 |と定義した。すなわ
ち、歪緩和量が0%のときは、バッファ層上面の格子定
数がGaAs基板1の格子定数と同一であり、歪緩和量
が100%のときはバッファ層上面の格子定数がバッフ
ァ層の無歪時の格子定数と同一であることを表してい
る。Here, the strain relaxation amount of the buffer layer is GaA.
When the lattice constant of the s substrate 1 is a, the lattice constant of the buffer layer 2 without strain is b 0 , and the lattice constant of the upper surface of the buffer layer 2 is b 1 , | a−b 1 | / | a−b 0 | Was defined. That is, when the strain relaxation amount is 0%, the lattice constant on the upper surface of the buffer layer is the same as the lattice constant of the GaAs substrate 1, and when the strain relaxation amount is 100%, the lattice constant on the upper surface of the buffer layer is the same as that of the buffer layer. It is the same as the lattice constant when strained.
【0044】図中の記号●、■は、それぞれバッファ層
2の歪量が−0.8%、−0.3%の場合を示してい
る。なお、歪緩和量は、バッファ層の厚さを変化させる
ことにより制御し、非対称結晶面のX線回折を調べるこ
とにより測定した。The symbols and in the figure indicate the cases where the strain amounts of the buffer layer 2 are −0.8% and −0.3%, respectively. The strain relaxation amount was controlled by changing the thickness of the buffer layer, and measured by examining the X-ray diffraction of the asymmetric crystal plane.
【0045】図4に示すように、バッファ層の歪緩和量
が大きくなると、PL強度も大きくなる。これは、量子
箱の結晶性が改善されているかもしくは量子箱の分布密
度が高くなっているためと考えられる。従って、量子箱
を発光中心として使用する場合には、バッファ層の歪緩
和量を大きくすることが好ましい。As shown in FIG. 4, as the strain relaxation amount of the buffer layer increases, the PL intensity also increases. It is considered that this is because the crystallinity of the quantum boxes is improved or the distribution density of the quantum boxes is increased. Therefore, when the quantum box is used as the emission center, it is preferable to increase the strain relaxation amount of the buffer layer.
【0046】上記実施例では、InGaAsPバッファ
層2とInGaAs量子箱層4との間にInGaAsP
下層3を挿入した場合を説明したが、InGaAsPバ
ッファ層2の上に直接InGaAs量子箱層を形成して
もよい。また、InGaAsPバッファ層2とInGa
As量子箱層4との間に複数の層を挿入してもよい。In the above embodiment, the InGaAsP buffer layer 2 and the InGaAsP quantum box layer 4 are arranged between the InGaAsP buffer layer 2 and the InGaAsP quantum box layer 4.
Although the case where the lower layer 3 is inserted has been described, the InGaAs quantum box layer may be directly formed on the InGaAsP buffer layer 2. In addition, the InGaAsP buffer layer 2 and InGa
A plurality of layers may be inserted between the layer and the As quantum box layer 4.
【0047】また、上記実施例では、基板にGaAs、
バッファ層にInGaAsP、量子箱層にInGaAs
を用いた場合を説明したが、その他の半導体結晶を用い
てもよい。例えば、その他のIII−V族化合物半導
体、または、Si、Ge及びSiGe等のIV族元素か
らなる半導体を用いてもよい。また、バッファ層として
低温で成長させたGaAs層を用いてもよい。GaAs
を低温で成長させるとストイキオメトリからずれたGa
As層が成長する。このため、通常のGaAsと格子定
数が異なるGaAs層を形成することができる。In the above embodiment, GaAs is used as the substrate,
InGaAsP for the buffer layer and InGaAs for the quantum box layer
However, other semiconductor crystals may be used. For example, other III-V group compound semiconductors or semiconductors composed of group IV elements such as Si, Ge and SiGe may be used. Alternatively, a GaAs layer grown at a low temperature may be used as the buffer layer. GaAs
Ga grown at low temperature deviates from stoichiometry
The As layer grows. Therefore, it is possible to form a GaAs layer having a lattice constant different from that of normal GaAs.
【0048】図1では、量子箱4aが量子箱層4と同時
に形成される場合を示したが、半導体表面上に半導体結
晶が島状に成長する場合もある。図5は、量子箱が島状
に成長した場合の半導体積層構造の断面図を示す。半導
体基板1の上にバッファ層2が形成され、その上に、島
状に微結晶体6が成長している。このように島状に成長
した微結晶体も、その大きさが量子効果が現れる程度に
小さければ量子箱として作用する。微結晶体6を他の半
導体層で埋め込んでもよい。このとき、他の半導体層中
には、格子歪が存在してもよいし存在しなくてもよい。Although FIG. 1 shows the case where the quantum box 4a is formed at the same time as the quantum box layer 4, a semiconductor crystal may grow on the semiconductor surface in an island shape. FIG. 5 shows a cross-sectional view of the semiconductor laminated structure when the quantum boxes are grown in an island shape. A buffer layer 2 is formed on a semiconductor substrate 1, and an island-shaped microcrystalline body 6 is grown on the buffer layer 2. The island-shaped grown microcrystals also act as quantum boxes if their size is small enough to cause quantum effects. The microcrystalline body 6 may be embedded with another semiconductor layer. At this time, lattice strain may or may not exist in the other semiconductor layers.
【0049】図6は、上記実施例による積層構造を適用
した半導体レーザ装置の断面図を示す。n型GaAs基
板20の上に、厚さ500nmのn型In0.2 Ga0.8
Pバッファ層21、厚さ500nmのn型In0.3 Ga
0.7 Pバッファ層22、厚さ50nmのn型GaAs
0.7 P0.3 クラッド層23、厚さ10nmの真性GaA
s0.7 P0.3 ガイド層24、真性InGaAs活性層2
5、厚さ10nmの真性GaAs0.7 P0.3 ガイド層2
6、厚さ50nmのp型GaAs0.7 P0.3 クラッド層
27、厚さ500nmのp型In0.3 Ga0.7 Pコンタ
クト層28がこの順番に積層されている。FIG. 6 is a sectional view of a semiconductor laser device to which the laminated structure according to the above-mentioned embodiment is applied. On a n-type GaAs substrate 20, a 500 nm-thick n-type In 0.2 Ga 0.8
P buffer layer 21, 500 nm thick n-type In 0.3 Ga
0.7 P buffer layer 22, 50 nm thick n-type GaAs
0.7 P 0.3 clad layer 23, 10 nm thick intrinsic GaA
s 0.7 P 0.3 guide layer 24, intrinsic InGaAs active layer 2
5, 10 nm thick intrinsic GaAs 0.7 P 0.3 guide layer 2
6. A p-type GaAs 0.7 P 0.3 clad layer 27 having a thickness of 50 nm and a p-type In 0.3 Ga 0.7 P contact layer 28 having a thickness of 500 nm are laminated in this order.
【0050】InGaPバッファ層21の無歪時の格子
定数はGaAsの格子定数よりも小さいため、InGa
Pバッファ層21内に引張り歪が発生する。逆に、In
GaAs活性層25の無歪時の格子定数はGaAsの格
子定数よりも大きいため、圧縮歪が発生する。このよう
に、InGaPバッファ層21及びInGaAs活性層
25に、相互に逆方向の歪が発生している。Since the lattice constant of the InGaP buffer layer 21 without strain is smaller than that of GaAs,
Tensile strain occurs in the P buffer layer 21. Conversely, In
Since the lattice constant of the GaAs active layer 25 without strain is larger than that of GaAs, compressive strain occurs. As described above, strains in opposite directions are generated in the InGaP buffer layer 21 and the InGaAs active layer 25.
【0051】GaAsPガイド層24とInGaAs活
性層25との間の格子不整合により、活性層25の中に
量子箱25aが形成される。この格子不整合は、InG
aAs活性層25とGaAs基板との格子不整合よりも
拡大しているため、より小さな量子箱25aが形成され
る。活性層25に注入された電子及び正孔は、バンドギ
ャップの小さい量子箱の中に入り、量子箱のエネルギ状
態を占める。量子箱25a内で電子正孔対が再結合して
エネルギ状態が空きになると、他の電子及び正孔が量子
箱25aの中に入る。A quantum box 25a is formed in the active layer 25 due to the lattice mismatch between the GaAsP guide layer 24 and the InGaAs active layer 25. This lattice mismatch is caused by InG
Since it is larger than the lattice mismatch between the aAs active layer 25 and the GaAs substrate, a smaller quantum box 25a is formed. The electrons and holes injected into the active layer 25 enter the quantum box having a small band gap and occupy the energy state of the quantum box. When the electron-hole pair recombines in the quantum box 25a and the energy state becomes empty, other electrons and holes enter the quantum box 25a.
【0052】このように、量子箱内で電子正孔対が再結
合して発光することにより、温度特性の優れた半導体レ
ーザを実現することが可能になる。また、InGaPバ
ッファ層21の上面は、GaAsよりも小さな格子定数
を有する。このため、クラッド層としてGaAsよりも
格子定数の小さい半導体結晶を使用することが可能にな
る。一般に、III−V族化合物半導体結晶において
は、格子定数が小さくなるとバンドギャップは大きくな
る。As described above, the electron-hole pairs are recombined in the quantum box to emit light, so that a semiconductor laser having excellent temperature characteristics can be realized. Further, the upper surface of the InGaP buffer layer 21 has a lattice constant smaller than that of GaAs. Therefore, it becomes possible to use a semiconductor crystal having a lattice constant smaller than that of GaAs for the cladding layer. Generally, in a III-V compound semiconductor crystal, the band gap increases as the lattice constant decreases.
【0053】このため、クラッド層としてバンドギャッ
プの大きな半導体結晶を使用することが可能になる。ク
ラッド層のバンドギャップが大きくなると、より効率的
に光閉じ込めが行われるため、レーザ発光効率の向上が
期待できる。Therefore, it becomes possible to use a semiconductor crystal having a large band gap as the cladding layer. When the band gap of the clad layer becomes large, the light can be confined more efficiently, so that improvement in the laser emission efficiency can be expected.
【0054】以上実施例に沿って本発明を説明したが、
本発明はこれらに制限されるものではない。例えば、種
々の変更、改良、組み合わせ等が可能なことは当業者に
自明であろう。The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
【0055】[0055]
【発明の効果】以上説明したように、本発明によれば、
小さな量子箱を高密度に自己形成することが可能にな
る。この量子箱を半導体レーザ装置に適用すると、温度
特性の優れた半導体レーザ装置を得ることができる。As described above, according to the present invention,
It becomes possible to self-assemble small quantum boxes with high density. When this quantum box is applied to a semiconductor laser device, a semiconductor laser device having excellent temperature characteristics can be obtained.
【図1】本発明の実施例による半導体積層構造を断面
図、及び各層の無歪時の格子定数の相対値を示すグラフ
である。FIG. 1 is a cross-sectional view of a semiconductor laminated structure according to an example of the present invention, and a graph showing relative values of lattice constants of each layer when there is no strain.
【図2】図1に示す積層構造内の量子箱の面内直径を、
バッファ層の歪量に対して示すグラフである。2 shows the in-plane diameter of the quantum box in the laminated structure shown in FIG.
It is a graph shown with respect to the amount of strains of a buffer layer.
【図3】図1に示す積層構造内の量子箱からのPL発光
波長を、バッファ層の歪量に対して示すグラフである。FIG. 3 is a graph showing the PL emission wavelength from the quantum box in the laminated structure shown in FIG. 1 against the strain amount of the buffer layer.
【図4】図1に示す積層構造内の量子箱からのPL発光
強度を、バッファ層の歪緩和量に対して示すグラフであ
る。FIG. 4 is a graph showing the PL emission intensity from the quantum box in the laminated structure shown in FIG. 1 against the strain relaxation amount of the buffer layer.
【図5】量子箱を島状に成長させた場合の、半導体積層
構造の断面図である。FIG. 5 is a cross-sectional view of a semiconductor laminated structure when quantum boxes are grown in an island shape.
【図6】本発明の実施例による半導体レーザ装置の断面
図である。FIG. 6 is a sectional view of a semiconductor laser device according to an embodiment of the present invention.
【図7】本願発明者らの先の提案による半導体積層構造
の断面図である。FIG. 7 is a cross-sectional view of a semiconductor laminated structure proposed by the inventors of the present application.
1 GaAs基板 2 InGaAsPバッファ層 3 InGaAsP下層 4 InGaAs量子箱層 4a 量子箱 5 InGaAsP上層 6 微結晶体 20 n型GaAs基板 21、22 n型InGaPバッファ層 23 n型GaAsPクラッド層 24、26 GaAsPガイド層 25 InGaAs活性層 27 p型GaAsPクラッド層 28 p型InGaPコンタクト層 31 GaAs基板 32 GaAsバッファ層 33 InGaAs層 34 GaAsキャップ層 35 量子箱 1 GaAs substrate 2 InGaAsP buffer layer 3 InGaAsP lower layer 4 InGaAs quantum box layer 4a quantum box 5 InGaAsP upper layer 6 Microcrystal 20 n-type GaAs substrate 21, 22 n-type InGaP buffer layer 23 n-type GaAsP clad layer 24, 26 GaAsP guide layer 25 InGaAs active layer 27 p-type GaAsP clad layer 28 p-type InGaP contact layer 31 GaAs substrate 32 GaAs buffer layer 33 InGaAs layer 34 GaAs cap layer 35 quantum box
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平7−231084(JP,A) 特開 平5−62896(JP,A) 特開 平8−88345(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01S 5/00 - 5/50 H01L 29/06 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-231084 (JP, A) JP-A-5-62896 (JP, A) JP-A-8-88345 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01S 5/00-5/50 H01L 29/06
Claims (8)
する半導体結晶からなるバッファ層と、 前記バッファ層の上に散点状に配置され、面内方向の格
子歪を有する半導体結晶からなる微結晶体とを有し、 前記バッファ層の格子歪と前記微結晶体の格子歪のうち
一方は伸び歪、他方は縮み歪である半導体装置。1. A substrate having a semiconductor surface, a buffer layer formed on the semiconductor surface and made of a semiconductor crystal having in-plane lattice strain, and arranged on the buffer layer in a scattered manner. A semiconductor device having a microcrystalline body made of a semiconductor crystal having in-plane lattice strain, wherein one of the lattice strain of the buffer layer and the lattice strain of the microcrystalline body is extension strain and the other is contraction strain.
覆い、伸び歪及び縮み歪のうち前記微結晶体と同じ格子
歪を有し、その大きさは前記微結晶体の格子歪の大きさ
よりも小さい半導体結晶からなる半導体層を有する請求
項1に記載の半導体装置。2. The surface on which the microcrystalline body is arranged is covered, and the strain has the same lattice strain as that of the microcrystalline body among extension strain and shrinkage strain, and its magnitude is the lattice strain of the microcrystalline body. The semiconductor device according to claim 1, further comprising a semiconductor layer made of a semiconductor crystal smaller than a size.
っている半導体結晶からなるバッファ層と、 前記バッファ層の上に散点状に配置され、面内方向の応
力が加わっている半導体結晶からなる微結晶体とを有
し、 前記バッファ層内の面内方向の応力と前記微結晶体内の
面内方向の応力のうち一方は圧縮応力、他方は引張り応
力である半導体装置。3. A substrate having a semiconductor surface, a buffer layer formed on the semiconductor surface and made of a semiconductor crystal to which a stress in an in-plane direction is applied, and dot-shaped arrangements on the buffer layer. , Having a microcrystalline body made of a semiconductor crystal to which stress in the in-plane direction is applied, one of the in-plane direction stress in the buffer layer and the in-plane direction stress in the microcrystal body is a compressive stress, The other is a semiconductor device that has tensile stress.
覆い、内部に圧縮応力及び引張り応力のうち前記微結晶
体と同じ応力が加わっており、その大きさは前記微結晶
体内の応力よりも小さい半導体結晶からなる半導体層を
有する請求項3に記載の半導体装置。4. The surface of the microcrystalline body is covered with a stress that is the same as the microcrystalline body of the compressive stress and the tensile stress, and the magnitude of the stress is the stress in the microcrystalline body. The semiconductor device according to claim 3, further comprising a semiconductor layer made of a semiconductor crystal smaller than that.
結晶からなる半導体表面を有する基板と、 前記半導体表面の上に形成され、無歪時に第2の格子定
数を有する半導体結晶からなるバッファ層と、 前記バッファ層の上に散点状に配置され、無歪時に第3
の格子定数を有する半導体結晶からなる微結晶体とを有
し、 前記第1の格子定数が前記第2の格子定数と前記第3の
格子定数との中間の大きさである半導体装置。5. A substrate having a semiconductor surface made of a semiconductor crystal having a first lattice constant when unstrained, and a buffer formed on the semiconductor surface and made of a semiconductor crystal having a second lattice constant when unstrained. Layer and the buffer layer, and the third layer is arranged in a scattered manner on the buffer layer when there is no strain.
And a microcrystal body made of a semiconductor crystal having a lattice constant of, wherein the first lattice constant is an intermediate size between the second lattice constant and the third lattice constant.
覆い、無歪時に前記第1の格子定数と前記第3の格子定
数の中間の格子定数を有する半導体結晶からなる半導体
層を有する請求項5に記載の半導体装置。6. A semiconductor layer formed of a semiconductor crystal that covers a surface on which the microcrystalline body is arranged and that has a lattice constant intermediate between the first lattice constant and the third lattice constant when no strain is applied. The semiconductor device according to claim 5.
I−V族化合物半導体からなる請求項1〜6のいずれか
に記載の半導体装置。7. The buffer layer and the microcrystalline body are II
The semiconductor device according to claim 1, which is made of an IV group compound semiconductor.
導体からなる請求項1〜7のいずれかに記載の半導体装
置。8. The semiconductor device according to claim 1, wherein the semiconductor surface is made of a III-V group compound semiconductor.
Priority Applications (1)
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JP6101895A JP3534879B2 (en) | 1995-03-20 | 1995-03-20 | Semiconductor device using three-dimensional quantum confinement |
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JP3534879B2 true JP3534879B2 (en) | 2004-06-07 |
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