JP3533476B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
More specifically, the present invention relates to a liquid crystal display device that switches a switching element according to scanning timing and applies a video signal to liquid crystal.

[0002]

2. Description of the Related Art A liquid crystal display device using a conventional switching element includes, for example, a thin film transistor (TFT).
There is known an active matrix type TFT-LCD panel that drives a liquid crystal by writing a video signal according to a scanning timing for each pixel using a film transistor).

In this active matrix type liquid crystal display device, generally, as an equivalent circuit for each pixel, as shown in FIG. 5, gate lines (scanning lines) 1 are provided in the row direction and drain lines in the column direction. (Signal line) 2 is provided. A video signal is input to the drain line 2 and a gate voltage signal is sequentially input to the gate line 1 in accordance with the horizontal scanning timing.

A thin film transistor (TFT) 3 as a switching element is connected to each pixel portion corresponding to the intersection of the gate line 1 and the drain line 2.
The liquid crystal capacitance CLC is connected to the source electrode S of the TFT 3, the gate line 1 is connected to the gate electrode G, and the drain line 2 is connected to the drain electrode D.
Here, an n-channel MOS is used for the TFT 3.

Then, VGH is applied to the gate line 1 of the TFT3.
Is applied to turn on the selected state.
At this time, the drain voltage VD from the drain line 2 as a video signal as shown in FIG. 7A is written in the liquid crystal capacitance CLC in the form of charges, and is selected while another gate line 1 is selected. By turning off the non-existing TFT 3, the pixel is driven by the written charges.

[0006]

However, in such a conventional liquid crystal display device, since the TFT 3 has a gate-source parasitic capacitance CGS as shown in FIG. 5, the TFT 3 is switched. When the pixel is driven in this manner, the waveform of the source voltage VS applied to the liquid crystal capacitance CLC is at low level and high level with respect to the drain voltage VD, as shown by white arrows A and B in FIG. 7A. ,
Both have distorted waveforms that are deviated by ΔVGS to the negative side (the positive side in a p-channel MOS TFT).

This is because the gate voltage VG changes from "Low" to "High" due to the influence of the gate-source parasitic capacitance CGS.
h ”(in the p-channel TFT,“ High ”to“ Low ”)
This is due to the jump-in characteristic in which the source voltage VS changes abruptly when switching to "). This .DELTA.VGS is called the jump-in voltage.

The ΔVGS component in the source voltage VS waveform causes the source voltage VS waveform to be asymmetric with respect to the common voltage VCOM, as shown in FIG. 7A, and due to the asymmetry of the liquid crystal drive waveform. There is a problem that the generated DC component deteriorates the liquid crystal and causes an afterimage to deteriorate the image quality.

However, if ΔVGS is a constant, it can be easily removed by adjusting the common voltage. However, this ΔVGS has a similar voltage dependence due to the voltage dependence of the liquid crystal capacitance CLC, and therefore cannot be completely removed only by adjusting the common voltage. Therefore, in order to reduce the above-mentioned adverse effect of ΔVGS, in the conventional example shown in FIG. 6, the auxiliary capacitance electrode is provided in the liquid crystal display panel to form the auxiliary capacitance CS.

That is, the above-mentioned ΔVGS is expressed by the following equation, where CGS is the gate-source parasitic capacitance, CLC is the liquid crystal capacitance, and VGHL is the value obtained by subtracting the gate voltage of the low level VGL from the high level VGH.

[0011]

[Equation 1] From the above equation, it can be seen that in order to reduce the jump voltage ΔVGS, the auxiliary capacitance CS should be increased. However, if the auxiliary capacitance CS is made too large, the aperture ratio becomes small and the writing time becomes long.

Therefore, the present invention has been made in view of the above problems, and provides a liquid crystal display device in which the direct current component of the driving voltage applied to the liquid crystal is eliminated, the liquid crystal is less likely to deteriorate, and high image quality is obtained. Is intended.

[0013]

According to another aspect of the present invention, there is provided a liquid crystal display device in which pixel electrodes, which are arranged to face a common electrode of a liquid crystal display panel with a liquid crystal interposed therebetween, are arranged in a matrix and are provided for each pixel. A predetermined control voltage alternating from the gate wiring is applied to the gate electrode of the selected switching element to bring it into a selected state, and a predetermined display voltage alternating from the drain wiring is applied to the pixel electrode in the selected state to perform display control. In a liquid crystal display device, the switching element is configured by connecting a first conductivity type field effect transistor and a second conductivity type field effect transistor in parallel, and the same conductivity type is formed by using a common gate wiring between adjacent pixels in a column direction. Field-effect transistors are connected to each other to simultaneously switch one field-effect transistor between adjacent pixels in the column direction, and By applying a first conductivity type and a display voltage alternately by switching the control voltage applied to the field-effect transistor of the second conductivity type from said gate line is configured to the pixel electrode, to achieve the above object.

[0014]

[0015]

The liquid crystal display device of the present invention is, for example,
As described in claim 2, field effect transistors of the same conductivity type are connected to each other using a common gate wiring between adjacent pixels, and the same control voltage is supplied so that two lines are simultaneously selected. May be.

The liquid crystal display device of the present invention is, for example,
As described in claim 3, a control voltage which is alternately inverted for each frame or each field may be applied to the gate wiring.

[0018]

In the liquid crystal display device according to the first aspect, the switching element provided for each pixel is constituted by connecting the field effect transistors of the first conductivity type and the second conductivity type in parallel, and they are adjacent to each other in the column direction. The field effect transistors of the same conductivity type are connected to each other using a common gate wiring between the pixels so that one field effect transistor between the pixels adjacent in the column direction is simultaneously switched and the field effect transistors are configured for each pixel. The display voltage is applied to the pixel electrode by alternately switching the first conductivity type field effect transistor and the second conductivity type field effect transistor with the control voltage applied from the gate line.

Therefore, in each pixel, the jump-in voltage waveform output via one conductivity type field effect transistor and the jump-in voltage waveform output via the other conductivity type field effect transistor should be canceled each other. As a result, the DC component of the voltage applied to the liquid crystal is eliminated, and good image quality with little liquid crystal deterioration can be obtained. Further, among the first conductivity type and second conductivity type field effect transistors connected in parallel for each pixel, one field effect transistor between adjacent pixels in the column direction is supplied with a control voltage from a common gate line. Switch with. Therefore, the number of gate wirings can be reduced and the aperture ratio of each pixel can be increased.

[0020]

[0021]

[0022]

According to another aspect of the liquid crystal display device of the present invention, a pair of field effect transistors of the same conductivity type are connected to each other by using a common gate wiring between adjacent pixels, and the same control voltage is supplied to switch two lines at a time. Line driving is performed. Therefore, as the number of gate wirings decreases, the aperture ratio increases and pair line driving can be easily realized.

According to another aspect of the liquid crystal display device of the present invention, a control voltage which is alternately inverted for each frame or each field is applied to the gate wiring.

Therefore, the direct current component of the voltage applied to the liquid crystal is eliminated, and good image quality with little deterioration of the liquid crystal can be obtained.

[0026]

EXAMPLES The present invention will be described below based on examples.
1 to 4 are views showing an embodiment of the liquid crystal display device of the present invention. First, the configuration will be described. FIG. 1 is a cross-sectional view of a TFT arranged in each pixel of a liquid crystal display device 10 according to this embodiment, and this TFT is a bottom gate type in which a gate electrode is provided on the substrate side.

In this embodiment, two types of switching elements, an n-channel TFT and a p-channel TFT, are used as the switching elements of the active matrix type liquid crystal display device provided for each pixel. The liquid crystal display device 10 of FIG.
The cross-sectional structure in the case of an n-channel TFT will be described, which is formed by stacking book films by vapor deposition sputtering, plasma CVD, etching, or the like. The other p-channel TFT is arranged, for example, in the depth direction of FIG.

In the liquid crystal display device 10 shown in FIG. 1, a gate electrode G forming a part of a thin film transistor (TFT) is formed on a glass substrate 11 at a predetermined position. Here, in the conventional example shown in FIG. 6, the auxiliary capacitance electrode 12 for generating the auxiliary capacitance Cs is formed between the pixel electrode 16 and the pixel electrode 16 at the position of the broken line on the glass substrate 11 of FIG. The jump voltage ΔVGS component included in the generated drive waveform is reduced. However, the auxiliary capacitance electrode 12 reduces the aperture ratio and reduces the writing speed.

For this reason, in the present embodiment, the jump voltage ΔVGS is made small without forming the auxiliary capacitance electrode 12 so that no direct current component is applied to the liquid crystal.
That is, in this embodiment, an n-channel TFT and a p-channel TF are used as a switching element provided for each pixel.
Ts are connected in parallel and switched alternately. This n
The jump voltage ΔVGS component generated in the channel TFT and the p-channel TFT shifts the drive waveform applied to the liquid crystal to the positive side and the negative side, respectively, so that the jump voltage ΔVGS components generated in the drive voltage waveform are offset to each other, and It eliminates the ingredients.

Returning to FIG. 1 again, the gate electrode G on the glass substrate 11 is connected to the gate line arranged in the row direction of the liquid crystal display panel. And the gate electrode G
The entire upper surface of the glass substrate 11 is covered with silicon nitride (Si
Insulating film 1 made of N) or silicon oxide (SiO)
3 is formed. Then, on the upper surfaces of the gate electrode G and the insulating film 13, the semiconductor layer 14 forming a part of the thin film transistor is patterned and formed in a predetermined shape.

A central portion of the semiconductor layer 14 corresponding to the gate electrode G is formed as a channel region 14a, and n-type high-concentration impurity ions (n + -Si) are formed on both left and right sides thereof.
Drain region 14b and source region 14c diffused
Are formed.

Next, an interlayer insulating film 15 is formed on the upper surface of the insulating film 13 including the semiconductor layer 14, and a pixel electrode 16 made of ITO (Indium Tin Oxide) is formed on the interlayer insulating film 15. Has been done. Then, the drain region 14b and the source region 14c of the interlayer insulating film 15 are formed.
The contact holes 17, 1 are provided in the portion corresponding to the upper part of
8 is formed. These contact holes 17, 18
A drain electrode D and a source electrode S made of aluminum and forming a part of the TFT are formed on the portion. The drain electrode D is connected to the drain line 35 shown in FIG. 2, and the source electrode S is connected to the pixel electrode 16.

An alignment film 19 for controlling the alignment of liquid crystal molecules is formed on the pixel electrode 16, the source electrode S and the drain electrode D, and the liquid crystal 20 is further arranged thereon.

Further, a common electrode made of ITO and a glass substrate (not shown) are arranged on opposite surfaces sandwiching the liquid crystal 20 to form a liquid crystal display panel. A liquid crystal capacitance CLC is formed by the above-mentioned pixel electrode 16, the common electrode arranged to face the pixel electrode 16 and the liquid crystal 20 between them. In addition, the silicon (Si) of the TFT in the above-described embodiment includes amorphous silicon, polysilicon,
Single crystal silicon is used.

FIG. 2 is a circuit diagram for each pixel of the liquid crystal display device of this embodiment. In the active matrix type liquid crystal display device of the present embodiment, the switching element is formed by connecting the drains and sources of the n-channel TFT and the p-channel TFT for each pixel and connecting them in parallel. FIG. 2 shows a circuit for two pixels in the first column of the first row and the second row.

The upper pixel in FIG. 2 is the n-channel TFT 3
6 and a p-channel TFT 37, and gate lines 31 and 32 unique to each gate electrode are separately connected. The gate lines 31 and 32 have
The n-channel TF is set according to the scan timing for each odd / even frame (or odd / even field).
A gate pulse signal for alternately turning on T36 and p-channel TFT 37 is applied.

Further, the gate line 3 of the lower pixel of FIG.
Similarly, 3 and 34 have an n-channel TFT 38 and a p-channel TFT for each odd / even frame (or field).
A gate pulse signal is applied so that 39 is alternately turned on. The liquid crystal display device of this embodiment is configured as described above, and its operation will be described below.

FIG. 3 is a time chart of the gate pulse signal applied to the switching element of this embodiment and the drive voltage waveform. FIG. 3A shows the reference voltage V of the common electrode.
With respect to COM, drain voltage VD (diagram indicated by a broken line) as a video signal input to the drain side of the TFT, and T
The source voltage VS (diagram indicated by the solid line) applied to the liquid crystal by the switching of the FT is shown. Also, FIG.
3B shows the gate pulse signal VGN applied to the gate electrode of the n-channel TFT 36, and FIG. 3C shows the gate pulse signal VGP applied to the gate electrode of the p-channel TFT 37.

Therefore, when interlaced scanning is performed by the liquid crystal display device of this embodiment, a video signal is written in each pixel arranged in a matrix on the liquid crystal display panel for each frame (2 fields), and the video signal is written. Are inverted every frame.

In this embodiment, the video signal is written by alternately switching the n-channel TFT and the p-channel TFT of the switching element of each pixel in the odd frame and the even frame.

That is, as shown in FIG. 2, in an odd frame, the gate line 31 to the n-channel TFT 36 are used.
By applying high level data (VGH) as the gate pulse signal VGN shown in FIG.
The TFT 36 is turned on, and the drain line 35 is negative (inverted).
By supplying the drain voltage VD of
Write. At this time, as shown by the white arrow C in FIG. 3A, a source voltage VS deviated from the drain voltage VD to the negative side by the jump voltage ΔVGS is generated.

Next, as shown in FIG. 2, in an even frame, low level data (VGL) is supplied from the gate line 32 to the gate electrode of the p-channel TFT 37 as the gate pulse signal VGP shown in FIG. 3C. Apply TF
The liquid crystal capacitance CLC is written by turning on T37 and supplying a positive (non-inverted) drain voltage VD to the drain line 35. At this time, as shown by the white arrow D in FIG. 3A, a source voltage VS deviated from the drain voltage VD to the positive side by the jump voltage ΔVGS is generated.

The absolute value of the jump voltage ΔVGS indicated by the arrows C and D is the gate-source parasitic capacitance C
GS, liquid crystal capacity CLC, high level data V of gate voltage
When the value obtained by subtracting the low level data VGL from GH is VGHL, it is expressed by the following equation.

[0044]

[Equation 2] In the above equation, since the TFT characteristics such as mobility are not included, even if there is a slight characteristic difference between the n-channel TFT and the p-channel TFT, the absolute value of the jump voltage ΔVGS generated during switching is almost the same. Become.

Therefore, in the present embodiment, the jump voltage ΔVGS generated at the time of switching the TFT is used in reverse,
By alternately using the n-channel TFT and the p-channel TFT, the waveform of the source voltage VS can be made symmetrical with respect to the reference voltage VCOM, and the direct current component applied to the liquid crystal can be removed. Therefore, it is possible to avoid image quality deterioration such as afterimage and liquid crystal deterioration.

Next, FIG. 4 is a diagram showing a circuit configuration of a liquid crystal display device according to another embodiment. In the present invention, the n-channel and p-channel TFTs of the switching element for each pixel are connected in parallel, but in the embodiment of FIG. 4, the gate line is shared between the pixels adjacent in the column (up and down direction) direction. There is a feature in doing it.

That is, as shown in FIG.
In each pixel of row 3 and row 3, from the gate line 41,
A gate pulse is supplied to the n-channel TFT 46 of the pixels on the first row. In addition, the gate line 42 includes a p-channel TFT 47 of the first row pixel and a p-channel T of the second row pixel.
The same gate pulse is supplied to the FT 48. Further, the gate line 43 is the n-channel TFT 49 of the pixel in the second row.
And the same gate pulse is supplied to the n-channel TFTs 50 of the pixels in the third row. The gate line 44 supplies the same gate pulse to the p-channel TFT 51 of the pixel on the third row and the p-channel TFT of the pixel on the fourth row (not shown).

As described above, by configuring the TFTs of the same conductivity type to share the gate line between the adjacent pixels, it is possible to reduce the number of wirings of the gate line and increase the aperture ratio accordingly. Therefore, the light transmittance can be improved and the brightness of the liquid crystal display screen can be increased.

In the case of the liquid crystal display device shown in FIG. 4,
There is an advantage that pair line driving in which two scanning lines of liquid crystal are simultaneously driven can be easily performed. This is because in the case of pair line driving in the conventional liquid crystal display device, it is necessary to control the application timing of the gate pulse in the odd rows and the application timing of the gate pulse in the even rows in a complicated manner.

On the other hand, in the case of the liquid crystal display device shown in FIG. 4, since the gate line is shared between the adjacent rows, when a gate pulse is applied to a predetermined gate line,
Two rows can be simultaneously selected, and pair lines are driven based on a video signal supplied from the drain line 45 at the time of selection.

For example, as shown in FIG. 4, in the odd-numbered field, the gate line 42 is used for the first and second rows, the gate line 44 is used for the third and fourth rows (not shown), ... In this way, the video signals are written simultaneously in two lines in a pair. In the even field, the gate line 43 is used for the second and third lines, the gate line (not shown) is used for the fourth and fifth lines, and so on. You can write

As described above, when pair line driving is performed using the liquid crystal display device shown in FIG. 4, in the case of interlaced driving in which two fields form one frame, a video signal is written in each pixel in each field. The voltage holding time in each pixel can be shortened as compared with the case where the video signal is written in each frame in the above embodiment.

Further, as described above, in the odd field and the even field which are pair-line driven, the pixels are vertically displaced by one row, so that high image quality display can be performed without lowering the vertical resolution. Furthermore, in the case of the above-described embodiment, the n-type gate line driving the gate of the n-channel TFT in the odd field and the p-type gate line driving the gate of the p-channel TFT in the even field are sequentially scanned, and automatically. Because it can be pair line driven,
Pair line driving can be performed with a simpler configuration than that of a conventional liquid crystal display device.

The structure of the TFT of the liquid crystal display device of the present invention is not limited to the bottom gate type described above, and TFTs having other structures can be adopted.
Further, the preferred embodiment of the present invention is to improve the aperture ratio by not forming the CS electrode. However, even when the CS electrode is provided, the above-mentioned actions are exactly the same, and therefore the present invention Can be naturally applied to a liquid crystal display device having a CS electrode.

[0055]

According to the liquid crystal display device of the first aspect,
Since different conductivity type field effect transistors are provided in each pixel and a gate pulse is applied so that switching is performed alternately, the ΔVGS component of the jump voltage of the source voltage VS applied to the liquid crystal is positive and negative. Since they appear alternately on both sides, the waveform of the source voltage VS applied to the liquid crystal becomes symmetrical with respect to the reference voltage VCOM of the common electrode, the DC component is eliminated, and high image quality is obtained and liquid crystal deterioration is prevented. You can Further, among the field effect transistors of different conductivity types connected in parallel for each pixel, one field effect transistor between adjacent pixels in the column direction is switched by the control voltage supplied from the common gate line, The number of wirings can be reduced and the aperture ratio of the liquid crystal display panel can be increased.

[0056]

[0057]

According to the liquid crystal display device of the second aspect, the field effect transistors of the same conductivity type are connected to each other by using the common gate wiring between the adjacent pixels, and the same control voltage is supplied to switch every two lines. Since the pair lines are driven in this manner, the aperture ratio increases as the number of gate lines decreases, and the pair lines can be easily driven.

According to the liquid crystal display device of the third aspect, since the control voltage which is alternately inverted for each frame or each field is applied to the gate wiring, the DC component of the voltage applied to the liquid crystal disappears, and the liquid crystal deteriorates. And good image quality can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a TFT arranged in each pixel of a liquid crystal display device according to an embodiment.

FIG. 2 is a circuit diagram of each pixel of the liquid crystal display device of the present embodiment.

FIG. 3 is a time chart of a gate pulse signal and a drive voltage waveform applied to the switching element of this embodiment.

FIG. 4 is a diagram showing a circuit configuration of a liquid crystal display device according to another embodiment.

FIG. 5 is a circuit diagram for each pixel of a conventional liquid crystal display device.

FIG. 6 is a circuit diagram of each pixel of another conventional liquid crystal display device.

FIG. 7 is a waveform diagram illustrating a problem of a conventional example.

[Explanation of symbols]

10 Liquid crystal display device 11 glass substrate 12 Storage capacitor electrode 13 Insulating film 14 Semiconductor layer 15 Interlayer insulation film 16 pixel electrodes 17,18 Contact hole 31, 32, 33, 34 Gate line 35 drain line 36, 38 n-channel TFT 37, 39 p-channel TFT

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/133 550 G09G 3/36

Claims (3)

(57) [Claims] 1. A pixel electrode arranged to face a common electrode of a liquid crystal display panel via a liquid crystal is arranged in a matrix, and a gate electrode of a switching element provided for each pixel is alternately changed from a gate wiring. In a liquid crystal display device, in which a predetermined control voltage is applied to bring a pixel into a selected state, and a predetermined display voltage which changes alternately from the drain wiring is applied to the pixel electrode in the selected state to perform display control, the switching element is of a first conductivity type. A field effect transistor of the second conductivity type is connected in parallel, and field effect transistors of the same conductivity type are connected to each other in the column direction by using a common gate wiring between pixels adjacent in the column direction. One field effect transistor between adjacent pixels is simultaneously switched, and a field effect of a first conductivity type and a second conductivity type formed for each pixel. The liquid crystal display device, characterized in that the display voltage alternately by switching the control voltage applied from the gate wiring transistor is applied to the pixel electrode. 2. A field effect transistor of the same conductivity type is connected to each other by using a common gate line between adjacent pixels, and the same control voltage is supplied to simultaneously select two lines. 1. The liquid crystal display device according to 1. 3. The liquid crystal display device according to claim 1, wherein a control voltage which is alternately inverted for each frame or each field is applied to the gate wiring.