JP3531081B2 - Semiconductor device, method of manufacturing the same, and verifying method using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for determining a current or a voltage of a semiconductor device such as a floating gate type nonvolatile memory and a method of manufacturing the same.
And a verification method using the same.

[0002]

2. Description of the Related Art In a floating gate type non-volatile semiconductor memory device, cells in an array are "0" and "1".
At the time of determination, the current flowing in the cell under a predetermined condition and the current flowing in the standard transistor are compared by a differential amplifier, and this standard transistor is called a reference cell.

In order to maintain the similarity with the cells in the array, such a reference cell is formed to have the same structure as the array cell or a so-called dummy cell type in which a control gate and a floating gate are connected. It is common. That is, the reference cell array is a miniature version of the cell array.

Further, in a reference for determining the output of a logic device, the reference level is generally limited to the threshold value of the transistor used in the device.

[0005]

By the way, in recent years, the characteristics of devices have been diversified, and it is necessary to judge "0", "0.5", "1", etc., as in a multi-valued memory, for example. ing.

In response to such a demand, in the conventional approach, a plurality of sense amplifiers having different sense ratios are prepared to cope with diversification of devices, that is, multi-valued.

However, this method has a problem that the circuit area increases, the chip area increases, and the cost increases.

On the other hand, in the non-volatile semiconductor memory device, at the time of verify for confirming the threshold value of the memory cell after programming or erasing, the verify voltage is changed according to the state to be verified. However, when the verification is performed in this way, there is a problem that the circuit of the voltage supply circuit becomes complicated.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same which can cope with diversification of devices without causing the above problems. And

Another object of the present invention is to provide a verifying method which can verify a memory cell by using such a semiconductor device without complicated voltage setting.

[0011]

Means for Solving the Problems The present invention is provided to solve the above problems, a first, a plurality of reference cells thresholds are different, and a selection circuit for selecting one of these Semiconductor device, wherein each of the reference cells
Is formed on a semiconductor substrate having a main surface and the main surface.
Source and drain and the source and drain of the main surface.
Provided via an insulating film on the channel region between the rain
Floating gate and the
It has a control gate and a control gate of these reference cells.
The gate between the loading gate and control gate
Provided is a semiconductor device characterized in that the passivities are different among a plurality of reference cells .

[0012]

[0013] Second, a plurality of threshold values are different Reference
And a selection circuit that selects one of these
A semiconductor device having a main surface, a source and drain formed on the main surface, and a channel region between the source and drain of the main surface. A floating gate provided via an insulating film and a control gate provided on the floating gate are provided, and the area of a portion of the surface of the reference cell facing the control gate of the floating gate corresponding to the control gate has a plurality of areas. There is provided a semiconductor device characterized in that the reference cells are different.

Thirdly, a plurality of reference cells thresholds are different, and a semiconductor device that includes a selection circuit for selecting one of these, each reference cell, the has a major surface A floating gate provided on a semiconductor substrate of one conductivity type, a source and a drain of a second conductivity type formed on the main surface of the semiconductor substrate, and a channel region between the source and the drain of the main surface via an insulating film. When,
A conductive cap continuously provided on the floating gate so as to project from the floating gate; and a control gate provided on the floating gate via an insulating layer. The conductive cap has a plurality of areas. Provided is a semiconductor device characterized by being different between cells.

[0015] Fourth, in the above apparatus, the conductive cap of each reference cell, to provide a semiconductor device characterized by being formed from the same conductive layer.

Fifth , there is provided a method of manufacturing a semiconductor device comprising a plurality of reference cells having different threshold values, and a selection circuit for selecting one of the reference cells, which is on a semiconductor substrate of the first conductivity type. A step of forming a first insulating film, a step of forming a first conductive film to be a floating gate of each reference cell on the first insulating film,
Etching the conductive film to form the floating gate of each reference cell, forming a diffusion region serving as a drain and a source of each reference cell on the main surface of the semiconductor substrate, and between the floating gates. forming a second insulating film, and forming the over floating gate and a second insulating film of each reference cell, the second conductive film to be the conductive cap of each reference cell, off O Etching the second conductive film by lithography to form conductive caps having different areas in each reference cell so as to protrude from the floating gate; and a step of forming the second insulating film and the conductive cap. A step of forming a third insulating film on the third insulating film, and a control gate on the third insulating film. To provide a method of manufacturing a semiconductor device characterized by a step of forming a third conductive film to be the bets.

Sixth , there is provided a method of manufacturing a semiconductor device comprising a plurality of reference cells having different thresholds, and a selection circuit for selecting one of the reference cells, wherein the semiconductor device is of a first conductivity type. in step a, said first forming a first conductive film to be the floating gate of each reference cell on the insulating film, the first conductive by off O preparative lithography to form a first insulating film Etching the membrane,
Forming floating gates having different areas in each reference cell; forming diffusion regions serving as drains and sources of each reference cell on the main surface of the semiconductor substrate; the first insulating film and the floating region; providing a step of forming a second insulating film, a method of manufacturing a semiconductor device characterized by a step of forming a second conductive film to be the control gate on said second insulating film on the To do.

[0018] Seventh, and a plurality of reference cells thresholds are different, a semiconductor device that includes a selection circuit for selecting one of these, each reference cell, a semiconductor having a major surface It has a 1-poly EPROM structure including a substrate, a read transistor section and a control gate section formed on the main surface thereof, and a common floating gate provided on the read transistor section and the control gate section. According to another aspect of the present invention, there is provided a semiconductor device, wherein a ratio of an area of a portion where the floating gate and the active region overlap in the gate portion and an area of a portion where the floating gate and the active region overlap in the read transistor portion differ between the reference cells. provide.

Eighthly, there is provided a verifying method using the semiconductor device according to any one of the second to fourth embodiments, wherein a constant voltage is applied to the plurality of reference cells and the memory cells, and the verification target at that time is applied. Provided is a verification method characterized by performing verification by comparing the current of a semiconductor device to be compared with the current of each reference cell.

According to the first aspect of the present invention, any one of the plurality of reference cells having different thresholds is selected by the selection circuit and is used for the cell determination without using a plurality of sense amplifiers. Supporting diversification of devices
The reference cell floating gate and
The capacitance between the control gate and
Gate capacitors can be made different by differentiating between them.
The pull ratio can be different, which allows the referenc
The cell thresholds can be different.

[0021]

According to the second aspect of the present invention, a plurality of different threshold values are used.
Number of reference cells
Selected and used to determine the cell
When dealing with diversification of devices without using
In addition, the area of the portion of the floating gate facing the control gate corresponding to the control gate is made different between the plurality of reference cells, which makes the capacitance between the floating gate and the control gate different, so that a complicated process , The threshold value of the reference cell can be made different.

According to the third aspect of the invention, in each reference cell, a conductive cap is provided so as to be continuous with the floating gate and project from the floating gate, and the areas of the conductive caps are made different between the reference cells. Since the capacitance between the floating gate and the control gate integrated with the conductivity cap is made different, the threshold value of the reference cell can be made different without adding a complicated process.

According to the fourth invention, since the conductive caps of the reference cells are formed of the same conductive layer, the conductive caps can be formed by a simple process.

According to the fifth and sixth aspects of the invention, the floating gate of each reference cell or the area of the conductive cap continuously provided on the floating gate is provided by using the openings of different sizes in the single mask. The reference cells having different thresholds can be realized by a simple process.

According to the seventh aspect of the invention, 1 poly is provided with a read transistor section and a control gate section, and a common floating gate provided on the read transistor section and the control gate section.
In a plurality of reference cells of the type EPROM structure,
The ratio of the area of the overlapping portion of the floating gate and the active region in the control gate portion to the area of the overlapping portion of the floating gate and the active region in the read transistor portion is made different between the reference cells, and thereby the gate couple ratio is increased. Since they are made different, the threshold value of the reference cell can be made different also in this case without adding a complicated process.

According to the eighth aspect of the present invention, the difference in the threshold voltage of the reference cell can be replaced with the difference in the verify voltage, so that the complicated voltage setting is not necessary.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below.

FIG. 1 is a diagram showing a configuration of a determination circuit in which a reference device according to an embodiment of the present invention is incorporated.

This circuit comprises a semiconductor cell to be judged 1, a reference device 2, and a sense amplifier (differential amplifier) 3 connected to these. This sense amplifier 3
Compares the current flowing in the cell 1 with the current flowing in the reference device under a predetermined condition.

The reference device 2 includes a reference selection circuit 4 and three reference cells 5, 6 and 7 having different threshold values. Either is selected. These reference cells are semiconductors of the same type as the semiconductor cell 1 and are formed in the same cell array.

A plurality of semiconductor cells 1 are arranged to form a cell array 10 as shown in FIG.
Reference numerals 6 and 7 form a reference cell array as shown in FIG.

For example, a non-volatile semiconductor memory is used as the cell 1, and semiconductors of the same type are used as the reference cells 5, 6 and 7 of the reference device 2, and the reference device 2 is used for program verification. And
As shown in FIG. 4, at the verify voltage V _d0 , the cell in which the program is stopped when the current becomes I _d1 and the current is I _d1
cells to stop the execution of the program when turned _d2, by causing current to correspond to the respective cell reference cells 5, 6 and 7 for stopping the execution of the program when turned I _d3, cells were not programmed, the cell of I _d1, I _d2 It is possible to form four levels of multi-valued memory of the cells of I _d3 and I _d3 . That is, it is possible to deal with a multi-valued memory without increasing the circuit area due to the use of a plurality of sense amplifiers.

Incidentally, FIG. 5 shows the I-d of the semiconductor cell at this time.
Show the characteristics. Further, FIG. 6 shows an example of cell threshold distribution in the case of program low. Here, program low means an operation of lowering the threshold voltage of a memory cell, or a state in which the threshold voltage becomes lower after such a program operation (“'94 Symposiumu on VLSITe”).
chnology, pp. 97-98). In the exemplary embodiment described in this document, in the program operation, -8V is applied to the selected word line and 5V or 0V is applied to the drain. Is applied, electrons are emitted from the floating gate to the drain, and the threshold voltage of the memory cell becomes low.

FIG. 6 shows an example in which program low is carried out after simultaneous erasing in the time mode without verifying. When verifying V ₊₀ with I _d1 , the program level is V ₊ corresponding to I _{d2. 1} , there are three levels obtained by adding V ₊₂ corresponding to I _d3 .

Next, a structural example of the reference cell will be described.

Here, an example using a Poly-Si cap type floating gate cell will be described. Poly
-Si cap type floating gate cell is shown in U.S. Pat. No. 4,833,514 and has a structure as shown in FIG. That is, the p-type substrate 21
An n-type source 22 and a drain 23 are formed on the main surface of, and a poly-Si floating gate 2 is formed on a channel region 24 between them via a gate insulating film 25.
6 is formed, and a Poly-Si cap 27 is further formed thereon. A control gate 29 made of Poly-Si is formed on the Poly-Si cap 27 via an interlayer insulating layer 28 made of ONO (oxide-nitride-oxide). An insulating layer 30 is formed on the side of the floating gate 26.

The floating gate 26 is provided so as to cover the channel region 24, and the Poly-Si layer on the floating gate 26 is provided.
The cap 27 has an eaves shape that covers a part or all of the source 22 and the drain 23 or a part of an element isolation region such as a field oxide film. And this Poly-
The Si cap 27 functions as a part of the floating gate 26. By providing this Poly-Si cap 27, the capacitance between the floating gate and the control gate can be increased.

Here, the threshold value of the reference cell is
Since the capacitance can be controlled by changing the capacitance between the floating gate and the control gate to change the gate coupling ratio, the area of the Poly-Si cap 27 is made different in the above structure, and the Poly-Si cap 27 and the control gate 29 are made different.
The threshold values can be made different by changing the area of the portion where and overlap.

For example, as shown in FIGS. 8A to 8C, the threshold value of the reference cell can be set to three levels by setting the area of the Poly-Si cap to three types. That is, the Poly-Si cap 2 shown in (a)
The reference cell having No. 7 is made to correspond to the above-mentioned reference cell 5, and as shown in (b) and (c), the Poly-Si cap 27 is sequentially lengthened (that is, the area is increased)
The reference cells having ', 27''are made to correspond to the reference cells 6 and 7 described above.

Next, an example of the manufacturing process of these reference cells will be described with reference to FIG.

First, a gate insulating film made of, for example, silicon oxide is formed on the p-type substrate 21, and a first Poly-Si film for a floating gate is formed thereon. The first Poly-Si film is etched by a general photolithography process to form the floating gate 26 corresponding to each reference cell. Next, the source 22 and the drain 23 of each reference cell are formed on the main surface of the semiconductor substrate 21 by ion implantation (see FIG. 9A).

Next, after forming an insulating film on the entire surface, it is etched back to form an insulating film 30 made of, for example, silicon oxide between the floating gates 26 of the reference cells (see FIG. 9B).

Next, a second Poly-Si film is formed, and subsequently, a mask having a plurality of openings each having a different length (area) corresponding to the Poly-Si cap of each reference cell is used to perform a photo process. Second Po by lithography
By etching the ly-Si film, conductive caps 27, 27 'having different areas in each reference cell,
27 ″ is formed so as to project from the floating gate 26 (see FIG. 9C).

Next, the Poly-Si caps 27, 27 ',
27 ″ and the insulating film 30, an interlayer insulating layer 28 made of ONO (oxide-nitride-oxide) is formed,
Further, a control gate 29 made of Poly-Si is formed thereon (see FIG. 9D).

Through the above steps, a plurality of reference cells having different threshold values can be formed.

As described above, in the photolithography process at the time of processing the Poly-Si cap, a complicated process is added only by placing patterns having different lengths (areas) of the Poly-Si cap on the mask. Instead, it is possible to manufacture a plurality of reference cells having different threshold values by using a very general thin film forming technique and photolithography technique. That is, the threshold value of the reference cell can be made different by a simple process such as forming patterns having different sizes at the reticle stage to improve the mask.

In the above cell, a Poly-Si cap is provided on the floating gate, but such a cap is not provided and the floating gate itself is provided with a Poly-Si cap.
-It may have a function of Si cap. A cell having such a structure is shown in FIGS. FIG. 10 is a plan view showing a part of a cell array of such cells, FIG. 11 is a sectional view taken along the line XX ', and FIG. 12 is a sectional view taken along the line YY'.
As shown in these figures, in this cell, the floating gate 37 covers a part of the source 32 and the drain 33 and a part of the element isolation region 36. The specific structure of this cell is shown in FIGS.
Is shown in. That is, n is formed on the main surface of the p-type substrate 31.
A source 32 and a drain 33 of the mold are formed, and a gate insulating film 35 is formed on the channel region 34 between them. Then, on the gate insulating film 35, Po
A floating gate 37 of ly-Si is formed, and a control gate 39 made of Poly-Si is further formed thereon via an interlayer insulating layer 38 made of, for example, ONO (oxide-nitride-oxide). There is. Then, these cells are separated by the element isolation region 36.

In the cell having such a configuration, the capacitance between the floating gate and the control gate is changed by changing the area of the floating gate 37 and the area of the overlapping portion of the floating gate 37 and the control gate 39. The threshold value can be controlled by changing the gate couple ratio. Also in this case, when forming the floating gate, as described above, a mask having a plurality of openings having different lengths (areas) corresponding to the floating gates of the reference cells may be used. There is no need to use complicated means of.

That is, first, a gate insulating film made of, for example, silicon oxide is formed on the p-type substrate 31, a first Poly-Si film for a floating gate is formed thereon, and the floating of each reference cell is performed. A first mask is formed by photolithography using a mask having a plurality of openings having different lengths (areas) corresponding to the gates.
The poly-Si film is etched to form floating gates having different areas in each reference cell.

After that, a diffusion region is formed, an insulating film between floating gates is formed, an interlayer insulating film is formed, and a control gate is formed by using a general process, so that a plurality of references having different threshold values are formed. A cell can be formed.

In this case, the width of the control gate may be changed in order to make the capacitance between the floating gate and the control gate different. Further, although the example in which the floating gate is extended in the direction orthogonal to the source / drain arrangement direction has been shown, it goes without saying that the floating gate may be provided so as to extend in the source / drain arrangement direction.

Next, another structural example of the reference cell will be described with reference to FIG.

Here, an example is shown in which the 1poly EPROM according to 1993 VLSI Symposium 52-A is used as a reference cell of a logic device. This cell has an n-well on a part of a p-type substrate 41.
42 is formed, and an n ⁺ -type source 43 and a drain 44 are formed in a portion other than the n-well 42.
A source 45 and a drain 46 are respectively formed in the portions of the above, and a common floating gate 49 is provided on the channel regions 47 and 48 between these via a gate oxide film (not shown). That is, NMO
It has a CMOS structure in which S and PMOS are combined. The source 43 and the drain 44 are connected to the power source 5
The voltage Ve is applied from 1, the source 45 and the drain 46 are grounded, the NMOS portion functions as a read transistor, and the PMOS portion functions as a control gate portion. Reference numeral 52 is a high-concentration region for improving the grounding characteristics.

In such a 1-poly EPROM structure, the gate couple ratio is such that the implantation amount of threshold ion implantation, the film thickness of the gate oxide film, and the floating gate and active region in the control gate portion (PMOS). It depends on the ratio of the area of the overlapping portion and the area of the overlapping portion of the floating gate and the active region in the read transistor portion (NMOS) (hereinafter referred to as the area ratio of the active region). Therefore, by making them different, the gate couple ratio can be changed, and thus the threshold values can be made different.

In this case, in the case of the method of changing the threshold ion implantation amount and the method of changing the film thickness of the gate oxide film, the number of steps is increased, but the area ratio of the active region is changed. The method is more preferable because there is no fear of increasing the number of steps. That is, the area ratio of the active regions is changed by changing the area (gate oxide film area) of the PMOS and NMOS channel regions in the device isolation region forming photo step or by changing the floating gate area in the floating gate forming photo step. Although the number of stages can be increased in this way, a simple method of improving the photomask in the same manner as in the above-mentioned example without increasing the number of steps is sufficient to change these areas.

It is clear that the reference cell thus manufactured has good compatibility with the logic. For example, the reference cells can be made at one time in the same process that makes a logic circuit.

As described above, when the reference device of the present invention is used for a logic device, output levels I _d1 , I _d2 , I are determined when the output from the logic circuit or its block is judged, for example, in three levels. _The output destination is changed according to _d3 , or for circuits A and B with different output levels,
It can be used as a reference for checking I _d1 -I _d2 for A and as a reference for checking I _d3 -I _d2 for B, and various applications are possible depending on the purpose. Further, the 1poly type EPROM structure is not limited to the CMOS structure, and the 1poly type EPROM structure is not limited to the CMOS structure.
All structures known as structures can be used.

Next, another embodiment of the present invention will be described.

FIG. 14 shows a state in which a voltage supply circuit 8 for supplying a voltage to each reference cell and memory cell of the reference device of FIG. 1 is connected.

Generally, in a nonvolatile semiconductor memory device such as a flash memory, the operation of confirming the threshold value of a memory cell after programming or erasing is called verify.

In general, in a memory cell, since a state with a high threshold value (V _thH ) and a state with a low threshold value (V _THL ) are verified with a sufficient margin, the voltage applied to the gate of the memory cell at the time of verification. (Verify voltage)
Changes depending on the state to be verified. That is, as shown in FIG. 15, a verify voltage V _GH is applied to verify V _thH , and a verify voltage V _GL is applied to verify V _THL . Here, V _GH is larger than V _GL .

On the other hand, a constant voltage V _R is applied to the reference cell regardless of the state to be verified, and a cell current I _{R serving} as a reference in the determined state is supplied. That is, a verify voltage is applied to a memory cell after programming or erasing, and the current flowing at that time is I _R
The verification is performed in comparison with. Here, the voltage V _D applied to the drain is the same in both the memory cell and the reference cell.

In the case of the reference device of this embodiment, as shown in FIG. 16, the verify voltage V _Gn (n =
1, 2, 3), the reference cell current I _dn (n
= 1,2,3).

By the way, in the present invention, the current value I _Rn of each reference cell for the same V _R is different. By utilizing this, as shown in FIG. 17, it is understood that the verification can be performed without setting the verify voltage for each cell state. That is, the verification is performed by comparing the cell current of the memory cell at a certain verify voltage V _{G0 with} the cell current of each reference cell. Now, V
When _G0 = V _R, a plurality of thresholds would be verifying a single gate voltage. This means that the difference in the threshold voltage of the reference cell is used as the difference in the verify voltage. In this case, since it is not necessary to use a plurality of verify voltages, the divider of the voltage supply circuit is not necessary, and the circuit The configuration can be simplified.

Further, by utilizing this fact, as shown in FIG. 18, more verify states at a plurality of verify voltages, that is, V _thL1 , V _thL2 , V _thL3 , and V _thL .
_It can be seen that _thH1 , V _thH2 , and V _thH3 can be created. At this time, the verify voltages applied to the memory cells are V _GL and V _GH , and V _R is applied to the reference cells.

By the way, the flash memory has a problem of a tail bit ("'93 Symposium on VLSI").
Technology ", pp.83-84). In particular, the low-threshold cell after electrons are extracted from the floating gate is
It causes problems such as leaks. As a measure against this problem,
Currently, techniques such as program back are proposed. Here, the program back means that all cells are collectively erased (F-
Writing is performed again (by N tunneling) (for example, the source and gate are set to 0 V, 5 V is applied to the drain, and hot electrons are injected to the floating gate), thereby reducing the distribution of the threshold. (IEDM 91-307 11.4.1-1
See 1.4.4). However, they are no longer valid at the multilevel. Therefore, a technique for limiting the threshold value of the memory cell to a narrow range at the time of verification is required. In the conventional method, after verifying that the memory cell current is I _R or more at the verify voltage V _G , the memory cell current is I at the verify voltage V _G −ΔV _G (<V _G ).
It is necessary to control the threshold voltage of the memory cell at many voltage levels, such as verifying that it is _R or less.

On the other hand, if the reference device of the present invention is used, such a verify operation becomes easier. That is, the same thing can be achieved by simply switching the reference cells without changing the verify voltage. Figure 1
As is clear from 6, since different reference cells have different current levels, the upper and lower limits of the memory level can be set only by switching the reference cells.

In the above embodiment, the case where the reference threshold level is 3 has been described, but the present invention is not limited to this, and may be set appropriately as needed. Needless to say, the type of the reference cell is not limited to that shown in the above example. That is, in the above example, the stacked gate type reference cell is used for the memory device, and the 1poly type EPROM structure reference cell is used for the logic device. However, the type of the reference cell is not limited to this and the type of the reference cell can be easily designed. Just select it.

Furthermore, in the above example, the devices having a plurality of threshold values are arranged in the same reference array, but it is also possible to form the reference block of each threshold level.

[0071]

As described above, according to the first invention, among the plurality of reference cells having different thresholds,
Since any one of them is selected by the selection circuit and used for the cell determination, it is possible to cope with the diversification of devices without using a plurality of sense amplifiers and avoid an increase in circuit area.

According to the second aspect of the present invention, the capacitance between the floating gate and the control gate of the reference cell is made different between the plurality of reference cells, so that the gate couple ratio can be made different. Can have different thresholds.

According to the third to sixth inventions, the area of the surface of the floating gate or the conductive cap continuously provided thereto facing the control gate is made different between the plurality of reference cells. Since the capacitance between the control gate and the control gate is made different, the threshold value of the reference cell can be made different only by improving the photomask without going through a complicated process.

According to the seventh invention, a 1-poly EPR
In a plurality of reference cells of the OM structure, the ratio of the area of the overlapping portion of the floating gate and the active region in the control gate portion to the area of the overlapping portion of the floating gate and the active region in the read transistor portion is set between the reference cells. Since the gate couple ratios are made different by making them different, the threshold value of the reference cell can be made different by only improving the photomask without going through complicated steps in this case as well.

According to the eighth aspect of the present invention, the difference in the threshold voltage of the reference cell can be replaced with the difference in the verify voltage, which eliminates the need for complicated voltage setting.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a determination circuit in which a reference device according to an embodiment of the present invention is incorporated.

FIG. 2 is a schematic diagram showing an example of a semiconductor cell array to which the reference device is applied.

FIG. 3 is a schematic diagram showing a reference array incorporating the reference device of the present invention.

FIG. 4 is a characteristic diagram showing VI characteristics of the reference device according to the embodiment.

FIG. 5 is a diagram showing a VI characteristic of a semiconductor cell to which the reference device according to the above-described embodiment is applied.

FIG. 6 is a diagram showing an example of cell threshold distribution in the case of program low.

FIG. 7 is a cross-sectional view showing an example of the structure of a reference cell used in the reference device of the present invention.

8 is a diagram showing an example in which the threshold values of the reference cells of FIG. 7 are made different.

FIG. 9 is a diagram for explaining a method of manufacturing a plurality of reference cells having different threshold values.

FIG. 10 is a plan view showing another example of the structure of the reference cell used in the reference device of the present invention.

11 is a cross-sectional view taken along the line XX ′ of FIG.

12 is a sectional view taken along line YY ′ of FIG.

FIG. 13 is a schematic view showing still another example of the structure of the reference cell used in the reference device of the present invention.

14 is a diagram showing a state in which a voltage supply circuit that supplies a voltage to each of the reference cells and memory cells of the reference device of FIG. 1 is connected.

FIG. 15 is a diagram showing a verification state of a general memory cell.

FIG. 16 is a diagram showing a general verify situation in the reference device of the present invention.

FIG. 17 is a diagram for explaining a verifying method of the present invention using a reference device.

FIG. 18 is a diagram showing a case where the verify method of the present invention is performed using a plurality of verify voltages.

[Explanation of symbols]

1 ... Semiconductor cell, 2 ... Reference device, 3 ... Sense amplifier, 4 ... Reference selection circuit, 5, 6, 7
... reference cell, 8 ... voltage supply circuit, 10 ... semiconductor cell array, 11 ... reference cell array,
21, 31, 41 ... Semiconductor substrate, 22, 32, 43,
45 ... Source, 23, 33, 44, 46 ... Drain, 24, 34, 47, 48 ... Channel region, 25,
35 ... Gate insulating film, 26, 37, 49 ... Floating gate, 27 ... PolySi cap, 28, 38
...... Interlayer insulating layer, 29, 39 ...... Control gate,
36 ... Element isolation region, 42 ... n-well

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/06 H01L 27/115 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] And 1. A threshold is different reference cells, and a selection circuit for selecting one of these
In each of the reference cells, each of the reference cells has a first conductivity type semiconductor substrate having a main surface, a second conductivity type source and drain formed on the main surface, and a source and drain of the main surface. Between the floating gate and the control gate of the reference cell, the floating gate provided on the channel region between the floating gate and the control gate provided on the floating gate of the reference cell via the insulating layer. A semiconductor device having a plurality of reference cells having different capacitances. 2. A plurality of reference cells having different thresholds.
And a selection circuit that selects one of these
In each of the reference cells , each of the reference cells has a first conductivity type semiconductor substrate having a main surface, a second conductivity type source and drain formed on the main surface, and a source and drain of the main surface. A floating gate provided via an insulating film on the channel region between and a control gate provided on the insulating layer via an insulating layer, and opposed to the control gates of the floating gates in these reference cells. A semiconductor device, wherein the area of a portion of the surface corresponding to the control gate is different among the plurality of reference cells. 3. A threshold is different reference cells, and a selection circuit for selecting one of these
In each of the reference cells, each of the reference cells has a first conductivity type semiconductor substrate having a main surface, a second conductivity type source and drain formed on the main surface, and a source and drain of the main surface. A floating gate provided on the channel region between the two via an insulating film, a conductive cap continuously provided on the floating gate so as to project from the floating gate, and an insulating layer on the conductive cap. A semiconductor device having a control gate provided, wherein the areas of the conductive caps are different among a plurality of reference cells. 4. The semiconductor device according to claim 3, wherein the conductive caps of the reference cells are formed of the same conductive layer. 5. A plurality of reference cells having different threshold values, and a selection circuit for selecting one of these reference cells.
And a step of forming a first insulating film on a semiconductor substrate of a first conductivity type, and a step of forming a floating gate of each reference cell on the first insulating film. A step of forming a conductive film; a step of etching the first conductive film to form a floating gate of each reference cell; and a diffusion region serving as a drain and a source of each reference cell on the main surface of the semiconductor substrate. Forming a second insulating film between the floating gates, and forming a second insulating film between the floating gates and the second insulating film on the floating gates of the reference cells and the second insulating film. forming a conductive film, off O Sorted by lithography etching the second conductive film, it in each reference cell Re forming such a different conductive cap in area protruding from the floating gate, the third on the second insulating film and the conductive cap
Semiconductors that of forming an insulating film, characterized by a step of forming a third conductive film to be the control gate on said third insulating film
Body device manufacturing method. 6. A plurality of reference cells having different thresholds, and a selection circuit for selecting one of these reference cells.
And a step of forming a first insulating film on a semiconductor substrate of a first conductivity type, and a step of forming a floating gate of each reference cell on the first insulating film. forming a conductive film, a step of etching the off O preparative lithography by the first conductive film, forming a floating gate having different areas respectively, in each reference cell, to the main surface of said semiconductor substrate, each reference cell Forming a diffusion region serving as a drain and a source of the second insulating film, and forming a second region on the first insulating film and the floating film.
Semiconductors that of forming an insulating film, characterized by a step of forming a second conductive film to be the control gate on the second insulating film
Body device manufacturing method. 7. A threshold is different reference cells, and a selection circuit for selecting one of these
And a semiconductor device, wherein each reference cell includes a semiconductor substrate having a main surface, and a read transistor unit and the control gate portion formed on the main surface, provided on these reading transistor section and the control gate section Lpoly type EPR with common floating gate
The reference cell has an OM structure, and the ratio of the area of the overlapping portion of the floating gate and the active region in the control gate portion to the area of the overlapping portion of the floating gate and the active region in the read transistor portion is different between the reference cells. Semi-conductor characterized by
Body device. 8. A base Rifai method using the semiconductor device according to according to any one of claims 2 to 4, a constant voltage is applied to said plurality of reference cells and memory cells, in which The verification method is characterized in that the verification is performed by comparing the current of the semiconductor device to be verified with the current of each reference cell.