JP3526316B2 - Video compression encoding method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention digitizes moving images,
The present invention relates to a moving picture compression coding method for compressing and coding the data.

[0002]

2. Description of the Related Art In a method of digitizing a moving image and compressing and coding the data, pixels of each frame are divided into grid-like blocks, and prediction and orthogonal transformation are appropriately combined for each block. Conventionally, a method of performing compression encoding by performing the above processing is generally used. For example, the international standard “ISO standard 11172
This method is adopted in (commonly called MPEG).

An encoding circuit according to the MPEG standard defines 8 × 8 pixels in one frame as one block, and further 2 ×
Macro block (16 x 1
(6 pixel size), and processing is performed in units of this macroblock. Therefore, the image size normally handled by MPEG is 16 × M pixels horizontally and 16 × N pixels vertically (M, N
Is a positive integer).

Here, when the image size to be processed is not an integral multiple of 16, the surplus portion is cut off, or the pixel is supplemented so that the multiple becomes 16. Which process is to be performed is often selected according to the application. For example, when a normal NTSC signal is digitized, one frame has 720 × 483 pixels, but if processing is performed in units of 16 pixels, there will be 3 pixels left in the vertical direction. When this signal is displayed on a general television, the remaining 3 pixels are outside the display range, and there is no problem even if this data is cut off and set to 720 × 480 pixels. On the contrary, when it is not appropriate to omit the information of the material such as editing the signal in the studio, the pixel can be processed as 720 × 496 by using interpolation.

[0005]

However, when interpolation is used here, it becomes redundant as much as data is added,
Does not fit the purpose of compression. In addition, when decoding and displaying the encoded signal, an extra process of cutting off the interpolated data is also required. On the contrary, when the data is cut off so as to be suitable for the block processing, the data included in the dropped data cannot be reproduced.

Therefore, the present invention solves the drawback that, when processing an image in block units, when the image size is not an integral multiple of the block size, the remaining pixels cannot be processed appropriately.

[0007]

According to the present invention, one screen is divided into a main area which is an integral multiple of a block and a sub-area which is a fractional part, and image information of each area is encoded by a different method and compressed. It is characterized in that it is processed and output from a common channel.

[0008]

Therefore, according to the present invention, the images of the main area and the sub area are subjected to conversion compression processing by different methods and output from the common channel.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an illustrated embodiment. FIG. 1 is a circuit block diagram of a moving picture compression / encoding circuit of this embodiment, and FIG. 2 is a diagram showing a divided configuration of an NTSC television screen of this embodiment. As is clear from FIG. 2, in the present embodiment, the NTSC effective video line includes a main area (720 dots × 480 lines) constituted by macroblocks (16 dots × 16 lines) as a unit, and a line segment (8 It is divided into sub-areas (720 dots × 3 lines) composed of dots × 1 line), the main area is subjected to two-dimensional orthogonal quantization and compression processing by MPEG, and the sub-area is subjected to one-dimensional orthogonal quantization and compression. It is characterized in that it is processed.

As is apparent from FIG. 1, image data of 483 effective video lines of one frame of NTSC is temporarily stored in the first frame memory 1. It should be noted that the frame to be stored is I for convenience of formation of MPEG data.
A frame processed as a picture or a P picture is stored in advance, and a frame positioned temporally between them and processed as a B picture is stored later.

Image data in the main area is output from the first frame memory 1 in macroblock units, and M
PEG data processing is executed. At the time of forming an MPEG I picture, image data in macroblock units is directly input to the two-dimensional DCT conversion circuit 5 via the first switch 4 and subjected to two-dimensional orthogonal conversion processing, and further the first quantization circuit 6
Is quantized. The quantized output is input to the variable length coding circuit 22 via the third switch 21 and output via the identification signal adding circuit 23. The identification code adding circuit 23 precedes the information of the first macroblock in the main area with a first identification code, for example, "0000001F".
E "is output, and the second identification code, for example," 0000001FF ", is output prior to the first line segment of the sub area.
Is output. When the I picture is formed, the quantized output is the first
Inverse quantization is performed by the inverse quantization circuit 7, and the first inverse two-dimensional D
The image data is inversely converted by the CT conversion circuit 8 and converted into original image data, which is stored in the second frame memory 12 via the fourth switch 9, the adder 10 and the fifth switch 11.

Next, at the time of forming an MPEG P picture, the image data in units of macroblocks is subtracted from the image data of the corresponding macroblock read from the second frame memory 12 by the subtractor 2 to obtain difference data. 1
It is input to the two-dimensional DCT transform circuit 5 via the switch 4 and subjected to a two-dimensional orthogonal transform process, and is further quantized by the first quantizer circuit 6. The quantized output is input to the variable length coding circuit 22 via the third switch 21 and output via the identification signal adding circuit 23. At the time of forming this P picture, the quantized output is inversely quantized by the first inverse quantization circuit 7, further inversely transformed by the first inverse two-dimensional DCT transformation circuit 8 and transformed into the original difference data, and the fourth difference data is obtained. It is input to the adder 10 via the switch 9. The adder 10 is added with the output of the second frame memory 12 input via the sixth switch to be converted into original image data, and the fifth switch 11
Is stored in the third frame memory 13 via.

By storing the image data in the two frame memories, the B picture processing of the subsequently input frame becomes possible. B picture processing is formed by I or P pictures that are temporally preceding and following. Next, MP
When forming the B picture of the EG, the image data is input to the subtractor 2 in macro block units. The output of the mixing circuit 14 is input to the subtractor 2 via the fifth switch 15. The mixing circuit 14 includes the image data of the corresponding macro block read from the second frame memory 12 and the third
The image data of the corresponding macro blocks read from the frame memory 13 are mixed, and the first frame memory 1
It forms data that is closer to the image data that is output. The subtractor 2 subtracts the approximate data from the image data output from the first frame memory 1 to form difference data. The difference data is input to the two-dimensional DCT conversion circuit 5 via the one switch 4, subjected to two-dimensional orthogonal transformation processing, and further subjected to quantization processing in the first quantization circuit 6. The quantized output is input to the variable length coding circuit 22 via the third switch 21 and output via the identification signal adding circuit 23.

The image data in the main area is subjected to the time-related conversion / compression processing by the MPEG conversion / compression method as described above. This method is well known as MPEG except for the identification code adding circuit, and the feature of this embodiment is the following configuration. In the present embodiment, the second, third and fourth switches are switched based on the output of the area control circuit, and the image data of the remaining sub-area is read from the first frame memory 1 in units of 8 dots to perform a one-dimensional DCT conversion process. Is going. This conversion processing is performed in accordance with the processing of I-pictures, P-pictures, and B-pictures in the main area, and the first, fifth, sixth, and seventh switches are kept as they are, and the processing timing is It is executed following the processing of the main area of each frame.

Therefore, immediately after the main area forms an I picture, the 8-dot unit segment data of the sub-area read from the first frame memory is passed through the first switch 3 and the second switch 4 to the one-dimensional DCT conversion circuit. 1
It is input to 7 and one-dimensional DCT conversion is performed. This converted output is quantized by the second quantizing circuit 18, then input to the variable length coding circuit 22 via the fourth switch and output via the identification code adding circuit 23. On the other hand, the second quantized output is inversely quantized by the second inverse quantization circuit 19, converted into the original image data by the inverse one-dimensional DCT conversion circuit, and the fourth switch 9, the adder 10, and the fifth switch 11
Is stored in the second frame memory 12 via.

Immediately after the P picture is formed in the main area, the 8-dot unit segment data of the sub-area read from the first frame memory is stored in the first area.
It is input to the subtractor 2 together with the corresponding segment data read from the frame memory 1, converted into difference data by subtraction processing, and input to the one-dimensional DCT conversion circuit 17 via the first switch 3 and the second switch 4. Then, one-dimensional DCT conversion is performed. This converted output is
After being quantized by the second quantization circuit 18, the variable length coding circuit 2 is passed through the fourth switch.
2 and is output through the identification code adding circuit 23.
On the other hand, the second quantized output is inversely quantized by the second inverse quantization circuit 19, converted into original image data by the inverse one-dimensional DCT conversion circuit, and then added by the adder 10 via the fourth switch 9.
Entered in. The adder 10 adds the corresponding segment data read from the second frame memory 10 and input through the sixth switch 15 and the seventh switch to convert the same into original image data, and the fifth switch 11 is operated. It is stored in the third frame memory 13 via the above.

Immediately after forming the B picture in the main area, the 8-dot unit segment data of the sub area read from the first frame memory is input to the subtractor 2. The subtractor 2 receives the corresponding segment data read from the second frame memory 12 and the third frame memory 13 from the sixth switch 15 as the data obtained by the mixing circuit 14 and uses it as the subtraction input. The difference data obtained by this subtraction processing is input to the one-dimensional DCT conversion circuit 17 via the first switch 3 and the second switch 4, and the one-dimensional D
CT conversion is performed. The converted output is quantized by the second quantizing circuit 18, and then input to the variable length coding circuit 22 through the fourth switch and output through the identification code adding circuit 23. .

As described above, in the present embodiment, I picture processing of the main area, independent one-dimensional processing of the sub area, P picture processing of the main area, subordinate dependent one-dimensional processing, B picture processing of the main area. , Sub-area dependent one-dimensional processing is sequentially performed. As a result, as shown in FIG. 3, in the encoded encoded data to be output, the encoded compressed data in the main area is preceded by the identification code 000001FF, and the encoded compressed data in the sub area is identified by 00.
0001FE is multiplexed first.

In the present embodiment, the motion vector is obtained and processed in the entire screen without distinguishing between the main area and the sub-area, but it is also possible to divide the area to obtain the motion vector if necessary. The operation of the decoding circuit of this embodiment shown in FIG. 4 will be described below. First, the I-picture data in the main area is subjected to a variable length decoding process in the variable length decoding circuit 24, and is input to the first dequantization circuit 26 via the eighth switch to be dequantized. After the inverse quantization, the inverse two-dimensional DCT conversion circuit 27 converts the original image data in macroblock units, and the image data in the main area is converted into the fourth frame memory through the ninth switch 28 and the tenth switch 29. Stored in 30. At the same time, the image data is stored in the fifth frame memory 32 via the eleventh switch 31. Next, when the sub-area data is input, the area detection circuit 39 detects the identification code and switches the eighth switch 25 and the ninth switch 28. Therefore, the variable-length decoded output is input to the second inverse quantization circuit 35 and subjected to inverse quantization processing. Inverse one-dimensional D after inverse quantization
The CT conversion circuit 36 converts the original image data, and the image data in the sub-area is converted into the fourth frame memory 30 via the ninth switch 28 and the tenth switch 29.
Memorized in. At the same time, the image data is stored in the fifth frame memory 32 via the eleventh switch 31.
The decoding process for the frame ends.

Then, when the P picture data of the main area is input, the area detection circuit 39 detects the identification code and switches the eighth switch 25 and the ninth switch 28. At the same time, the ninth, tenth and twelfth switches are also switched. The P-picture data is subjected to variable length decoding processing in the variable length decoding circuit 24, and is input to the first dequantization circuit 26 via the eighth switch to be dequantized. After the inverse quantization, the inverse two-dimensional DCT conversion circuit 27 converts the original difference image data and inputs the difference image data to the adder 37 via the ninth switch 28. The image data of the corresponding macroblock stored in the fifth frame memory 32 is input to the adder 37 via the twelfth switch, and the original image data is restored by addition. The restored image data is stored in the fourth frame memory 30 via the tenth switch 29. At the same time, the image data is stored in the sixth frame memory 32 via the eleventh switch 31. Next, when the sub-area data is input, the area detection circuit 39 detects the identification code and switches the eighth switch 25 and the ninth switch 28. Therefore, the variable length decoded output is the second inverse quantization circuit 35.
Is input to and subjected to inverse quantization processing. After the inverse quantization, the inverse one-dimensional DCT conversion circuit 36 converts the original difference data, and the difference data is input to the addition circuit 37 via the ninth switch 28. The image data of the corresponding line segment stored in the fifth frame memory 32 is stored in the adder 37 as the twelfth image data.
The original image data is input via the switch and restored by addition. The restored image data is stored in the fourth frame memory 30 via the tenth switch 29. At the same time, the image data is stored in the sixth frame memory 33 via the eleventh switch 31, and the decoding process for one frame is completed.

Further, when the B picture data of the main area is input, the area detection circuit 39 detects the identification code and switches between the eighth switch 25 and the ninth switch. The area detection circuit 39 detects the identification code and switches between the eighth switch 25 and the ninth switch 28.
The data of the B picture is subjected to a variable length decoding process in the variable length decoding circuit 24, is input to the first dequantization circuit 26 via the eighth switch, and is dequantized. After the inverse quantization, the inverse two-dimensional DCT conversion circuit 27 converts the original difference data, and the difference data is input to the adder 37 via the ninth switch 28. This adder 37 has the fifth
The image data of the corresponding macro blocks stored in the frame memory 32 and the sixth frame memory 33 is input to the mixing circuit 38, the original image data is input via the twelfth switch by a predetermined proportional distribution, and the addition is performed. The image data of the frame is restored. The restored image data is stored in the fourth frame memory 30 via the tenth switch 29. Next, when the sub-area data is input, the area detection circuit 39 detects the identification code and switches between the eighth switch 25 and the ninth switch. As a result, the variable length decoded output is the second inverse quantization circuit 35.
Is input to and is subjected to inverse quantization processing. After the inverse quantization, the inverse one-dimensional DCT conversion circuit 36 converts the original difference data, and the difference data is input to the addition circuit 37 via the ninth switch 28. The adder 37 includes the fifth frame memory 3
2 and the image data of the corresponding segment stored in the sixth frame memory 33 are input to the mixing circuit 38, the image data restored by a predetermined proportional distribution is input via the twelfth switch, and the image data of the frame is added by addition. The image data is restored. The restored image data is the first
It is input to the adder 37 via the 0 switch. The image data of the corresponding line segment stored in the fifth frame memory 32 is input to the adder 37 via the twelfth switch, and the original image data is restored by addition. The restored image data is stored in the fourth frame memory 30 via the tenth switch 29.
R> ru. At the same time, the image data is stored in the sixth frame memory 32 via the eleventh switch 31, and the decoding process for one frame is completed.

The encoded compressed data of each frame is restored by the procedure described above. However, there are cases where sub-codes are not required when decoding. Therefore, it is possible to omit the decoding of the sub-area. In that case, not only the memory capacity can be reduced, but also the circuit system relating to the one-dimensional processing can be omitted.

[0023]

According to the present invention, it is possible to effectively carry out the encoding process of a fractional pixel, which is a problem in the image compression encoding circuit based on the process of the macro block unit. Further, when decoding the encoded data, it is possible to omit the decoding depending on the necessity of the data of the fractional pixel.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an encoding circuit showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a frame structure of the present invention.

FIG. 3 is a data array explanatory diagram showing an embodiment of the present invention.

FIG. 4 is a circuit block diagram of a decoding circuit showing an embodiment of the present invention.

[Explanation of symbols]

17 One-dimensional DCT conversion circuit 18 Second Quantization Circuit 19 Second inverse quantization circuit 20 Inverse one-dimensional DCT conversion circuit 23 Identification code addition circuit 24 area switching control circuit

Continuation of the front page (56) Reference JP-A-6-217149 (JP, A) JP-A-6-237385 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 7 / 24-7/68 H04N 1/41-1/419

Claims (2)

(57) [Claims] 1. A moving picture compression coding method in which a screen is divided into blocks of a predetermined unit and data is compressed for each block. Data is compressed by encoding by orthogonal transformation , and image information of a sub area formed by a region other than the main area in the screen is encoded by orthogonal transformation based on a block size different from that of the main area and data is compressed, A moving picture compression encoding method, characterized in that both compressed data are output from a common channel. 2. Image information of the main area is two-dimensional DC
The image information of the sub-area is coded by T conversion and is 1
The moving image compression encoding method according to claim 1, wherein the encoding is performed by a three-dimensional DCT transform.