JP3525025B2 - Semiconductor memory inspection method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection method and apparatus for a semiconductor memory manufactured as a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor memory manufacturing process, a static DC test and a dynamic function test are generally performed. In the DC test, direct current specification items such as input leakage current and power consumption of the semiconductor memory are tested. Such a DC test is commonly performed even if the type of semiconductor memory changes. On the other hand, in the function test, for the purpose of testing the function of the semiconductor memory, an address decoder test, an interference test between memory cells, and the like are performed using a dedicated test pattern. In order to accurately test the access time etc., highly accurate timing and complicated waveform output function are required. Therefore, a tester, which is a semiconductor memory inspection device, generally needs to include a highly functional pattern generator, a highly accurate timing generator, a highly functional waveform shaper, and the like. As the operating speed of the semiconductor memory to be inspected is increased, the demand for higher functionality and higher accuracy of the tester is further increased, and the price of the tester is increasing.

FIG. 12 shows a schematic electrical configuration of a tester for a general semiconductor memory. The pattern generator 1 is
Address, data and data for control signals
Occurs under microprogram control. The pattern generator 1 includes an arithmetic logic operation unit and a group of registers, which constitute a complicated logic circuit and can operate at high speed. The address generated by the pattern generator 1 becomes a logical address, and the X address scrambler 2 and the Y address are generated.
It is converted into a physical address by the address scrambler 3. In a semiconductor memory, since memory cells are generally arranged in a matrix, it is better to separate the X address and the Y address so as to correspond to the row address and the column address, respectively. It becomes easy to understand.

The waveform shaping circuit 4 shapes the address signal, the data signal and the control signal so as to have a desired waveform. Dynamic RAM (hereinafter "DRAM")
The waveform shaping circuit 4 also has a function of multiplexing and giving an address signal to (for example).
The timing generator 5 applies a pattern generated by the pattern generator 1 to a semiconductor memory to be inspected (hereinafter abbreviated as “DUT”), various timing edges used by the waveform shaping circuit 4, and the like. , A signal is generated that indicates all the timing required for the test. High-speed operation is required to generate timing with high accuracy. The waveform signal shaped by the waveform shaping circuit 4 is applied to the DUT via the pin electronics 6 which is an aggregate of drivers and comparators. The pin electronics 6 has a function of converting a logical value of a signal in the tester to a real level and giving it to the DUT, and at the same time, converting an output from the DUT into a logical value and taking it into the tester.
The comparison / determination circuit 7 performs comparison / determination of the output logical value from the DUT and the expected value data generated by the pattern generator 1 in accordance with the timing designated by the timing generator 5.

FIG. 13 shows the pattern generator 1 shown in FIG.
Here is the simplest example of. The pattern generator 1 includes an instruction memory 10, an X address generator 11, and a Y address.
It comprises an address generator 12, a data generator 13 and a sequence instruction decoder 14. The instruction memory 10 includes a sequence control memory unit 10
S, a control data unit 10C, an X address generator instruction memory unit 10X, a Y address generator instruction memory unit 10Y, and a data generator instruction memory unit 10D. Instructions such as repeats and jumps for repeating pattern generation are stored in the sequence control memory unit 10S as a microprogram. The instruction stored in the sequence control memory unit 10S is sequentially interpreted by the sequence instruction decoder 14 to determine the next instruction memory address.

The X address generator instruction memory unit 10X stores execution instructions for the X address generator 11. The inside of the X address generator 11 includes an instruction decoder 11D, at least two registers 11R1 and 11R2, and an arithmetic logic operation unit 11ALU. The execution instruction is decoded by the instruction decoder 11D in the X address generator 11, the operation according to the instruction is performed, and the address value is output. At the time of calculation, the register 11R1 is the first
In the operator, the register 11R2 also serves as the second operator and the output register, and the operation result by the arithmetic logic operation unit 11ALU between the registers 11R1 and 11R2 is taken into the register 11R2. The relationship between the Y address generator instruction memory unit 10Y and the data generator instruction memory unit 10D, and the Y address generator 12 and the data generator 13 is also the same.
In addition, the Y address generator 12 and the data generator 13
Are instruction decoders 12D and 1D, respectively.
3D and at least two registers 12R1, 12R
2; 13R1 and 13R2, and the arithmetic logic operation unit 12
It consists of ALU and 13 ALU.

Prior art relating to pattern generation for a tester of a semiconductor memory is disclosed in, for example, Japanese Patent Laid-Open No. 60-1316.
7, JP-A-63-187170, JP-A-64 (JP-A-1) -53176 and JP-A-5-281299. In addition, in Japanese Patent Laid-Open No. 6-230077,
Prior art is disclosed that allows DC measurements during pattern generation.

[0008]

The pattern generator of the conventional tester has a fairly complicated structure as shown in FIG. 13 and needs to operate at a high speed, so that it is expensive. Further, JP-A-60-113167 and JP-A-63-1871
70, JP-A-64-53176 and JP-A-5-281.
In the prior art such as 299, a method for easily realizing a highly functional pattern generator has been proposed, but none of them has been able to significantly reduce the price of the entire tester. Japanese Unexamined Patent Application Publication No. 6-230077 is also limited to adding a DC measurement function to a pattern generator similar to the conventional one.

In recent years, non-volatile memories such as flash memories and EEPROMs have been in increasing demand for applications such as mobile information terminals and mobile phones. Since these nonvolatile memories take a long time to write and erase data, they do not require high speed for testing. Does not require very complex signal waveforms. Therefore, using a high-priced, high-performance tester will increase the cost of testing. Further, in the nonvolatile memory, a test for guaranteeing reliability is specially required, and it is necessary to have a function of performing a DC test or the like during the function test. Therefore, in a normal tester, the inspection time becomes very long.

That is, a tester for inspecting a non-volatile memory such as a flash memory does not require a high-speed and highly-functional pattern generator, timing generator, waveform shaper or the like, unlike other types of semiconductor memories. Nevertheless, you will have to use an expensive tester. In addition, the hardware included in a normal tester cannot necessarily efficiently perform a flash memory specific test.

An object of the present invention is to provide a semiconductor memory inspection method and apparatus capable of efficiently inspecting with a significantly smaller amount of hardware than a conventional tester.

[0012]

[0013]

[0014]

[0015]

According to the present invention, first and second addresses and data having a predetermined pattern are set in advance in an address register and a data register, respectively, and the semiconductor memory to be inspected is set. The first address setting and the application of the data having the predetermined pattern are performed from the address register and the data register, respectively, and the second time the address setting and the application of the data having the predetermined pattern are performed from the address register and the data register, respectively. As described above, the semiconductor memory inspection method is characterized in that the time until it is determined whether or not expected data is output is measured while repeating at preset time intervals. According to the invention,
After the first address setting and the data application having the predetermined pattern, the second address setting and the data application having the predetermined pattern are repeatedly performed from the address register and the data register, respectively, from the semiconductor memory to be inspected. The output can be compared, for example, with expected data as an expected value and the time until a match or mismatch can be measured. As a result, even with simple hardware, it is possible to efficiently test the time required to complete the execution of writing or erasing.

Further, according to the present invention, data having an address of the first time, the second time, and the third time and data having a predetermined pattern are set in advance in the address register and the data register, respectively, and the semiconductor memory to be inspected is set to 1 The address setting for the second time and the application of the data having the predetermined pattern are performed from the address register and the data register, respectively, and the second time of the address setting and the application of the data having the predetermined pattern are performed at predetermined time intervals. Is performed from the address register and the data register respectively, and the third time address setting and the application of the data having the predetermined pattern are performed from the address register and the data register, respectively. Whether the output data is output A method of inspecting a semiconductor memory, characterized by measuring the time in. According to the invention, 1
The semiconductor memory to be inspected while repeatedly performing the address setting and the data application having the predetermined pattern for the third time and the data application having the predetermined pattern repeatedly from the address register and the data register, respectively. Can be compared with the expected data as expected values and the time to match or mismatch can be measured. by this,
It is possible to efficiently test the time required from the command input for writing or erasing to the completion of execution with simple hardware.

[0017]

Further, the present invention is an apparatus for inspecting an operation state of a semiconductor memory, wherein three types of address registers in which addresses are set, three types of control registers in which control signals are set, and data are set. Selected by three types of data registers, three types of address registers, control registers and data registers, and register selection means for outputting the setting contents of the selected registers, and selection by the register selection means An address memory that outputs the stored data designated by the input address, and an address selecting unit that selects the output from the register selecting unit and the output from the address memory. , Selected by register selection means The waveform shaping means for performing the waveform shaping based on the output of the control register and generating the control signal, the output from the address selecting means and the waveform selecting means, and the output of the data register selected by the register selecting means are inspected. Output applying means for applying to the semiconductor memory, comparing means for comparing the output from the semiconductor memory with expected data, and to the semiconductor memory,
A time measuring means for measuring the time from the application of the output of the address selecting means from the output applying means to the output of the comparison result indicating the coincidence or non-coincidence of the data from the comparing means, and the register according to the preset timing. An inspection apparatus for a semiconductor memory, comprising: a control unit that controls a selection operation of a selection unit and a control signal generation of a waveform shaping unit. According to the present invention, one type is selected from each of the three types of address register, control register and data register by the register selecting means, and at most three types of address, control signal and data are switched at high speed to the semiconductor memory to be inspected. Can be applied. Simple hardware, 1
It is possible to efficiently perform the write application completion time after repeating the pattern application once or twice, or repeating the pattern application once or twice.

[0019]

FIG. 1 shows a schematic electrical configuration of a semiconductor memory inspection device as an embodiment of the present invention. Three types of X registers 30A, 30B, 30
Address data of n bits is set in the C and Y registers 31A, 31B, 31C. Since the memory cells of a semiconductor memory are generally arranged in a matrix, it is easier to understand the correspondence with the arrangement when the addresses are set separately in rows and columns. The value of n is set larger than the number of bits required as an address of the semiconductor memory to be inspected.
M-bit control signal data and p-bit pattern data are set in the three types of C registers 32A, 32B, 32C and D registers 33A, 33B, 33C, respectively. X registers 30A, 30
B, 30C, Y registers 31A, 31B, 31C, C registers 32A, 32B, 32C and D register 33.
The multiplexers 34A, 34B, 34C, and 34D, which are register selecting means, select the outputs of one type of registers from the outputs of the three types of registers.

The selective outputs of the n-bit X registers 30A, 30B and 30C and the Y registers 31A, 31B and 31C from the multiplexers 34A and 34B are the X scramble file 35A and the Y scramble file 35, respectively.
B respectively. X scramble file 35
A and Y scramble files 35B each have 2
The memory is an ⁿ × n-bit configuration, and address conversion can be performed by setting n-bit address data in a memory cell specified by an n-bit address. Therefore, the X registers 30A, 30B, 30
Data is set as a logical address in the C and Y registers 31A, 31B, 31C, and the X scramble file 3
5A and Y scramble file 35B have data set as physical addresses, the X registers 30A, 30B, 30 can be set in correspondence with the memory cell arrangement, for example.
The logical address specified by the C and Y registers 31A, 31B, 31C can be converted into the physical address to which the DUT is actually connected. The multiplexers 36A and 36B, which are address selecting means, are
Output from A, 34B and X scramble file 35
Outputs from the A and Y scramble files 35B are selected and output as addresses. When converting a physical address and a logical address in the X scramble file 35A and the Y scramble file 35B, either the logical address or the physical address is selected.

Flip-flops 37A, 37B, 37
C and 37D are multiplexers 36A, 36B and 34
In order to align the timings of the X address, Y address, control signal and data from C and 34D, n bits, n bits, m bits and p pits are provided respectively. The timing and level of the output from the flip-flop 37C are further finely adjusted by the waveform shaping circuit 38 so as to obtain a desired waveform. The waveform mode at this time is NRZ (Non Return to Zero) or RZ (Return to Zer) for each of the m bits.
It should be relatively simple such as o). Signal selector 39
, An n-bit X and Y address and an m-bit control signal are input to select the q-bit that needs to be given to the DUT. In other words, n + n +
Arbitrary signals of the m-bit inputs, such as respective lower bits required for the test, are selected and assigned to the test channel. Such a signal selector 39 can be realized by using a multi-input multiplexer or an LSI whose wiring can be freely changed.

The q-bit output from the signal selector 39 and the p-bit output from the flip-flop 37D are given to the DUT from the level fixing circuit 40 via the drivers 41 and 41B, respectively. Level fixing circuit 40
Then, it is possible to fix any output of the q + p-bit outputs to a level where the logical value is either 0 or 1. Signals that do not need to be changed during the test, such as various mode selection signals, can be fixed regardless of the register data, and the load on the program can be reduced. Such a level fixing circuit 40 can be easily realized by a simple hardware that outputs a specific level only for a bit whose level is fixed and outputs an input as it is for other bits. Drivers 41A, 41B
Are provided for q channels and p channels, respectively, and D is set according to whether the input logical value is 0 or 1.
A low level input voltage VIL or a high level input voltage VIH is applied to UT, respectively. Driver 41A is DUT
Is an input-only channel, and is always enabled unless otherwise specified, but it can be disabled in high impedance if necessary. Since the driver 41B serves as an input / output channel for the DUT, input / output control is performed, and when the driver 41B serves as an output channel for the DUT, the driver 41B is disabled.

The output voltage from the DUT is converted into logical data by comparators 42A and 42B provided for p channels, respectively. The high-level output voltage VOH is given to the comparator 42A as a reference voltage, and depending on whether the output voltage from the DUT is higher or lower than the reference voltage,
The logical value 1 or 0 is output as COMH, respectively.
The comparator 42B is supplied with a low level output voltage VOL reference voltage, and outputs a logical value 0 or 1 as COML depending on whether the output voltage from the DUT is lower or higher than the reference voltage. Comparator 42A,
The outputs COMH and COML from 42B are compared with the p-bit data from the flip-flop 37D by the comparison / determination circuit 43 at the timing of STROBE given from the controller 44, and if there is a mismatched comparison result even in one channel, the comparison and determination is made. The logical value of the FAIL signal representing the result is 1. The outputs from the comparators 42A and 42B are
If the DUT output is lower than VOL, COML = 0, COM
If H = 0 and the DUT output is higher than VOH, COM
L = 1 and COMH = 1, and when the DUT output voltage is intermediate, COML = 1 and COMH = 0. The controller 44 sets the data in each register, and the selection signals SEL1 and SEL2 for performing selection by the multiplexers 34A, 34B, 34C and 34D; 36A and 36B, and the flip-flops 37A, 37B, 37C and 37D latch the data. Timing signal T indicating the timing for
IM and clock signal C given to the waveform shaping circuit 38
LOCK etc. also occur.

FIG. 2 shows a configuration example of the comparison / determination circuit 43 of FIG. The inverter 50 inverts the logic of the input COMH. The inverted COMH has a DUT output voltage of VO.
The logical value is 0 or 1 depending on whether it is higher or lower than H.
The multiplexer (hereinafter, also abbreviated as “MPX”) 51 uses the data from the flip-flop 37D in FIG. 1 as expected value data, and performs COML or inversion depending on whether the logical value is 0 or 1. Select and output COMH. Therefore, if the expected value data and the logical value of the DUT output voltage match, the logical value 0 is output, and if they do not match, the logical value 1 is output. A flip-flop (hereinafter sometimes abbreviated as “FF”) 52 is set to 1 when the comparison result is used for determination, and is set to 0 when it is not used. The output of FF52 is MPX51
Is input to the AND circuit 53, and the logical product is given to the FF 54 as an output. FF54 is STROB
At the timing of E, the output of the AND circuit 53 is latched. The comparison circuit 55 including the inverter 50, the MPX 51, the FF 52, the AND circuit 53, and the FF 54 is provided for p bits, and the output from each comparison circuit 55 is given to the OR circuit 56 having the input for p bits. Therefore, the OR circuit 56 outputs a FAIL signal having a logical value of 1 as a comparison determination result if there is a mismatch between the expected value data and the STROBE timing among the p-channel output voltages from the DUT.

FIG. 3 shows an example of the configuration of the controller 44 shown in FIG. From the t0 generator 60, the flip-flop 37
The TIM signal given to A, 37B, 37C, and 37D is t0.
It is generated in the cycle of. The TIM signal is a pulse signal indicating the beginning and end of the test cycle. t1 generator 61
The t2 generator 62 generates a clock signal CLOCK which is generated with a delay of t1 and t2 from the TIM signal and which is a timing to be given to the waveform shaping circuit 38. From the t3 generator 63, the comparison / determination circuit 43 performs STROBE for comparison / determination between the expected value data and the DUT output.
Generate timing. Comparison judgment is made with inspection device and DUT
Since there is a delay only in the propagation delay time required for the signal to make a round trip between and, the delay circuit 64 further delays it as hardware and outputs the STROBE signal at an appropriate timing. The time definition counter 65 defines the time between cycles when performing a test in a plurality of cycles. The time measuring counter 66 is used for measuring time. Control circuit 67
Is a t0 generator 60, a t1 generator 61, a t2 generator 6
2, t3 generator 63, delay circuit 64, time regulation counter 65 and time measurement counter 66 are real-time controlled to generate selection signals SEL1 and SEL2, and a FAIL signal indicating that the comparison and determination results do not match is input. It The CPU 68 sets and controls data for all hardware and executes a test on the DUT according to a preset program.

4 and 5 show an example of the test mode performed by the inspection apparatus of FIG. This test mode is referred to as a normal mode by repeating a one-cycle function test at high speed. FIG. 4 shows the timing inside the inspection device, and FIG. 5 shows the output waveform of the inspection device. The START signal of FIG. 4 corresponds to the CPU 68 of FIG.
Is given as an operation start command to the control circuit 67. The control circuit 67 starts its operation when the START signal rises to the high level, and outputs from the t0 generator 60 the timing signal T of the cycle t0 indicating the beginning and end of the test cycle.
Generate IM. The selection signals SEL1 and SEL2 are kept at constant values, and only the data set in the X register 30A and the Y register 31A are used as the X address and the Y address. If specified, the control signal uses t1 or t2 in the CLOCK signal to perform waveform shaping. FIG. 4 shows a case where the waveform is shaped as RZ. Since each signal is applied to the DUT through the signal selector 39, the level fixing circuit 40, and the drivers 41A and 41B, it takes a certain propagation delay time. In FIG. 4, the period actually applied to the DUT is shown by hatching. In the normal mode, when the test of only the application cycle for the DUT is performed, the START signal is reset and the processing is ended.

In the normal mode, as shown in FIG.
The address signal and the like are output only during the designated period t0, and the control signal and the strobe signal STROBE can be generated within that period. When the test of one cycle is completed, the next address is set to the controller 44.
It is set by the internal CPU 68 and the second cycle test is performed. Since the test of the second cycle is started after the end of the first cycle, a setting operation is required between the first cycle and the second cycle, and there is an unnecessary period in the DUT test itself. become. However, this time is short if the high-speed controller 44 is used, and in many non-volatile memories, it is a time that does not cause a problem as compared with the write and read times.

When the comparison judgment is performed in the normal mode, since a signal propagation delay time from the DUT to the comparison judgment circuit 43 is required, it is necessary to further delay it as shown by the hatching in FIG. 4 as a comparison judgment cycle. . In this cycle, a comparison determination is made by the STROBE signal, and if they do not match, the FAIL signal is output as a logical value 1. In this example, the STROBE signal is well ahead of the time when the START signal falls to the low level, so there is no problem, but when it is later in the cycle, the completion processing is performed by the pulse indicating the end of the cycle of the TIM signal. However, there is a possibility that the comparison determination may not be completed. In such a case, the circuit is configured so that the START signal is reset after the STROBE signal is generated. After generating the START signal, the CPU 68 may wait for the START signal to be reset, confirm the reset, and then shift to the next cycle.

6 and 7 show another example of the test mode performed by the inspection apparatus of FIG. In this test mode, after completing the first cycle test, wait for the specified time and then perform the second cycle test.
Repeat the 2-cycle function test at high speed,
We will call it double mode. FIG. 6 shows the internal timing of the inspection device, and FIG. 7 shows the output waveform of the inspection device.

As shown in FIG. 6, between the cycle 1 of the first cycle and the cycle 2 of the second cycle, a time wait defined by the time definition counter 65 of FIG. 3 is performed. In order to make the data to be applied to the DUT different in the application cycle 1 and the application cycle 2 shown by hatching, two types of X registers 30A and 30B and Y registers 31A and 3 are used.
1B, C register 32A, 32B and D register 33
A and 33B are switched by the selection signal SEL1. ST
The ART signal is reset after the end of cycle 2.

As shown in FIG. 7, after outputting to the DUT for writing in cycle 1, the DUT is again written in cycle 2.
Write to. When the time from writing to rewriting at this time is meaningful as a test of an operation mode that requires command input, for example, an effective test can be performed.

FIG. 8 and FIG. 9 show still another example of the test mode performed by the inspection device of FIG. In this test mode, when the test of the first cycle is completed, 2
The test of the cycle is repeated, and when the judgment result of the expected value and the output of the DUT becomes FAIL or PASS which is the opposite of FAIL, the test is completed and the time measurement mode is called. FIG. 8 shows the timing inside the inspection device, and FIG. 9 shows the output waveform of the inspection device.

As shown in FIG. 8, when the cycle 1 of the first cycle is completed, the cycle 2 of the second cycle is repeatedly executed, and the comparison and judgment result between the expected value and the output of the DUT is F.
The time until the PASS becomes AIL or vice versa is measured by the time measuring counter 66 of FIG. D in the application cycle 1 and the time measurement cycle 2 shown by hatching
In order to make the data applied to the UT different, two types of X registers 30A, 30C and Y registers 31A, 31C, C
Registers 32A and 32C and D registers 33A and 33
C is switched by the selection signal SEL1. The START signal is reset at the end of cycle 2. In cycle 1 and cycle 2, the cycle periods are t0 and t0 '.
The data set in the t0 generator 60 can also be switched so that it can be switched to and. The same applies to other timing generators.

As shown in FIG. 9, after the data is output to the DUT in the cycle 1 for writing, the comparison judgment in the cycle 2 is repeated. Outputting desired data from the DUT is equivalent to measuring the result of comparison with the expected value, that is, the time until the signal indicating FAIL / PASS changes corresponding to 1/0 of the logical value. . This time measurement mode is effective as a test of the completion time of writing or erasing, for example.

FIG. 10 shows an output waveform in a mode in which after the outputs of cycle 1 and cycle 2 in the double mode, desired data is output from the DUT and the time until it matches or does not match the expected value data is measured. Indicates. Such a mode is called a double time measuring mode. double·
In the time measurement mode, the third cycle, Cycle 3, is a time measurement cycle and is repeated.

Three types of X registers 30A, 30B, 30
Among the C, one X register 30A has address data in the normal mode, or cycle 1 in the double mode, the time measurement mode, and the double / time measurement mode.
Set the address data of. Address data of cycle 2 in the double mode and the double / time measuring mode is set in the other X register 30B. Address data of cycle 2 in the time measurement mode and cycle 3 in the double / time measurement mode are set in the other X register 30C. Data setting is similarly performed for the other registers. If the types of modes are limited, it is possible to reduce the types of registers and further simplify the hardware.

In the inspection apparatus shown in FIG. 1, the tester can be configured with simple hardware as compared with the conventional tester, and the DUT can be tested in various modes. Although such hardware can basically perform only one cycle of function test, the CPU
If 68 is controlled at high speed and continuously, the same functional test as the conventional tester can be executed without a large loss of time. Although processing time of software is included between cycles, this is about several hundred ns, which is sufficiently smaller than the time required for writing and erasing the nonvolatile memory and can be ignored.

FIG. 11 shows a simplified description example of a test program which is software for controlling the inspection apparatus of FIG. Software for controlling such hardware is generally called a test statement. In this embodiment, the execution is performed in units of normal mode, double mode, time measurement mode, and double / time measurement mode. FIG. 11A shows a case where the same data DATA is written in all the memory areas in the normal mode. FIG. 11B shows a case where data is further read. “Set_data ()” indicated by reference numeral 70 is the D register 3
It is a test statement that sets a value in 3A, 33B, and 33C. “Set_addr ()” indicated by reference numeral 71 is a test statement for setting values in the X register 30A and the Y register 31A. Further, "run_pg ()" indicated by reference numeral 72 is a test statement that executes the function test only once according to the designated mode. Here, NORMAL indicating the normal mode is used as the first argument parameter 73. Two
If the second argument parameter 74 is WR, no comparison judgment is made, but if it is RD, comparison judgment is made. Reference mark 7
“Set_fail ()” indicated by 5 is a test statement indicating the processing when there is a mismatch.

The test program shown in FIG. 11 can be described in C format in a very easy-to-understand manner. In addition,
In order to simplify and simplify the explanation, the description of test statements such as timing setting is omitted and only the change of address is shown. Furthermore, in "run_pg ()", 1
Since only the function test of the cycle is executed, it is possible to flexibly set the inspection process such as changing the setting of other conditions or executing the DC measurement after finishing the application of one pattern. In the tester including the conventional pattern generator, the voltage condition cannot be changed or the DC measurement cannot be performed during the pattern generation. Although a tester in which some of these functions are incorporated as a function of the pattern generator is also considered, the price as a tester rises, and the flexibility of the function is far greater when the present invention is applied. Is excellent.

[0040]

As described above, according to the present invention, the address register and the data register are set once for the address and the data having the predetermined pattern, respectively, and the semiconductor memory to be inspected is provided with the address. Since the address setting and the data application from the register and the data register only have to be repeated, the hardware configuration can be made extremely simple, and the inspection can be efficiently performed by performing the repetition at high speed.

[0041]

[0042]

Further, the addresses and data required for the test are set in the address register and the data register, respectively, so that even with simple hardware, it is possible to efficiently test the time required until the completion of writing and erasing. .

Further, according to the present invention, the address and data required for the test are set in the address register and the data register respectively, and the time required from the input of the command for writing or erasing to the completion of execution can be determined by simple hardware. Can be tested efficiently.

[0045]

Further, according to the present invention, one type is selected from each of the three types of address registers, control registers and data registers, and at most three types of addresses, control signals and data are switched at high speed to the semiconductor memory to be inspected. Therefore, the inspection can be efficiently performed with simple hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of an inspection apparatus according to an embodiment of the present invention.

FIG. 2 is a logical block diagram showing an example of a comparison / determination circuit 43 in FIG.

FIG. 3 is a logical block diagram showing an example of a controller 44 of FIG.

4 is a time chart showing the operation of the inspection device of FIG. 1 in a normal mode.

5 is an output waveform diagram of a signal given to the DUT in the normal mode from the inspection device of FIG.

FIG. 6 is a time chart showing the operation of the inspection device of FIG. 1 in the double mode.

7 is an output waveform diagram of a signal given to the DUT in a double mode from the inspection device of FIG.

8 is a time chart showing the operation of the inspection apparatus of FIG. 1 in a time measurement mode.

9 is an output waveform diagram of a signal given to the DUT in the time measurement mode from the inspection device of FIG.

10 is an output waveform diagram of a signal given to the DUT in the double / time measurement mode from the inspection apparatus of FIG.

11 is a list diagram showing an example of a test program of the inspection apparatus of FIG.

FIG. 12 is a block diagram showing a schematic electrical configuration of a conventional semiconductor memory tester.

13 is a logical block diagram showing an example of the pattern generator 1 of FIG.

[Explanation of symbols]

30A, 30B, 30C X register 31A, 31B, 31C Y register 32A, 32B, 32C C register 33A, 33B, 33C D register 34A, 34B, 34C, 34D, 36A, 36B, 5
1 multiplexer 35A X scramble file 35B Y scramble file 38 Waveform shaping circuit 39 Signal selector 40 Level fixing circuit 43 Comparison determination circuit 44 Controller 55 Comparison circuit 56 OR circuit 60 t0 generator 61 t1 generator 62 t2 generator 63 t3 generator 64 Delay circuit 65 Time regulation counter 66 Time measurement counter 67 Control circuit 68 CPU

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-7-73700 (JP, A) JP-A-60-113167 (JP, A) JP-A-63-187170 (JP, A) JP-A-64- 53176 (JP, A) JP-A-5-281299 (JP, A) JP-A-6-230077 (JP, A) JP-A-6-167546 (JP, A) JP-A-59-45699 (JP, A) JP-A-1-120000 (JP, A) JP-A-4-329382 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 29/00

Claims (3)

(57) [Claims] 1. A first and second address and data having a predetermined pattern are set in advance in an address register and a data register respectively, and the first address setting and the predetermined data are set in a semiconductor memory to be inspected. It is preset so that the application of the data having the pattern is performed from the address register and the data register respectively, and the second address setting and the application of the data having the predetermined pattern are performed from the address register and the data register respectively. A method for inspecting a semiconductor memory, which is characterized by measuring the time until it is determined whether or not expected data is output while repeating at time intervals. 2. A first, second, and third address and data having a predetermined pattern are set in advance in the address register and the data register, respectively, and the first address is set in the semiconductor memory to be inspected. The setting and the application of the data having the predetermined pattern are performed from the address register and the data register respectively, and the second time of the address setting and the application of the data having the predetermined pattern are performed at predetermined time intervals. The expected data is repeated from the register and the data register, and the third time address setting and the application of the data having the predetermined pattern are repeated at preset time intervals so as to be performed from the address register and the data register, respectively. The time until it is determined whether or not is output A method of inspecting a semiconductor memory, characterized by measuring. 3. A device for inspecting an operation state of a semiconductor memory, comprising: three types of address registers to which addresses are set, three types of control registers to which control signals are set, and three types of data to be set. Data register, three kinds of address registers, one register from each of the control register and the data register, and a register selecting means for outputting the setting contents of the selected register, and an address selected by the register selecting means. The output of the register is input as an address, the address memory for outputting the storage data specified by the input address, the address selecting means for selecting the output from the register selecting means, and the output from the address memory, and the register selecting The controller selected by means The waveform shaping means for performing the waveform shaping based on the output of the register to generate the control signal, the output from the address selecting means and the waveform shaping means, and the output of the data register selected by the register selecting means are subject to inspection. Output applying means for applying to the semiconductor memory, comparing means for comparing the output from the semiconductor memory with expected data, and applying the output of the address selecting means from the output applying means to the semiconductor memory, and then the comparing means. Time measuring means for measuring the time until the comparison result indicating the coincidence or non-coincidence of data is output, and control for controlling the selecting operation of the register selecting means and the control signal generation of the waveform shaping means according to the preset timing. An inspection device for a semiconductor memory, comprising: