JP3503745B2 - Demodulator with quasi-synchronous detection - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quasi-synchronous detection system demodulator, and more particularly to a quasi-synchronous detection system demodulator for performing parallel processing on a frequency-converted reception signal after serial-parallel conversion.

[0002]

2. Description of the Related Art A conventional quasi-synchronous detection demodulator is
As shown in FIG. 7, the local oscillator 3 having substantially the same frequency as the carrier wave of the modulation signal input to the IF input terminal of the demodulator, and the output signal of the local oscillator 3 are branched into two, and one phase is π / 2. A π / 2 phase shifter 4 for shifting, multipliers 1 and 2 for multiplying the outputs of the local oscillator 3 and the π / 2 phase shifter 4 by the modulated wave input from the IF input terminal,
A / D converters 5 and 6 for converting the analog signal outputs of the multipliers 1 and 2 into digital signals, and a serial / parallel conversion circuit that enables the subsequent processing to be performed at low speed because the output signals of the A / D converters are high speed. 7, 8 and Ich and Q
Automatic amplitude correction circuit (AGC) 9 that corrects the amplitude difference between channels
And a carrier synchronization circuit 10 for correcting the deviation between the carrier frequency and the frequency of the local oscillator, and I (In-phase) c
A parallel-serial conversion circuit 11 for converting parallel signals of h and Q (Quadrature) ch into serial signals,
CLK phase detection circuit 12 for detecting the phase for clock synchronization, and LPF for integrating and smoothing the phase detection signal
13, a D / A converter 14 for converting a smoothed multi-bit digital signal into an analog control signal, a VCXO 15 for controlling a clock oscillation frequency by the analog control signal and outputting a clock synchronized with a transmission clock,
A reset circuit 40 that resets the serial-parallel conversion circuits 7 and 8 is used.

The reset circuit 40, as shown in FIG. 8, is a power supply monitoring circuit 3 for monitoring that the power supply is normally started.
3 is provided.

The operation of the divided clock reset circuit will be described with reference to FIGS. Conventionally, since the output signal section of the A / D converters 5 and 6 of the demodulator by the quasi-synchronous detection is a high-speed / multi-bit signal string, there is no device that can be used at low cost. There was something to do. However, when there are a plurality of frequency dividing circuits, there is uncertainty in the phase between the frequency dividing circuits, and therefore there is a circuit for matching the frequency dividing phases between the frequency dividing circuits. Generally, if the frequency division phase is adjusted only when the power is turned on, the phase will not be shifted after that. Therefore, conventionally, the power supply monitoring circuit 33 releases the reset control and starts the frequency division of the clock after the power of the module is turned on and becomes stable. I was letting it. In the conventional systems, it was not assumed that the frequency division phases would be shifted after the frequency division phases of the serial-parallel conversion circuits 7 and 8 were made to coincide when the power was turned on.

[0005]

However, when a control signal having a frequency component equal to the spurious component peculiar to the oscillator is input to the oscillation frequency control terminal of the VCXO 15, the VCXO stops oscillation for a short time or skips the oscillation frequency. May occur. At this time, there is a problem that the frequency division timing between the serial-parallel conversion circuits 7 and 8 is deviated and correct demodulation cannot be performed unless the power is turned on again and the frequency division circuit 24 is reset.

The present invention has been made in view of the above problems, and even when the clock generated by the VCXO is interrupted or the frequency is skipped during operation, the difference between the plurality of serial-parallel conversion circuits is reduced. It is an object of the present invention to provide a demodulator by a quasi-coherent detection method that can immediately correct the deviation of the peripheral phase.

[0007]

According to the present invention, the I component and the Q component of the received signal are serial / parallel converted by the serial / parallel converting means for the I component and the serial / parallel converting means for the Q component, respectively. In the demodulator by the quasi-synchronous detection method for converting and processing, the serial / parallel conversion means for the I component performs serial / parallel conversion.
Serial / Phase for parallel conversion and the Q component
Detection means for detecting that the phases of the serial / parallel conversion performed by the parallel conversion means do not match, and serial / parallel conversion performed by the serial / parallel conversion means for the I component
Serial / Phase for parallel conversion and the Q component
If the detection means detects that the phases of the serial / parallel conversion performed by the parallel conversion means do not match, the phase of the serial / parallel conversion performed by the serial / parallel conversion means for the I component and the Q component. And a reset means for simultaneously resetting the phase of the serial / parallel conversion performed by the serial / parallel conversion means for the quasi-synchronous detection method.

In the above-mentioned quasi-synchronous detection system demodulator, the reset means intermittently generates an intermittent mask signal which is intermittently at an enable level, and serial / parallel conversion means for the I component. Masks the output signal of the detection means by the intermittent mask signal, which indicates whether or not the phase of the serial / parallel conversion performed by and the phase of the serial / parallel conversion performed by the serial / parallel conversion means for the Q component match. The serial / parallel conversion phase performed by the serial / parallel conversion means for the I component and the serial / parallel conversion phase performed by the serial / parallel conversion means for the Q component do not match. When the output of the detection means indicates that there is, and the intermittent mask signal At the enable level, the phase of serial / parallel conversion performed by the serial / parallel conversion unit for the I component and the phase of serial / parallel conversion performed by the serial / parallel conversion unit for the Q component are simultaneously reset. Good.

In the demodulator by the quasi-coherent detection method, the reset means is a phase of serial / parallel conversion performed by the serial / parallel conversion means for the I component and a serial / parallel conversion means for the Q component. When the logic level of the output signal of the detecting means changes from the logic level indicating coincidence to the logic level indicating non-coincidence, which indicates whether or not the phases of the serial / parallel conversion performed by Whether or not the phase of serial / parallel conversion performed by the serial / parallel conversion means for the I component and the phase of serial / parallel conversion performed by the serial / parallel conversion means for the Q component are coincident with each other. The logical level of the output signal of the detection means indicating that When converted, the phase of serial / parallel conversion performed by the serial / parallel conversion unit for the I component and the phase of serial / parallel conversion performed by the serial / parallel conversion unit for the Q component may be simultaneously reset. .

In the above-mentioned quasi-synchronous detection system demodulator, the serial / parallel conversion means for the I component and the serial / parallel conversion means for the Q component are:
A first flip-flop circuit that clock-synchronizes an input signal, a second flip-flop circuit that delays the output of the first flip-flop circuit by one clock, a frequency dividing circuit that divides the clock, and An output of the first flip-flop circuit and an output of the second flip-flop circuit, and third and fourth flip-flops for synchronizing the output of the second flip-flop circuit with the divided clock, and the output of the divider circuit is reset. By doing so, the serial / parallel conversion means may be reset.

The demodulator by the quasi-synchronous detection method described above comprises first multiplication means for obtaining the I component by multiplying the received signal by a local oscillation signal having a frequency close to the carrier of the received signal, and the received signal by the local oscillator. First multiplication means for obtaining the Q component by multiplying the oscillation signal by a signal having the same frequency and a phase difference of π / 2; and a first A / D conversion means for A / D converting the I component. Second A / D conversion means for A / D converting the Q component, wherein the serial / parallel conversion means for the I component performs serial / parallel conversion of the A / D converted I component. The serial / parallel conversion means for the Q component may serial / parallel convert the A / D converted Q component.

The quasi-synchronous detection demodulator corrects the difference between the output level of the serial / parallel conversion means for the I component and the output level of the serial / parallel conversion means for the Q component. Automatic amplitude correction means,
The carrier synchronization means for inputting the output of the automatic amplitude correction means and outputting the I component and the Q component in which the deviation between the frequency of the carrier and the frequency of the local oscillation signal is corrected, and the output of the carrier synchronization means. Parallel / serial conversion means for performing parallel / serial conversion, clock phase detection means for detecting the phase of the clock from the output of the carrier wave synchronization means, and a low pass filter for integrating the phase detection signal output by the clock phase detection means. A D / A converter for D / A converting the output of the low pass filter, and a voltage controlled oscillator for generating an oscillation signal whose frequency is controlled by the output of the D / A converter. First
And a second A / D conversion means, the parallel / serial conversion means, the clock phase detection means, the low pass filter, and the D / A conversion means clock the oscillation signal output from the voltage controlled oscillation means. You may use as.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIG. 1, a demodulator according to the quasi-coherent detection method of the present invention is a VCXO 15 for a clock signal.
When the waveform of the clock output by is broken due to frequency jump or oscillation at another frequency, Ich / Q
Even if the frequency-divided clock timing of each of the serial-parallel conversion circuits 7 and 8 for ch is deviated, the phase is constantly monitored.
Since 4 is reset and frequency division timing is adjusted again, good demodulation control can always be performed.

The demodulator according to the quasi-coherent detection method of the present invention is
As shown in FIG. 1, the local oscillator 3 having substantially the same frequency as the carrier wave of the modulation signal input to the IF input terminal of the demodulator, and the output signal of the local oscillator 3 are branched into two, and the phase of one of them is π / 2. A π / 2 phase shifter 4 for shifting, multipliers 1 and 2 for multiplying the outputs of the local oscillator 3 and the π / 2 phase shifter 4 by the modulated wave input from the IF input terminal,
A / D converters 5 and 6 for converting the analog signal outputs of the multipliers 1 and 2 into digital signals, and a serial / parallel conversion circuit that enables the subsequent processing to be performed at low speed because the output signals of the A / D converters are high speed. 7, 8 and Ich and Q
Automatic amplitude correction circuit (AGC) 9 that corrects the amplitude difference between channels
And a carrier synchronization circuit 10 for correcting the deviation between the carrier frequency and the frequency of the local oscillator, and Ich and Qch.
A parallel-serial conversion circuit 11 for converting each parallel signal into a serial signal, a CLK phase detection circuit 12 for detecting a phase for clock synchronization, and an integration circuit (LPF) 13 for integrating and smoothing the phase detection signal. , A D / A converter 14 for converting a smoothed multi-bit digital signal into an analog control signal, a VCXO 15 for controlling a clock oscillation frequency by the analog control signal and outputting a clock synchronized with a transmission clock, and each serial / parallel conversion Reset circuit 1 for resetting circuits 7 and 8
It is composed of 6.

As shown in FIG. 2, the serial-parallel conversion circuits 7 and 8 include the latch circuits 21a and 21b and the latch circuit 2.
1b of clock signal inverting circuit 23, clock frequency dividing circuit 24, and parallel output F / F circuits 22a and 22b.

The reset circuit 16, as shown in FIG.
The phase comparison circuit 31 that compares the phases of the ch frequency-divided CLK and the Q-channel frequency-divided CLK to determine whether they match / mismatch, the intermittent reset circuit 32, the logical product circuit 34, and that the power supply of the module is normally activated. A power supply monitoring circuit 33 for monitoring,
It is composed of a logical product circuit 35.

In the demodulator of the quasi-coherent detection method according to the present invention, the modulation signal input as the IF signal is QPSK,
A multilevel quadrature modulation signal such as QAM is used. Also, in the following description, regarding each orthogonal component (channel),
The description will be given using general notations Ich and Qch.

In FIG. 1, the local oscillator 3 is an oscillator having substantially the same frequency as the IF input signal. The output signal of the local oscillator 3 is branched into two and one signal is converted into a π / 2 phase by a π / 2 phase shifter 4. Then, each of them is multiplied by the IF input signal to obtain Ich and Qch signal components. These are converted into a digital signal string of several bits by the A / D converters 5 and 6 and Ich1,
It is output as Qch1. In the case of the quasi-coherent detection method that generally uses the oversampling method, A /
Since the output signals of the D converters 5 and 6 are extremely high speed, parallel processing is performed by sampling with a divided clock in order to enable the subsequent processing to be performed at low speed. In the present invention, the serial / parallel conversion circuits 7 and 8 divide the frequency by two to perform parallel processing. This frequency division phase is controlled by the reset circuit 16. AGC7 is Ic
h2 and Ich2 ′, Qch2 and Qch2 ′ are input, and control is performed so that the amplitude of Ich2 matches the amplitude of Qch2. Since the demodulator according to the present invention performs quasi-synchronous detection, Ich1 and Qch1 are not the perfect baseband signals obtained by correctly demodulating the signals output by the transmitter, but the frequency difference between the carrier frequency of the IF signal and the local oscillator 3. And the phase difference is included. Carrier wave synchronization circuit 1
At 0, the frequency difference and the phase difference are removed and the carrier wave of the received demodulated signal is synchronized. The parallel-serial conversion circuit 11 converts Ich and Qch converted into parallel signals for low-speed calculation.
Each parallel digital signal is arithmetically processed and converted into a serial signal. The CLK phase detection circuit 12 detects the phase from the received and demodulated baseband signal in order to reproduce the clock signal synchronized with the transmission clock frequency. The phase detection signal is sampled every clock and
It is integrated / smoothed by PF13. D / A converter 14
Then, the smoothed multi-bit digital control signal is converted into an analog control signal. The oscillation frequency of the VCXO 15 is controlled by an analog control signal and outputs a clock synchronized with the transmission clock.

Referring to FIG. 2, in the serial / parallel conversion circuits 7 and 8, the F / F circuit 21a clocks an I signal sequence or a Q signal sequence of several bit widths (bit widths of the A / D converters 5 and 6). Synchronize with CLK. F / F circuit 2
1b delays the output of the F / F circuit 21a by one clock. Therefore, compared with the I signal sequence or the Q signal sequence supplied to the F / F circuit 22a, the I signal supplied to the F / F circuit 22b is
The signal train or the Q signal train is delayed by one clock. The clock divider circuit 24 divides the clock CLK into halves. Further, the clock frequency divider circuit 24 has a reset signal of H level.
When it becomes IGH, the output is reset. The F / F circuit 22a and the FF circuit 22b synchronize the input I signal sequence or Q signal sequence with the divided clock output from the clock divider circuit 24. Therefore, the F / F circuit 22a and F
From the F circuit 22b, two series of I signal sequences or Q signal sequences that are updated once every two clocks are output.

In FIG. 3, the operation of the reset circuit 16 when the power supply of the module is normally started will be described. The phase comparison circuit 31 receives the clock signals divided by the serial-parallel conversion circuits 7 and 8 as inputs, compares the phases, and determines whether the phases match or mismatch.
First, when the divided clock phases between Ich / Qch match, the logic level of the phase match (in this embodiment, LO
The phase mismatch signal of W) is output. The phase mismatch signal is
The intermittent mask signal output from the intermittent mask signal generation circuit 32 is ANDed with the AND gate 34. When the logic level of the phase mismatch signal is the logic level of the phase match, whether the logic level of the intermittent mask signal is HIGH or LOW, the logic of the temporary reset signal which is the output signal of the AND gate 34 is set. The level is a logical level (LOW in this embodiment) that does not cause a temporary reset. Therefore, in this case, the logic level of the reset signal output from the OR gate 35 is a level at which reset is not performed, except immediately after the power is turned on.

The power supply monitoring circuit 33 releases the reset signal with a delay of a certain time after each set voltage is normally started after the power supply of the device is turned on. That is, the power supply monitoring circuit 33 determines that the logic level is the power-on reset level (HIGH in the present embodiment) from which the power-on reset is performed after a certain time has elapsed after each set voltage is normally activated after the power-on of the device. A signal that changes to (LOW in this embodiment) is output. Therefore, after the power supply becomes stable, the power supply monitoring circuit 33
Since the level of the output signal of LOW is LOW, as long as the level of the output signal of the AND gate 34 is LOW, the OR gate 35 outputs a reset signal of a logic level that does not reset, and stable frequency division is performed. The operation continues.

Next, the operation in the case where the divided clock phases between Ich / Qch do not match will be described with reference to FIG. The VCXO 15, which is a clock source, may jump in frequency or start oscillating at another frequency when a specific frequency component as a control signal is input at a level higher than the reference level. At this time, the clock waveform may be instantaneously collapsed, and the frequency division phase may shift between channels due to the influence of individual differences in device characteristics between Ich / Qch or delay time differences due to pattern routing on the printed board.
If the frequency division phase between Ich / Qch does not match,
The logic level of the phase mismatch signal output from the phase comparison circuit 31 indicates the phase mismatch (in this embodiment, HI
GH). When the clock frequency dividing circuit 24 is directly reset by the phase mismatch signal, the clock frequency dividing circuit 24 is always in the reset state and cannot be recovered. Therefore, it is necessary to forcibly cancel the reset state. As shown in FIG. 4, the intermittent mask signal generation circuit 32 outputs an intermittent mask signal in which an enable level (HIGH in this embodiment) and a disable level (LOW in this embodiment) are alternately repeated at predetermined intervals. For example, the period of the intermittent mask signal is several microseconds, and each time the intermittent mask signal is at the enable level is several nanoseconds (1 clock time).
Is. Therefore, as shown in FIG. 4, even if the time during which the phase mismatch signal is at the phase mismatch level is longer than the period of the intermittent mask signal and is long, the logical level of the temporary reset signal is the reset level (in the present embodiment, HIG
The time of H) is limited to the time when the logic level of the intermittent mask signal becomes the enable level. Therefore, it is possible to prevent the clock divider circuit 24 from being continuously reset. Assuming that the power supply is normally activated, the logic level of the power-on reset signal output by the power supply monitoring circuit 33 is a level at which power-on reset is not performed (LOW in this embodiment), and therefore the logic level of the temporary reset signal. Becomes the logic level of the reset signal output from the OR gate 35. Each clock divider circuit 24 reset by the reset signal starts the dividing operation at the same time when the reset is released, and the I / Q channels start operating at the same timing. As a result, in the phase comparison result in the phase comparison circuit 31, since the phases match, the level of the reset signal output from the reset circuit 16 does not reach the level for resetting again (HIGH in the present embodiment), and the phase shift occurs. Operation continues in the restored state.

Even if the configuration of the reset circuit 16 is as shown in FIG. 5, the same effect as in the case of the configuration of the reset circuit 16 as shown in FIG. 3 can be obtained.

The reset circuit shown in FIG. 5 includes a rising edge detection circuit 36 instead of the intermittent mask signal generation circuit 32 and the AND gate 34, but other parts are the same as the reset circuit 16 shown in FIG.

Referring to FIG. 6 which shows the operation when the frequency division phase mismatch of the clock frequency divider circuit 24 of the I channel and Q channel of the reset circuit 16 shown in FIG. 5 occurs, the logic level of the phase mismatch signal is phase matched. From the logic level indicating the phase mismatch to the logic level indicating the phase mismatch, and the logic level is HIG between the first clock and the next clock.
The rise detection circuit 36 generates a temporary reset signal that becomes H. Another operation of the reset circuit 16 shown in FIG.
The reset circuit 16 is the same as the reset circuit 16 shown in FIG.

[0026]

As described above, according to the present invention,
In multi-level quadrature modulation such as QPSK or QAM, when a specific frequency component as a control signal is input to the VCXO 15 as a clock source at a level higher than the reference level, the VCX
When O jumps in frequency or oscillates at another frequency and the waveform is broken, the divided clock timings of the serial-parallel conversion circuits 7 and 8 between Ich and Qch may shift. Until now, it was not assumed that the division timing would be shifted after the division timings of the serial-parallel conversion circuits 7 and 8 were made to match when the power of the device was turned on. There wasn't. In the demodulator according to the quasi-synchronous detection method of the present invention, the phases of the outputs CLK of the serial / parallel conversion circuits 7 and 8 are compared, and when the phases are deviated, the clock frequency dividing circuit 24 of the serial / parallel conversion circuits 7 and 8 is used. By resetting, it became possible to automatically restore the division timing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a demodulator by a quasi-coherent detection method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of the serial-parallel conversion circuit shown in FIG. 1 according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a reset circuit shown in FIG. 1 according to an embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the reset circuit shown in FIG.

FIG. 5 is a block diagram showing another configuration example of the reset circuit shown in FIG. 1 according to the embodiment of the present invention.

6 is a timing chart for explaining the operation of the reset circuit shown in FIG.

FIG. 7 is a block diagram showing a configuration of a demodulator by a quasi-coherent detection method according to a conventional example.

8 is a block diagram showing a configuration of a reset circuit shown in FIG. 7 according to a conventional example.

[Explanation of symbols]

1, 2 multiplier 3 Local oscillator 4 π / 2 phase shifter 5, 6 A / D converter 7, 8 Serial-parallel conversion circuit 9 AGC (Automatic gain adjustment circuit) 10 Carrier synchronization circuit 11 Parallel-serial conversion circuit 12-clock phase detection circuit 13 LPF (low pass filter) 14 D / A converter 15 VCXO (voltage controlled crystal oscillator)

Claims (6)

(57) [Claims] 1. An I component and a Q component of a received signal are respectively I
A demodulator by a quasi-synchronous detection method, which performs serial / parallel conversion by serial / parallel conversion means for a component and serial / parallel conversion means for a Q component, the serial / parallel conversion means for the I component Detecting means for detecting a mismatch between the phase of the serial / parallel conversion performed by the serial signal and the phase of the serial / parallel conversion performed by the serial / parallel conversion means for the Q component, and the serial / parallel conversion for the I component. If it is detected by the detection means that the phase of the serial / parallel conversion performed by the means and the phase of the serial / parallel conversion performed by the serial / parallel conversion means for the Q component do not match, the Of the serial / parallel conversion performed by the serial / parallel conversion means of Demodulator according to quasi-synchronous detection method characterized by comprising a reset means for resetting simultaneously the phase of the serial / parallel conversion performed by the serial / parallel conversion means for min. 2. The demodulator according to the quasi-coherent detection method according to claim 1, wherein the reset means intermittently generates an intermittent mask signal which becomes an enable level intermittently, and the I component. The output signal of the detection means indicating whether the phase of the serial / parallel conversion performed by the serial / parallel conversion means and the phase of the serial / parallel conversion performed by the serial / parallel conversion means for the Q component match. A logic gate masked by the intermittent mask signal; and a phase of serial / parallel conversion performed by the serial / parallel conversion unit for the I component, and a serial / parallel conversion performed by the serial / parallel conversion unit for the Q component. When the output of the detection means indicates that the phases of conversion do not match, and The phase of serial / parallel conversion performed by the serial / parallel conversion means for the I component and the phase of serial / parallel conversion performed by the serial / parallel conversion means for the Q component when the missing mask signal is at the enable level are described. A demodulator using a quasi-synchronous detection method that is reset at the same time. 3. The demodulator according to the quasi-coherent detection method according to claim 1, wherein the reset means is for the phase of serial / parallel conversion performed by the serial / parallel conversion means for the I component and for the Q component. When the logic level of the output signal of the detection means, which indicates whether the phases of the serial / parallel conversion performed by the serial / parallel conversion means of the above-mentioned match, changes from the logic level indicating the match to the logic level indicating the mismatch, A phase for serial / parallel conversion performed by the serial / parallel conversion means for the I component and serial / parallel conversion performed by the serial / parallel conversion means for the Q component. The logic level of the output signal of the detection means indicating whether the phases match or not indicates the mismatch from the logic level indicating the match The phase of serial / parallel conversion performed by the serial / parallel conversion means for the I component and the phase of serial / parallel conversion performed by the serial / parallel conversion means for the Q component are simultaneously reset when the logic level is changed. A demodulator using a quasi-synchronous detection method characterized by the above. 4. The demodulator according to the quasi-coherent detection method according to claim 1, wherein the serial / parallel conversion means for the I component and the serial / parallel conversion means for the Q component are provided. Are a first flip-flop circuit that clock-synchronizes an input signal, a second flip-flop circuit that delays the output of the first flip-flop circuit by one clock, and a frequency dividing circuit that divides the clock. A third and a fourth flip-flop for synchronizing the output of the first flip-flop circuit and the output of the second flip-flop circuit with the divided clock, and the output of the divider circuit A demodulator by a quasi-synchronous detection method, wherein the serial / parallel conversion means is reset by being reset. 5. The demodulator by the quasi-coherent detection method according to claim 1, wherein the I component is obtained by multiplying the received signal by a local oscillation signal whose frequency is close to the carrier of the received signal. A first multiplication means, a first multiplication means for obtaining the Q component by multiplying the received signal by a signal having the same frequency as the local oscillation signal and a phase difference of π / 2; A first A / D conversion means for D conversion and a second A / D conversion means for A / D conversion of the Q component, wherein the serial / parallel conversion means for the I component is
Semi-synchronous, characterized in that the I / D converted I component is serial / parallel converted, and the serial / parallel conversion means for the Q component is serial / parallel converted to the A / D converted Q component. Demodulator by detection method. 6. The demodulator according to the quasi-coherent detection method according to claim 5, wherein the output level of the serial / parallel conversion means for the I component and the output of the serial / parallel conversion means for the Q component are An automatic amplitude correction means for correcting a level difference and an output of the automatic amplitude correction means are input, and the I component and the Q component in which the deviation between the frequency of the carrier wave and the frequency of the local oscillation signal is corrected are output. Carrier wave synchronizing means, parallel / serial converting means for parallel / serial converting the output of the carrier wave synchronizing means, clock phase detecting means for detecting the phase of the clock from the output of the carrier wave synchronizing means, and the clock phase detecting means for outputting A low-pass filter that integrates the phase detection signal, and D / A conversion means that performs D / A conversion on the output of the low-pass filter, A voltage controlled oscillator for generating an oscillation signal whose frequency is controlled by the output of the D / A converter, the first and second A / D converters, the parallel / serial converter, and the clock The quasi-synchronous detection system demodulator, wherein the phase detection means, the low-pass filter, and the D / A conversion means use the oscillation signal output from the voltage controlled oscillation means as a clock.