JP3503004B2 - IC with pre-buffer control function - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is pre-buffer control
More specifically, the present invention relates to an IC for pulse generation , and more particularly to an IC having a pre-buffer control function for rapidly performing an operation with a changed control mode.

[0002]

2. Description of the Related Art For example, in an NC machining apparatus or the like, movement control of a work or a cutting tool in the X-axis, Y-axis, Z-axis or θ-axis direction is controlled by the frequency of a pulse supplied to a stepping motor as a drive source. , By changing parameters such as the number of pulses. Conventionally, in such a device, C
The movement control mode (acceleration / deceleration, movement amount, etc.) is set by sending a control signal from the PU to the pulse generation circuit.

By the way, the above control mode needs to be changed every moment in accordance with the machining mode, and the CP mode is changed every time it is changed.
From U, the changed frequency data, acceleration / deceleration data, movement amount data, control data, and other data are supplied to a pulse generation circuit (usually composed of an IC) and written in a register provided in the IC, In response to the reception of the start command from the CPU, control is performed according to the data content written in the register.

[0004]

However, if these data are written to the register during operation, the content of the write changes. For example, if the frequency data is rewritten during operation, the operating frequency also changes. . Therefore, the data can be written to the register only while the operation is stopped. If you want to operate continuously with different data, etc., the data written to the register by the CPU must be between the stop and the next operation. It takes time to write.

FIG. 3 shows a timing chart of such an operation. During the period of operation stop of the pulse generation circuit shown in FIG. 3D, as shown in FIG. 3A, the frequency data as the operation data written in the register of the circuit is first input, and then, After the movement amount data and the like are input as shown in FIG. 3 (B), the operation starts in response to the input of the start command as the operation data, as shown in FIG. 3 (C).

Generally, when the pulse generating IC is stopped, the CPU often performs other control as compared with the operation.
When a CPU with a slow speed is used, this time also becomes long, and there is a problem that work efficiency is reduced.

An object of the present invention is directed to the controlled device
In the pulse generating IC of Te, the writing of control data to allow even during operation of the pulse generating circuit is to provide an IC having a pre-buffer control function to enable high-speed operation.

[0008]

[Means for Solving the Problems]
Prebuffer control according to the present inventionIC with functions
IsA control unit for operation control and a pulse generation circuit are provided, and C
PUOperation data sent fromProvided in the control unit
WasbufferData latch for operation asWrite toOnly
Shi, TheData latch for operationAccording to the data read from
handPulse generatorTo controlPulse generation configured as
IC forAnd saidThe control unit also has a pre-buffer
Equipped with a pre-data latch and a state determination circuit
The state determination circuit determines whether the pulse generation circuit is operating or stopped.
RefuseDuring operationIsThe operation data isPre-data
latchWrite toWhile operating, the data
The pre-data latch as well as
If there is data for the operation by judging whether or not there is data
In case ofWhen the operation is stoppedPre-data latchFrom
readingWrite to the operation data latch,pull
Then, in response to the next operation start signal,
To follow the controlIn orderComposed.

Here, the circuit of the pulse generating IC for generating a pulse of a predetermined mode is a circuit for generating a pulse as operation data for performing acceleration / deceleration control and movement amount control of a stepping motor to be controlled. be able to.

[0010]

According to the present invention, after the operation data is written in the pre-data latch during the operation of the pulse generation circuit of the IC , the operation data read from the pre-data latch when the next operation is stopped is read, and the subsequent next operation start signal is read. In response to, the control is performed according to the operation data.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows the prebuffer control according to the present invention.
7 is an operation timing chart in one embodiment of an IC having a function .

In the present embodiment, a pre-data latch 3 is prepared as a pre -buffer for the next operation data area in the pulse generation circuit of the IC as the controlled device, and the CPU area is lightly loaded in this data area. The data for the next operation is written in advance even when the circuit for pulse generation is operating. As shown in FIGS. 1A, 1B and 1D, during the operation of the pulse generating circuit, frequency data and pre-data such as a moving amount are written in the pre -data latch 3 , and a pre-data start command ( After the input of FIG. 1C, when the pulse generation circuit is stopped (FIG. 1D), that is,
As shown in FIG. 1 (E), after the operation end timing, as shown in FIGS. 1 (F) and (G), the frequency data and the movement amount data read from the pre-data latch 3 are input as control data. , A start command as operation data read from the pre-data latch 3 (see FIG.
In response to (H)), the next operation starts as shown in FIG.

FIG. 2 is a block diagram showing the configuration of the control unit of the pulse generating circuit according to this embodiment. Control unit
Is the operation data latch 5, pre-data latch 3, state
The judgment circuit 1, the selector 4, and the OR gate 2 are provided. Na
Note that the setting data in the explanation of FIG.
For distinguishing from the operation data sent from the switch 5.
It was what I had.

In this embodiment, the state judgment circuit 1
Be determined pulse generating circuit operation state of either running or stopped
The Rukoto, in operation stops using no pre-buffer, setting data is written to the operation data latch 5,
The contents are taken into the pulse generation circuit and the operation is controlled. Then, in operation using the pre-buffer, addressing mode with pre-decrement
Taratchi 3 Data is written to, and the operation ends, if the setting data in the pre-data latch 3 is stored, and setting data stored in the pre-data latch 3 is sent to the operation data latch 5 pulse generator The next operation is controlled by being taken into the circuit for use.

The setting data sent from the CPU is input terminal D of the pre-data latch 3 and input terminal A of the selector 4.
Is supplied to. As described above, the state determination circuit 1 has three states, that is, the state A of operating and data input (pre-data input), the state B of start pre-data and ending of operation, and the state C of stopping and data input. Determine the status and output. When it is determined that the state is A, the pulse generation circuit
During the operation of the path, its output is supplied to the gate G of the pre-data latch 3 and the setting data is input from the input terminal D to the pre-de- latch.
Captured in the data latch 3 . The input terminal A of the selector 4
Setting data from the CPU, the input terminal B is supplied with configuration data from the pre-data latch 3, has become so that the output from the output terminals Q, state determination circuit 1
Depending on the judgment signal of status B or status C from
If there is no data in the data latch 3, the pulse generation circuit stops.
If there is data from input terminal A when stopped, if there is data
After the operation is completed , any data is output from the output terminal Q from the input terminal B and written in the operation data latch 5.
Ru is.

The state B and the state C are input to the input of the OR gate 2.
Is inputted to the gate G of the operation data latch 5. Data latch for operation 5
Input terminal is input data from the output terminal Q of the selector 4 is the D, and after the correction or pulse generating circuit
In response to the output from the OR gate 2 to the gate G during the stop of, the data from the output terminal Q of the selector 4 is fetched and latched. The read operation data is output from the output terminal Q of the operation data latch 5 to control the operation of the pulse generation circuit.

[0017]

As described in the foregoing, according to the IC with a pre-buffer control function of the present invention, to allow the writing to the pre-data latch 3 of the control data for pulse generation circuit even during operation of the pulse generating circuit, moreover ,That
Writing during operation is performed while judging the state of data input.
Can be squeezed, and further to the operation data latch 5
Even when writing data, the pulse generation circuit is stopped
The next operation that can be written according to the state of whether or not
It can be controlled, and high-speed operation is possible as a whole .

[Brief description of drawings]

FIG. 1 shows an I having a pre-buffer control function according to the present invention.
9 is an operation timing chart in an example of C.

2 is a configuration block diagram of a control unit of a pulse generation circuit in the embodiment shown in FIG.

FIG. 3 is an operation timing chart of a control method of a conventional IC .

[Explanation of symbols]

1 State judgment circuit 2 OR gate 3 Pre-data latch 4 selector 5 Data latch for operation

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G05B 19/18-19/46 H02P 8/00

Claims (2)

(57) [Claims] 1. A control unit for controlling operation and a pulse generation circuit
And control the operation data sent from the CPU.
The operation data latch as a buffer provided in part sewing <br/> writing write, configured to control the pulse generating circuit according to the read data from the operation data latch Pas
And a control circuit , wherein the control unit further includes a driver.
Equipped with a pre-data latch as a buffer and a status judgment circuit
Yes, the status judgment circuit stops the pulse generation circuit
And determining whether in the said operation data during operation flop
Mississauga write to Li data latch, de for the operation is stopped
Data into the data latch and the pre-data latch
By determining whether or not there is operation data, the operation data
If there is, the pre-data
Write the operation data latch read from pitch
An IC having a pre-buffer control function, which is configured to perform control in accordance with the operation data in response to a subsequent next operation start signal. 2. The pulse generation circuit is configured to generate a pulse as operation data for performing acceleration / deceleration control and movement amount control of a stepping motor as a control target.
IC having a pre-buffer control function according to claim 1, characterized in that that have been.