JP3491480B2 - Timing recovery circuit and demodulator using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing recovery circuit and a demodulator, and particularly to a high bit rate, P
It can be applied to a demodulator of a digital high-speed wireless communication device using an SK (Phase Shift Keying) modulation method.

[0002]

2. Description of the Related Art Conventionally, as a timing recovery circuit of a demodulator for digital radio communication equipment using a PSK modulation system,
For example, in the document “π / 4 shift Q using received signal phase information”
Examination of timing reproduction method for PSK "(Fujimura 199
As described in the 6th IEICE General Conference B-450, there is a feedback type that samples phase data at four times the symbol rate and that realizes high-speed phase pull-in. A conventional technique will be described below with reference to the drawings. FIG. 22 shows a conventional demodulator including the above timing recovery circuit. In the figure, 1 is a limiter, 2 is a quadrature detection circuit, 3 is a quadrature detection local oscillator, 4 is a sampling circuit, 5 is a polar coordinate conversion circuit, 6 is a data determination circuit, 7 is a timing reproduction circuit, and 8 is a symbol rate of 1.
Fixed clock oscillators for timing reproduction having a frequency of 6 times, 4a1 and 4b are AD converters.

Next, the operation will be described with reference to the drawings.
Here, the modulation method is π / 4 shift differential encoding QPSK.
Use modulation method. The limiter 1 limits the amplitude of the received IF signal. The quadrature detection circuit 2 outputs the IF signal whose amplitude is limited,
Quadrature detection is performed using a local signal having the same frequency as the center frequency of the IF signal output from the quadrature detection local oscillator 3, and converted into a baseband in-phase signal and a baseband quadrature signal. The AD converters 4a and 4b forming the sampling circuit 4 perform AD conversion of the baseband in-phase signal and the baseband quadrature signal by using a reproduction quadruple clock having a frequency four times the symbol rate supplied from the timing reproduction circuit 7. Then, the 4 × oversampled data after AD conversion is output as baseband in-phase data and baseband quadrature data. The baseband in-phase data and the quadrature data are input to the polar coordinate conversion circuit 5. Polar coordinate conversion circuit 5
Converts the baseband in-phase data and baseband quadrature data from the sampling circuit 4 into polar coordinates and outputs them as in-phase and quadrature baseband phase data.

The timing reproduction circuit 7 controls the phase of the quadruple reproduction clock so as to sample the Nyquist point of the baseband in-phase / quadrature signal from the baseband phase data output from the polar coordinate conversion circuit 5, and the data determination circuit 6 uses the Nyquist signal. The phase of the reproduced symbol clock for extracting the phase data of the point is controlled. Since the timing recovery circuit 7 controls the phase of each clock at 1/16 symbol step intervals, it requires a fixed clock with a frequency 16 times the symbol rate. This fixed clock is supplied from the fixed clock oscillator 8 for timing reproduction. The data determination circuit 6 extracts the phase data at the Nyquist point from the baseband phase data from the sampling circuit 4 using the reproduction symbol clock reproduced by the timing reproduction circuit 7. Then, differential detection is performed using the extracted phase data at the Nyquist point and demodulated data is output. As described above, since the demodulator described as the conventional example operates by using the received PSK signal whose amplitude is limited and has the feedback type configuration that performs the AD conversion at the timing of the reproduction quadruple clock, the limiter is provided in the preceding stage. It can be configured with a simple circuit included in the above, and miniaturization of the circuit can be realized.

FIG. 23 is a diagram showing a detailed structure of the timing reproduction circuit in FIG. 71 is a symbol frequency component generation unit, 72 is a complex multiplication unit, 73 is a low-pass filtering unit, 74 is a phase control unit, 711 is a phase difference circuit, 712 is a data conversion circuit, 71
1a, 711b, 72a, 72b, 72e, 72f are D
Flip-flops, 711c, 72c and 72d are subtractors, 712a is an absolute value conversion circuit, 712b is a phase data conversion circuit, 73a and 73b are integration filters, 73c is an arctangent circuit, 73d is an integration filter control circuit, and 74a is 4
It is a bit down counter. Next, the operation of the timing reproduction circuit 7 will be described with reference to the drawings. From the PSK-modulated baseband phase data θ (t), a symbol frequency component Δθ (t) having a DC offset can be generated by the following equation (1a). However, the symbol period is T. Δθ (t) = min {| θ (t) −θ (t−T / 2) |, 2π− | θ (t) −θ (t−T / 2) |} (1a) As an example, FIG. π / 4 shift QPSK-modulated random pattern baseband phase data θ (t)
And Δθ (t) generated from θ (t). O marks are Nyquist point data. The horizontal axis represents time and the unit is the symbol period T. The vertical axis represents phase and the unit is radian. Since it is the π / 4 shift QPSK modulation method, the phase transition between the Nyquist points of the baseband phase data θ (t) is ± π / 4 and ± 3π / 4. As can be seen from FIG. 24, Δθ (t) has a DC offset A indicated by a dotted line, and a symbol frequency (fs) component (s) on the transmission side (s) is generated.
It can be seen that it includes in2πfs (t) + A).

In the conventional timing reproduction circuit 7, the DFT
Since the timing phase is estimated by the calculation based on (Discrete Fourier Transform), it is necessary to sample θ (t) at a sampling rate four times the symbol rate. Therefore, in the conventional timing recovery circuit 7, θ
(T) is the discrete data θ (i
T / 4) (where i = {1, 2, 3, ...}). The symbol frequency component generation unit 71 calculates a data sequence Δθ (iT / 4) including a symbol frequency component from the input baseband phase data θ (iT / 4) oversampled at four times the symbol rate, using the following equation ( 1b). Δθ (iT / 4) = min {| θ (iT / 4) −θ ((i-2) T / 4) |, 2π− | θ (iT / 4) −θ ((i-2) T / 4 ) |} (1b) The phase difference circuit 711 calculates θ (iT / 4) −θ ((i
-2) Perform T / 4) difference. This processing is performed based on the current phase data by 2 sample time D flip-flops 711a, 7a.
The phase data delayed by 11b is applied to the subtractor 711c.
It can be realized by making a difference using. Also, the absolute value conversion circuit 712a performs absolute value conversion of this phase difference value, and the phase data conversion circuit 712b subtracts the absolute value converted phase data and the absolute value converted phase data from 2π in radians. By outputting the smaller one of the values, the processing of the above formula (1) is realized. The phase data conversion circuit 712b can be easily configured by a subtractor and a comparator.

The complex multiplication section 72 calculates the correlation of one symbol between Δθ (iT / 4) including the frequency component fs on the transmission side and the symbol frequency (fs ■) on the receiver side by the following equation (2a ), (2b). CI (jT) is
The in-phase component of the correlation value at the j (= 1, 2, 3, ...) Symbol, and CQ (jT) are the orthogonal components of the correlation value at the j (= 1, 2, 3, ...) Symbol.

[0008]

[Equation 1]

The above cos 2πfs ((iT / 4) is 1,
It is a repetition of 0, -1, 0, 1, ...
Since 2πfs (iT / 4) is a repetition of 0, 1, 0, -1, 0, ..., CI (jT) and CQ (jT) above are
It can be easily calculated by the following equations (3a) and (3b). CI (jT) = Δθ (3jT / 4) −Δθ ((4j-2) T / 4) (3a) CQ (jT) = Δθ ((4j-3) T / 4) −Δθ ((4j-1) T / 4) (3b) In the actual circuit, CI (jT) is the current Δθ (iT / 4) from Δθ (iT / 4) latched by the D flip-flop 72a operating at the rising edge of the reproduction double clock. Subtractor 7
It is easily obtained by subtracting by 2c and latching the data after the subtraction by the D flip-flop 72e which operates at the rising edge of the reproduced symbol clock. Similarly, CQ (jT)
Is reproduced from Δθ (iT / 4) latched by the D flip-flop 72b which operates at the falling edge of the reproduction double clock.
D flip-flop 7 that operates at the falling edge of the double clock
This can be easily obtained by subtracting Δθ (iT / 4) latched by 2f by the subtractor 72d and latching the data after the subtraction by the D flip-flop 72e which operates at the rising edge of the reproduced symbol clock.

Next, the low-pass filtering section 73
First, the CI (jT) and CQ (jT) are integrated by the integration filter 73.
A and 73b are averaged to remove noise components and the like, and the averaged signals are output as DI (jT) and DQ (jT). The integration filter is, for example, the following formula (4a),
An infinite impulse response type filter operating in (4b) is used. However, α is a forgetting factor, and (0 <α <
Take the range of 1). DI (jT) = DI ((j-1) T) × α + CI (jT) (4a) DQ (jT) = DQ ((j-1) T) × α + CQ (jT) (4b)

Next, in the arctangent circuit 73c, DI (jT),
The vector angle Δθj indicated by DQ (jT) can be calculated by the following equation (5).
Ask by. Δθj = tan−1 (DQ (jT) / DI (jT)) (5) This vector angle Δθj is the symbol frequency component sin2πfs (t) included in the phase data on the transmission side and the symbol frequency component fs ■ on the reception side. The following equation (6) is established because the phase difference is sin2πfs (t) = cos (2πfs (t) + Δθj) (6) Therefore, the phase correction value Ej that cancels the timing phase error can be obtained from this Δθj.

The integral filter control circuit 73d outputs the phase error Ej and the control command signal only when the symbol time j is a multiple of a certain time k. That is, the phase correction value Ej and the control command signal are output at k symbol intervals. The phase control unit 74 uses, for example, a 4-bit down counter 74a.
And is driven by the 16-fold symbol rate clock which is the operation clock unless the phase correction value Ej and the control command signal are input. The most significant bit to the third bit of the 4-bit down counter 74a are outputted as a reproduction symbol clock, a reproduction double clock and a reproduction quadruple clock, respectively. When the phase correction value Ej and the control command signal are input to the phase control unit 74, the phase correction value Ej is synchronously loaded into the 4-bit down counter 74a. In this example, the timing of synchronous loading is as follows when the 4-bit down counter 74a is free running.
The timing is “0”.

FIG. 25 shows an example of this operation. At time A, the timing phase error between the rising edge of the reproduced symbol clock and the Nyquist point is -3π / 8. -3
In order to cancel the timing phase error of π / 8, the low-pass filtering unit 73 performs the above-described processing to set the phase of the recovered clock to 3π / 8, and when the time is 3T / 16.
(T: symbol period) Give an instruction to advance. In this case, 4
At time B indicating “0” when the bit down counter 74a is free running, the low-pass filtering unit 73 outputs the phase correction value Ej = 3 and the control command pulse (logic “1”) (loads the phase correction value Ej). Then, the corrected clock phase becomes Ejπ / 8). The 4-bit down counter 74a synchronously loads the phase correction value Ej when the control command signal indicates the logic "1". By the above processing, the rising point of the reproduced symbol clock and the Nyquist point match at time C, and the data at the Nyquist point is sampled after time C. Further, when the control command signal indicates logic "1", the integration filter controls the integration filter by the following equation (7).

[0014]

[Equation 2]

According to this control, the integration filter can be used even after the first phase control, so that a feedback type timing reproduction circuit for performing high-speed pull-in using the integration filter can be realized. As described above, the conventional timing reproduction circuit 7 includes Δθ (t) including the frequency component fs on the transmission side.
And the timing phase error is obtained from the vector angle indicated by the correlation value with the symbol frequency (fs2) on the receiver side, so that high-speed phase pull-in characteristics can be realized.

[0016]

As described above, since the conventional timing recovery circuit 7 needs to multiply Δθ (t) by the cosine component and the sine component of the symbol frequency on the receiver side, respectively, at least. Symbol rate of 4
The main multiplication cannot be realized unless Δθ (t) is calculated at the double timing. Therefore, the timing reproduction circuit 7 needs to oversample the baseband data at four times the symbol rate.

Further, in the conventional position control section 74, the number of phase control steps of the recovered clock needs to be made sufficiently small, so that the conventional phase control section 74 has a symbol rate of 16
It is necessary to operate with a clock of double frequency.

On the other hand, in recent years, a communication system which realizes wireless transmission at a high symbol rate of several tens Mbaud or more has been in the spotlight. When the conventional timing recovery circuit 7 is used in such a high-speed wireless communication system, the data oversampling frequency and the operating frequency of the phase control unit 74 are very high, from several tens of MHz to several hundreds of MHz. Power consumption increases. In addition, the demodulator is CMO
It becomes difficult to form the S gate array, and it becomes difficult to form an LSI.

The present invention has been made in order to solve the above problems, and realizes a high-speed timing phase pull-in characteristic by oversampling data at twice the symbol rate and at the same time as the symbol rate. It is an object of the present invention to provide a timing reproduction circuit which realizes a sufficiently small number of phase control steps of a reproduction clock while operating at twice the frequency or the same frequency as the symbol rate. Further, even when performing wireless communication at a high symbol rate of several tens of Mbaud or more, a demodulator that achieves both good bit error rate characteristics and low power consumption and can be implemented as an LSI using a CMOS gate array is provided. The purpose is to do.

[0020]

SUMMARY OF THE INVENTION A timing recovery circuit according to the present invention is a phase that subtracts 1/2 symbol of baseband phase data oversampled at twice the symbol rate and outputs the difference result as phase difference data. The difference part, the phase difference absolute value data obtained by converting the phase difference data into an absolute value, or the value obtained by subtracting the phase difference absolute value data from 2π in radians is the symbol frequency component data, which is twice the symbol rate. The symbol frequency generation section having a data conversion section for outputting at the timing of.

A timing reproduction circuit according to the next invention is
A multiplication unit that multiplies the symbol frequency component data by the symbol frequency component output from the phase control unit to be described later, and outputs the multiplication data, and a low-pass that averages the multiplication data and outputs the averaged data as a timing phase error signal. a filtering unit, on the basis of the timing phase error signal, reproducing the transmission timing of the transmit-side symbol black Tsu
The click so as to phase lock in which and a phase system Gyosu that phase controller.

A timing recovery circuit according to the next invention further comprises a random walk filtering section for averaging the multiplication data in the low pass filtering section.

Further, a timing recovery circuit according to the next invention uses two or more pieces of baseband phase data which are oversampled at twice the continuous symbol rate, and uses the phase at a symbol period / 4 from each sampling point. Data is calculated using interpolation calculation, the calculated value is phase interpolation data, the phase interpolation data is subtracted by 1/2 symbol, the difference result is interpolation phase difference data, and the interpolation phase difference data is subjected to absolute value conversion. The smaller of the phase difference absolute value data and the value obtained by subtracting the interpolation phase difference absolute value data from 2π in radians is the symbol frequency component interpolation data, and is output at a timing twice the symbol rate. The interpolation data calculation unit and the symbol frequency component interpolation data are added to the symbol output from the phase control unit. The in-phase component of the frequency
A complex multiplication unit that outputs as in-phase multiplication data, multiplies the symbol frequency component data by a quadrature component of a symbol frequency output from a phase control unit described below, and outputs as a quadrature multiplication data; , The first integral filtering unit that averages with the integral type filter and outputs it as timing in-phase data, and the second integral filtering unit that averages the quadrature multiplication data with the second integral type filter and outputs it as timing quadrature data, Timing in-phase data, an arctangent portion for obtaining the arctangent value of the timing quadrature data, and a timing phase error signal is obtained from the arctangent value at r symbol periods and output. At the same time, the timing in-phase data is output to the first integral type filter. And the vector length indicated by the timing quadrature data are set, and the product that resets the second integral filter And integrating filter control unit for outputting a filter set signal based on the timing phase error signal, the transmission recovered symbol clock to the transmission timing of the signal side so as to <br/> phase synchronized with the phase system Gyosu that phase controller Be prepared.

[0024]

[0025]

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further In the phase control unit, the correction delay value is subtracted from the timing phase error signal, and the value obtained by cumulatively adding the subtraction results is output as the delay time setting signal, and the delay time setting signal is used to generate a fixed clock. A clock phase shifter that delays the set fixed time, divides the delayed fixed clock by two, and outputs it as a reproduced symbol clock, and outputs 0 as a correction delay value during significant data reception. , While receiving meaningless data,
When the delay time setting signal indicates the time exceeding one cycle of the fixed clock, the value corresponding to one cycle of the fixed clock is output as a correction delay value, and the time when the delay time setting signal exceeds -1 cycle of the fixed clock is indicated. Tara's fixed clock
A correction delay value calculation unit that outputs a value corresponding to one cycle as a correction delay value and outputs 0 as a correction delay value while the delay time setting signal indicates a time within ± 1 cycle of the fixed clock. Be prepared.

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further In the phase control unit, the correction delay value is subtracted from the timing phase error signal, and the value obtained by cumulatively adding the subtraction results is output as the delay time setting signal, and the delay time setting signal is used to generate a fixed clock. A clock phase shifter that delays by a set time and outputs a delayed fixed clock as a reproduction symbol clock, and outputs 0 as a correction delay value during significant data reception, and during meaningless data reception, If the delay time setting signal indicates a time that exceeds one cycle of the fixed clock, supplement the value corresponding to one cycle of the fixed clock. When output as a positive delay value and the delay time setting signal indicates a time exceeding -1 cycle of the fixed clock, a value corresponding to -1 cycle of the fixed clock is output as a correction delay value, and the delay time setting signal ± 1
A correction delay value calculation unit for outputting 0 as a correction delay value is provided while the time within the cycle is shown.

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further In the phase control unit, the correction delay value is subtracted from the timing phase error signal, and the value obtained by cumulatively adding the subtraction results is output as the first delay time setting signal by the delay time setting signal calculation unit and the delay time setting signal. A second clock that outputs a value obtained by cumulatively adding a first clock phase shifter that delays a fixed clock for a set time and outputs it as a first delay clock, and a second delay time setting signal With the delay time setting signal calculation unit and the second delay time setting signal, the fixed clock is delayed by the set time The second clock phase shifter that outputs the second delay time setting signal and the absolute value of the time difference between the delay time indicated by the value of the first delay time setting signal and the fixed clock cycle are indicated by the value of the second delay time setting signal. If the absolute value of the time difference between the delay time and the fixed clock cycle is smaller than the absolute value, the first delay clock is output. A clock selection unit that selects either the first delay clock or the second delay clock based on the signal, and outputs a clock obtained by dividing the selected clock by two as a reproduction symbol clock; For the delay clock,
The first delay clock phase detects whether the phase is advanced or delayed, and outputs the detection information as a phase detection signal and a clock phase comparison unit that averages the phase detection signal and outputs an averaged phase detection signal. It includes an averaging unit, an error value accumulating unit that accumulates the averaged phase detection signals, adds the time corresponding to the accumulated value, the period of the fixed clock, and outputs the sum as a correction delay value.

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further In the phase control unit, the correction delay value is subtracted from the timing phase error signal, and the value obtained by cumulatively adding the subtraction results is output as the first delay time setting signal by the delay time setting signal calculation unit and the delay time setting signal. A second clock that outputs a value obtained by cumulatively adding a first clock phase shifter that delays a fixed clock for a set time and outputs it as a first delay clock, and a second delay time setting signal With the delay time setting signal calculation unit and the second delay time setting signal, the fixed clock is delayed by the set time The second clock phase shifter that outputs the second delay time setting signal and the absolute value of the time difference between the delay time indicated by the value of the first delay time setting signal and the fixed clock cycle are indicated by the value of the second delay time setting signal. A clock switching determination unit that outputs a clock selection signal that specifies a first delay clock if the absolute value of the time difference between the delay time and the fixed clock period is smaller than the absolute value, and a clock selection signal that specifies the second delay clock if it is larger Based on the selection signal, select either one of the first delay clock or the second delay clock and output the selected clock as the reproduction symbol clock, and for the second delay clock, The first delayed clock phase detects whether the phase is advanced or delayed and outputs the detection information as a phase detection signal, and the phase detection signal is averaged and averaged. And an error value accumulator that accumulates the averaged phase detection signals, adds the time corresponding to this accumulated value and the fixed clock cycle, and outputs the corrected delay value. And with.

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further The phase controller uses a π phase shifter that outputs a π phase-shifted signal in radians as a π phase-shifted clock and a clock selection signal to compare either the fixed clock or the π phase-shifted clock. A surplus when a clock switching unit that outputs the other as a clock and a timing phase error signal are cumulatively added, and the value after cumulative addition is divided by the time corresponding to one cycle of the fixed clock. It is the time when the phase-shifting clock is set by the cumulative adder that outputs the value as the delay time setting signal and the delay time setting signal. The delayed and delayed signal is used as the reproduction clock, the reproduction clock is divided by 2 and the signal is output as the reproduction symbol clock, and the comparison clock is divided by 2 and the divided clock is compared by 2. For comparison, a first divide-by-two division unit for outputting as a divided-by-two clock and a second divide-by-half unit for dividing the reproduction clock by two and outputting the divided clock as a reproduction divided-by-two clock, Sampling the divided-by-2 clock with the reproduced divided-by-2 clock,
When a change occurs in the sampled data, a reset signal that resets the cumulative addition value in the cumulative addition unit to 0 at the time of the change, and a clock that switches logic “1” and logic “0” at the time of the change And a clock switching signal output section for outputting a selection signal.

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further The phase controller uses a π phase shifter that outputs a signal that is a π phase shift of a fixed clock in radians as a π phase shift clock and a clock selection signal for comparing either the fixed clock or the π phase shift clock. A surplus when a clock switching unit that outputs the other as a clock and a timing phase error signal are cumulatively added, and the value after cumulative addition is divided by the time corresponding to one cycle of the fixed clock. It is the time when the phase-shifting clock is set by the cumulative adder that outputs the value as the delay time setting signal and the delay time setting signal. A clock phase shifter for outputting the delayed and delayed signal as a reproduction clock, outputting the reproduction clock as a reproduction symbol clock, and the comparison clock divided by 2 and outputting the divided clock as a comparison divided by 2 clock. A first division-by-two division unit, a reproduction clock divided by two, a division-by-two clock output as a reproduction division-two clock, and a comparison division-two clock When sampling is performed with a divide-by-two clock and a change occurs in the sampled data, a reset signal that resets the cumulative addition value in the cumulative addition unit to 0 at the time of the change, and a logic “1” at the time of the change, And a clock switching signal output section for outputting a clock selection signal for switching logic "0".

Further, in the timing recovery circuit according to the next invention, the fixed phase clock is applied to the time y in the clock phase shifter.
From the time y × (N−1) to y time steps to generate (N−1) delayed clocks, and N clocks including the fixed clock and the (N−1) delayed clocks. From the delay clock group based on the delay time setting signal, the clock selection signal generating section that generates and outputs the clock selection signal based on the delay time setting signal, A clock selection unit that selects one and outputs it as a delay clock is further provided, and the delay clock group generation unit further includes (N-1) delay units that give a delay time y by a delay element.

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further In the phase control unit, a cumulative addition unit that cumulatively adds the timing phase error signals and outputs a surplus value when the value after the cumulative addition is divided by the time corresponding to one cycle of the local sine wave is output as a delay time setting signal. , The value indicated by the delay time setting signal is expressed in terms of the phase with respect to the cycle of the local sine wave, and the sine value is calculated.
A cosine-sine converter that outputs as sine data, two cosine data and two DA converters that quadrature-modulate the sine data with a local sine wave and output the quadrature-modulated signal as a timing reproduction signal. Low-pass filter, two multipliers, one adder, one π
A quadrature modulation section composed of a / 2 phase shifter and a hard decision section for making a hard decision on a timing reproduction signal and outputting a signal obtained by dividing the data after the hard decision by two as a reproduction symbol clock. .

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further In the phase control unit, a cumulative addition unit that cumulatively adds the timing phase error signals and outputs a surplus value when the value after the cumulative addition is divided by the time corresponding to one cycle of the local sine wave is output as a delay time setting signal. , The value indicated by the delay time setting signal is expressed in terms of the phase with respect to the cycle of the local sine wave, and the sine value is calculated.
A cosine-sine converter that outputs as sine data, two cosine data and two DA converters that quadrature-modulate the sine data with a local sine wave and output the quadrature-modulated signal as a timing reproduction signal. Low-pass filter, two multipliers, one adder, one π
A quadrature modulation section composed of a / 2 phase shifter and a hard decision section for making a hard decision on a timing reproduction signal and outputting the data after the hard decision as a reproduction symbol clock.

The timing recovery circuit according to still another aspect of the present invention is based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmit side, further In the phase control unit, a cumulative addition unit that cumulatively adds the timing phase error signals and outputs a surplus value when the value after the cumulative addition is divided by the time corresponding to one cycle of the fixed clock is output as a delay time setting signal, When the value indicated by the delay time setting signal is expressed in terms of phase with respect to the fixed clock period, the cosine value and the sine value are obtained, and the cosine and sine converters that output as cosine data and sine data respectively, and twice the regenerated clock The frequency of the double fixed clock having the frequency of 2 is divided by 2 to generate a fixed clock, and the logic of the fixed clock is In the case of 1 ", the cosine data is output as it is, and when the logic of the fixed clock is" 0 ", the first sign inversion unit that multiplies the cosine data by" -1 "and outputs the result is the logic of the fixed clock. In the case of "1", the sign data is output as it is. When the logic of the fixed clock is "0", the second sign inversion unit which multiplies the sign data by "-1" and outputs it, and the double fixed clock are When the logical value is “1”, the output value of the first sign inverting section is output as quadruple reproduction timing data, and when the double fixed clock is logical “0”, the output value of the second sign inverting section is quadrupled. A clock amplitude value selection unit that outputs as timing reproduction data, a DA conversion unit that DA-converts the quadruple timing reproduction data and converts it to an analog timing signal, a low-pass filtering of the analog timing signal, and a harmonic wave. An analog low pass filtering unit that outputs a frequency was removed signal as a timing regeneration signal, the timing recovery signal hard decision, the data after the hard decision, in which and a hard decision unit for outputting as the recovered symbol clock.

Further, a demodulator according to the next invention is a timing recovery circuit which inputs baseband phase data oversampled at twice the symbol rate and outputs a recovered symbol clock phase-synchronized with the transmission timing on the transmission side. And an amplitude limiting unit for limiting the amplitude of the PSK-modulated reception IF signal, and I
A quadrature detection unit that performs a complex multiplication of a local signal having the same frequency as the F signal, low-pass filters the in-phase component after the complex multiplication and the quadrature component after the complex multiplication, and outputs them as a baseband in-phase signal and a baseband quadrature signal, respectively. And a sampling unit that oversamples the baseband in-phase signal and the baseband quadrature signal at the timing of twice the symbol rate synchronized with the reproduced symbol clock, and outputs as baseband in-phase data and baseband quadrature data, respectively. , The baseband in-phase data and the baseband quadrature data are converted into polar coordinates, and the polar coordinate conversion unit that outputs the data after the polar coordinate conversion as the baseband phase data and the regenerated symbol clock are used to latch the baseband phase data and Judge demodulated data from phase data and output In which and a that the data determination unit.

A demodulator according to the next invention outputs a regenerated symbol clock phase-synchronized with the transmission timing on the transmission side, and outputs a fixed clock having a frequency twice the symbol rate or a local clock having a frequency twice the symbol rate. A timing recovery circuit that generates a recovered symbol clock from a sine wave, an amplitude limiting unit that limits the amplitude of the PSK-modulated reception IF signal, and a local signal that has the same frequency as the IF signal in the amplitude-limited reception IF signal. The signal is subjected to complex multiplication, the in-phase component after complex multiplication and the quadrature component after complex multiplication are low-pass filtered, and output as a baseband in-phase signal and a baseband quadrature signal, respectively. The band quadrature signal is sampled with the recovered clock, and the baseband in-phase data and the Sampling unit that outputs as squadrature quadrature data, baseband in-phase data, and baseband quadrature data that undergoes polar coordinate conversion, and the polar coordinate conversion data that outputs as baseband phase data. The data determination unit latches phase data, determines demodulated data from the latched phase data, and outputs the demodulated data.

Further, a demodulator according to the next invention outputs a regenerated symbol clock phase-synchronized with the transmission timing of the transmitting side, and a fixed clock having the same frequency as the symbol rate,
Alternatively, a timing recovery circuit that generates a recovered symbol clock from a local sine wave having the same frequency as the symbol rate, an amplitude limiting unit that limits the amplitude of the PSK-modulated reception IF signal, and an IF
A quadrature detector that performs a complex multiplication of a local signal having the same frequency as the signal, low-pass filters the in-phase component after the complex multiplication and the quadrature component after the complex multiplication, and outputs them as a baseband in-phase signal and a baseband quadrature signal, respectively. , Baseband in-phase signal and baseband quadrature signal,
A sampling unit that samples at the rising and falling edges of the recovered symbol clock and outputs as baseband in-phase data and baseband quadrature data, respectively.
The baseband in-phase data and the baseband quadrature data are converted to polar coordinates, and the polar coordinate conversion part that outputs the data after polar coordinate conversion as baseband phase data, and the regenerated symbol clock are used to latch the baseband phase data and the phase after latching. The data determination unit determines the demodulated data from the data and outputs the determined data.

[0039]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. In the first embodiment of the present invention, a TDM that performs high-speed wireless transmission with a symbol rate of 50 Mbaud.
A demodulator for an A (Time Division Multiple Access) communication system will be described. The demodulator receives the QPSK-modulated IF signal and demodulates the data. In addition, the timing recovery circuit in the demodulator uses a fixed clock that is twice the symbol rate as the operation clock, and uses the BTR pattern at the beginning of each burst to recover the recovered symbol clock that is synchronized with the reception timing.

FIG. 1 is a diagram showing the structure of a demodulator including the timing recovery circuit 7A according to the first embodiment. In the figure,
21a and 21b are mixers, 22 is a π / 2 phase shifter, and 23
Reference numerals a and 23b are low-pass filters, 7A is a timing reproduction circuit, and 8A is a fixed clock oscillator for timing reproduction having a frequency twice the symbol rate (the same frequency as the bit rate). The same parts as those in the prior art are designated by the same reference numerals. Further, FIG. 3 shows a configuration of the timing reproduction circuit 7A of the first embodiment. In the figure, 71A is a symbol frequency component generation unit, 711A is a phase difference unit, and 72A.
Is a multiplication unit, 72f is a D flip-flop, 73A is a low-pass filtering unit, 73e is a random walk filter, 74A is a phase control unit, 75 is a reproduced symbol clock generation unit, 76 is a phase information memory, and 77 is a filter information memory. . 5 is a diagram showing the configuration of the phase controller 74A in the timing reproduction circuit of FIG. In the figure, 741 is a delay time setting signal calculation unit, 743 is a clock phase shift unit, 741a is an adder, and 741c is a D flip-flop. Further, FIG. 6 shows another phase control unit corresponding to the phase control unit 74A of FIG. 5, and shows a configuration of the phase control unit 74A having a function of avoiding a malfunction caused by a delay error of the delay element. In the figure, 741A is a delay time setting signal calculation unit, 742 is a corrected delay value calculation unit, 743A is a clock phase shift unit, and 741b is a subtractor. Further, FIG. 7 shows a configuration of the clock phase shifter 743 of the first embodiment.
In the figure, 7431 is a clock selection signal generation unit, 7432 is a delayed clock group generation unit, 7433 is a clock selection unit, and 7
432a, 7432b, 7432c, 7432d, 74
32e is a delay element, 7432f, 7432g, 7432
h, 7432i, 7432j, 7432k are buffers,
7433a, 7433b, 7433c, 7433d, 7
433e and 7433f are D flip-flops, 7433
g, 7433h, 7433i, 7433j, 7433
k and 7433l are AND gates, and 7433m is an OR gate.

Next, the operation of the demodulator of the first embodiment will be described. First, the overall operation will be described with reference to FIG. The QPSK-modulated IF signal is amplitude-limited by the limiter 1 as in the conventional example, and the quadrature detection circuit 2
Entered in. The quadrature detection circuit 2 performs quadrature detection on the amplitude-limited IF signal using the same local signal as the center frequency of the IF signal from the quadrature detection local oscillator 3 in the same way as in the conventional example, and performs baseband synchronization. Obtain a phase signal and a baseband quadrature signal. The quadrature detection circuit 2 multiplies the amplitude-limited IF signal and the quadrature detection local signal by the mixer 21a, removes harmonic components by the low-pass filter 23a, and outputs a baseband in-phase signal.
The quadrature detection local signal that has been phase-shifted by π / 2 by the phase shifter 22 and the amplitude-limited IF signal are multiplied by the mixer 21b, the harmonic component is removed by the low-pass filter 23b, and the baseband quadrature signal is output. .

In the conventional example, a baseband in-phase signal is generated by using a reproduction quadruple clock having a frequency four times the symbol rate.
Although the baseband quadrature signal is sampled, the sampling unit 4 in the first embodiment samples the baseband in-phase signal and the baseband quadrature signal by using a reproduction double clock having a frequency twice the symbol rate. Then, the double oversampled data after AD conversion is output as baseband in-phase data and baseband quadrature data. The polar coordinate conversion circuit 5 performs polar coordinate conversion on the baseband in-phase data and baseband quadrature data that are oversampled at twice the symbol rate, and outputs the data after polar coordinate conversion as baseband phase data.
The data determination circuit 6 extracts the phase data at the Nyquist point from the baseband phase data obtained at a timing twice the symbol rate using the reproduced symbol clock, and uses the extracted phase data at the Nyquist point for differential detection. And outputs demodulated data. The timing reproduction circuit 7A uses the baseband phase data from the sampling circuit 4 obtained at the timing of twice the symbol rate, and controls the phase of the reproduction double clock so as to sample the Nyquist points of the baseband in-phase and quadrature signals. Then, the phase of the reproduced symbol clock is controlled so that the data determination circuit 6 extracts the phase data at the Nyquist point. The timing recovery circuit 7A operates with a fixed clock having a frequency twice the symbol rate output from the timing recovery fixed clock oscillator 8A, and performs clock phase control at intervals of about 1/16 symbol step.

Next, the operation of the timing reproduction circuit 7A of the first embodiment will be described with reference to FIG. The symbol frequency component generation unit 71A uses the oversampled baseband phase data θ (iT
/ 2), the data sequence Δθ (iT / 2) including the symbol frequency component at the timing twice the symbol rate.
Is generated by the following equation (8). However, i =
It is {1, 2, 3, ...}. Δθ (iT / 2) = min {| θ (iT / 2) −θ ((i-1) T / 2) |, 2π− | θ (iT / 2) −θ ((i-1) T / 2 ) |} (8) The symbol frequency component generator 71A includes a phase difference circuit 71
1A and a data conversion circuit 712B, and the phase difference circuit 711A performs the difference of θ (iT / 2) −θ ((i-1) T / 2) in the equation (8). This processing can be realized by a simple circuit that subtracts the phase data delayed by the D flip-flop 711a for one sample time from the current phase data by using the subtractor 711c. In the data conversion circuit 712,
Similar to the conventional method, the processing of the above equation (8) is realized by the absolute value conversion circuit 712a and the phase data conversion circuit 712b, and the data series Δθ (i
T / 2) is obtained.

The multiplication unit 72A calculates the multiplication value M (jT) for one symbol by Δθ (iT / 2) including the frequency component fs on the transmission side and the symbol frequency (fs ■) on the receiver side as follows. It is obtained by the equation (9). M (jT) is j (= 1,
2, 3, ...) The multiplication value at the symbol eye.

[0045]

[Equation 3]

The above cos2πfs (iT / 2) is -1,
Since it is a repetition of 1, -1,1, ..., M (j
T) can be easily obtained by the following equation (10). M (jT) = Δθ (2jT / 2) −Δθ ((2j-1) T / 2) (10) M (jT) is the D that operates at the rising edge of the reproduction double clock.
The current Δθ (iT / 2) is subtracted from the Δθ (iT / 2) latched by the flip-flop 72a by the subtractor 72c, and the data after the subtraction is latched by the D flip-flop 72f operating at the rising edge of the reproduced symbol clock. Can be easily obtained.

By averaging M (jT), it is possible to determine whether the phase of the symbol timing on the receiving side is advanced or delayed. This will be described below. Symbol frequency component sin2 included in Δθ (t)
Considering only πfs (t) + A, the processing performed by the D flip-flop 72a and the subtractor 72c is 1
/ 2 symbol difference. This difference value Q (t) includes 2sin (2πfs) as shown in the following equation (11).
The symbol frequency component of (t) with the offset A removed is included. Q (t) = (sin2πfs (t) + A) − (sin (2πfs (t−T / 2)) + A) = (sin2πfs (t) + A) − (sin2πfs (t) −π) + A) = (sin2πfs ( t) + A)-(-sin2 [pi] fs (t)) + A) = 2sin (2 [pi] fs (t)) (11) M (jT) is obtained by sampling this Q (t) at the symbol frequency timing on the receiving side. Time t = jT
When Q (t) is sampled at the timing of (j = 1, 2, 3, ..., T; symbol period), the average value of M (jT) becomes zero. When Q (t) is sampled at the timing of time jT <t <3jT / 2, the average value of M (jT) shows a positive value, and Q (t) at the timing of time 3jT / 2 <t <2jT. ) Is sampled, M (j
The average value of (T) shows a negative value. Therefore, the averaged M
By determining whether the (jT) is positive or negative, it is possible to determine whether the timing phase is advanced or delayed.

FIG. 8 shows Q (t) and the operation of the timing reproduction circuit 7A of the first embodiment. FIG. 8 is an example of phase data of a random pattern, in which the dotted line indicates the phase data, and ■ indicates the Nyquist point. In this embodiment, since the modulation method is the QPSK modulation method, the phase fluctuation at each Nyquist point is ± 90 (degree), 180 (de)
green) and 0 (degree). The Q (t) generated from the phase data of this random pattern is shown in FIG.
Is indicated by the solid line. As is clear from the figure, when the initial phase of the reproduced symbol clock is advanced from the Nyquist point position as shown in the upper timing, Q (t) (=
M (jT) is “positive”. When the initial phase of the regenerated symbol clock is delayed from the Nyquist point position as shown in the lower timing, Q (t) (= M (j
T)) is "negative". It can be seen that the absolute value of this Q (t) data increases when the phase fluctuation of the baseband phase data is large. Therefore, the timing reproduction circuit 7A can perform high-speed pull-in on a fixed pattern in which the fluctuation of the baseband phase data is large.

Next, the low-pass filtering unit 73A
Averages this M (jT) and outputs the averaged M (jT) as a timing phase error signal. In the present embodiment, a random walk filter 73e is used for averaging and U is used to advance the phase as a timing phase error signal.
The Pj signal and the DWj signal whose phase is delayed are output. An example of the operation flow of the random walk filter 73e
It shows in FIG. The random walk filter 73e is composed of, for example, an up / down counter and a comparator. When the value of the up / down counter is Rj (j = 1,2,3, ...), the operation starts from Rj = 0 first. Further, as shown in Expression (12), M (jT) determined for each symbol by {-1, 0, 1} is input as LEADj in the operation flow of FIG. LEADj = 1 (M (jT) <0) LEADj = -1 (M (jT)> 0) LEADj = 0 (M (jT) = 0) (12) As shown in the operation flow of FIG. When 73j continues to operate and Rj becomes N, a logical "0" UPj signal for advancing the clock phase is supplied to Rj-
When it becomes N, D of logic "0" that delays the clock phase
The Wj signal is output. After either signal output,
Rj is reset to "0" and one symbol time Rj = 0
Is maintained. Further, when Rj is in the range of (-N <Rj <N), the logic "1" which does not give the phase control command is given.
UPj and DWj of logic "1" are output. As can be seen from FIG. 9, the band of the random walk filter is obtained by the filter constant N. Therefore, if high-speed pull-in is desired, N should be set small, and if low phase jitter after pull-in should be realized, N should be set high. In the present embodiment, the case where a random walk filter is used for the low-pass filtering unit 73A is taken up, but the low-pass filtering unit 73A may use a moving average circuit, an infinite impulse response circuit, M (jT ) Is averaged to remove noise components and the like.

Next, the operation of the phase controller 74A will be described. Similarly to the conventional phase control unit 74, the phase control unit 74A controls the phase of the regenerated double clock having a frequency twice the symbol rate at a sufficiently fine phase control interval of about 1/16 of the symbol period. When the UPj signal of logic "0" is input, the phase control unit 74A advances the phase of the clock of double reproduction by about 1/16 of the symbol period, and when the DWj signal of logic "0" is input, double reproduction is performed. The clock phase is delayed by about 1/16 of the symbol period. However, the difference between the phase control unit 74A and the conventional phase control unit 74 is that a fixed clock having a frequency twice the symbol rate is input (the conventional phase control unit 74 has a symbol rate 16 times the symbol rate). Needed a frequency clock). The operation of the phase controller 74A will be described below with reference to FIG. First, the delay time setting signal calculation circuit 741
Accumulates the timing phase error signal during significant data reception of the burst signal. In the present embodiment, when the UPj signal of logic “1” is input, “−1” is set, and when the DWj signal of logic “1” is input, “1” is set as the timing phase error value Ej. It is input to the signal calculation circuit 741. When the circuit of the delay time setting signal calculation circuit 741 is configured by an m-bit data bus, the delay time setting signal Kj which is the output of the delay time setting signal calculation circuit 741 is obtained by the following equation (13). Kj = mod (Kj-1 + Ej, 2m) (13) m is a value that satisfies the following expression (14), where T / Z (T; symbol period) is the phase control interval of the recovered clock. m = log2 (Z / 2) (14) In this case, since the design is performed with Z = 16, m is calculated by the formula (1
The value “3” that satisfies 4) is set. Therefore, when m = 3, Kp changes to 7,6,5, ..., 1,0,7,6, ... When the UPj signal of logic "1" is continuously input during the reception of significant data. To do. Conversely, if the DWj signal of logic "1" is continuously input, Kj changes to 7,0,1,2, ... 6,7,0,1,2 ... The Kj having a value of 0 to 7 is input to the clock phase shift unit 743.

Next, the operation of the clock phase shifter 743 will be described with reference to FIG. First, the delay clock group generation circuit 7432 generates eight clocks having different phases from a fixed clock having a frequency twice the symbol rate.
The frequency of each of the eight clocks is twice the symbol rate. Further, each clock is T / 16 as shown in FIG.
Seven delay elements for delaying the symbol time are connected in series, and an output clock of each delay element and a fixed clock as an input are amplified by a buffer and generated. The clock selection signal generation circuit 7431 generates an 8-bit clock selection signal Sj from the delay time setting signal Kj by the following equation (15). Sj = 2Kj + 2Kj-1 (15) The clock selection circuit 7433 selects and outputs one of the eight clocks by the clock selection signal Sj. The clock selection unit 7433 receives the clock selection signal Sj.
The circuit is configured as shown in FIG. 7 so that the phase of the output clock is not disturbed at the time of switching. As shown in FIG. 7, data of the d-th bit from the lower order of the clock selection signal Sj (where 1 ≦ d ≦
2m) is re-timed at the falling edge of the fixed clock that has passed through (d-1) delay elements, and the logical product of each re-timed signal and each clock that re-timed the same is ANDed. Ask at the gate. Further, by obtaining the logical sum of the outputs of the AND gates by the OR gate, the reproduced double clock can be obtained.

FIG. 10 is a timing chart showing an operation example of the clock phase shift circuit 743 when the UP signal of logic "1" is generated and Kj is switched from "3" to "2". The clock output from the buffer 7432f is the input fixed clock amplified by the buffer, the buffer 732.
The clock output from 432g is the buffer 7432.
The clock output from f is delayed by the delay element 7432a.
The clock output from the buffer 7432h is delayed by / 16, and the clock output from the buffer 7432g is delayed by T / 16 by the delay element 7432b. As shown in FIG. 10, when Kj is "3" and the UPj signal indicates a logical "0" in the symbol period width, "-1" is input to the delay time setting circuit 741. Changes from "3" to "2". At this time, Sj changes from “8” → “12” → “4” at the timing shown in FIG. 10 according to the equation (15). Since each bit of Sj is retimed at the falling edges of the eight clocks, the signal output from the buffer 7432g that is retimed at the falling edge,
That is, the output of the register 7433b becomes the timing shown in FIG. Further, the signal output from the buffer 7432h that is retimed at the falling edge of the clock, that is, the output of the register 7433b has the timing shown in FIG. The signals output from the other registers are all logical "0" (not shown). Therefore, AND74
The output of 33h and the output of AND7433i are shown in FIG.
The timings shown in FIG. 4 are reached, and all the other AND outputs become logic "0" (the output of logic "0" is not shown). Since the reproduction double clock takes the logical sum of all these AND outputs, as shown in FIG. 10, the rising point is advanced by T / 16 (symbol). If the clock is selected without performing each of the above processes, when the phase of the reproduction double clock is delayed, as in the timing shown in FIG.
The phase may be disturbed at the clock switching point, which causes a clock cycle slip. By performing each of the above operations, even when Kj is switched asynchronously with each of the eight fixed clocks, or when the value changes from "7" to "0" or from "0" to "7", the phase of the output clock changes. There is no disturbance, and it is possible to reliably control the reproduction double clock phase according to the change of Kj.

From the above, the following equation (16a) is established for Kj and the phase difference Δp (radian) from the input fixed clock of the reproduction double clock output from the clock selection circuit 7433. Δp = π × Kj / 2 (m−1) (16a) In this embodiment, the symbol rate is 50 Mbaud, and the clock phase control interval is the symbol period T.
Since it is 1/16 of the delay clock group generation circuit 7432 shown in FIG. 7, the delay amount of each delay element is 1 / (16
× 50 × 106) (second) = 1.25 (nan
o-second).

However, the delay time of this delay element may deviate from the set value due to temperature or the like. In that case, the configuration of the phase controller shown in FIG. 5 may malfunction. When the error time of the delay amount of this one delay element is α, Kj and the phase difference Δp (radian) from the input fixed clock of the reproduction double clock output from the clock selection circuit 7433 are given by (17a) is established. Δp = mod ((π / 2 (m-1) + 4απ / T) × Kj, 2π) (17a) FIG. 12 shows an example of Kj vs. Δ when α is a parameter.
The p characteristic is shown. It can be seen that the phase control malfunctions as the absolute value of α increases. For example, consider the case where Kj is changed to 6,7,0,1,2, ... To delay the phase. When α = 0, Δp is 1.5π, 1.75π, 0,0.25
.., .pi., 0.5.pi., etc., the phase is delayed at equal intervals of T / 16. However, when α = 1/50, Δp is 1.98π,
When Kj changes from "7" to "0" such as 0.31π, 0, 0.33π, 0.66π, ..., The phase advances from 0.31π to 0. Conversely, when α = -1 / 50, Δp is 1.
02π, 1.19π, 0, 0.17π, 0.34π, ... When Kj changes from “7” to “0”, the phase changes from 1.19π to 0.
Will be suddenly delayed. As described above, the phase control unit of FIG. 5 can be realized with a very simple circuit configuration, and is effective when the absolute value of α is a small value that does not disturb the phase control operation. When the value is large, when the Kj rapidly changes from "0" to "2m-1" or from "2m-1" to "0", the phase control operation is disturbed and the timing phase jitter increases. Resulting in.

When the absolute value of α is large as described above, the phase controller 74A is constructed as shown in FIG. However,
The phase control unit of FIG. 6 is effective only when a meaningless signal (for example, a signal containing only a noise component or a preamble pattern signal) exists between the significant burst signals in the TDMA communication system as in this embodiment. It is something. Or later,
The phase controller of FIG. 6 will be described. In the phase control unit of FIG. 6, when α = 0 in Expression (17), Δp of Kj
Paying attention to the fact that Δp of Kj ± 8 coincides with each other, and during a significant burst signal reception, a sudden change in the value of Kj that causes disturbance in the phase control operation is not given, and meaningless signal reception is performed. Only at, the rapid change from Kj to (Kj ± 8) is given. As a result, a stable phase control operation is realized during the reception of a significant burst signal. Hereinafter, each operation will be described.

First, the delay time setting signal calculation circuit 74
1A is during the significant data reception of the burst signal,
The timing phase error signal is accumulated, and the value of the correction delay value calculation circuit 742 is subtracted from the accumulated value during meaningless data reception of the burst signal. When the circuit of the delay time setting signal calculation circuit 741 is configured by an n (= m + 1) -bit data bus and the value of the correction delay value calculation circuit 742 is Hj, the delay time setting signal output from the delay time setting signal calculation circuit 741A is set. The signal Kj is obtained by the following equation (18). Kj = mod (Kj-1 + Ej-Hj, 2n) (18) The value of n is T / Z (T;
Symbol period), the value satisfies the following expression (19). n ≧ log2Z (19) In this case, since n = 16 is designed with Z = 16,
The value "4" that satisfies 9) is set. During significant data reception of the burst signal, Hj always outputs "0". Therefore, when m = 4, if the UPj signal of logic "1" is continuously input during the reception of significant data, Kj becomes 15,1.
It changes to 4,13, ..., 1,0,15,14, .... Conversely, logical "1"
When the DWj signal of is continuously input, Kj becomes 15,0,1,2,
… Changes to 14,15,0,1,2…. Kj having a value of 0 to 15 is input to the clock phase shift circuit 743A.

The clock phase shift circuit 743A can be easily realized by basically the same circuit configuration as the clock phase shift circuit 743 of FIG. That is, the clock selection signal generation circuit 7431
(FIG. 7) shows the delay time setting signal Kj according to the equation (15).
16-bit clock selection signal Sj is generated from the delay clock group generation circuit 7432, and the delay clock group generation circuit 7432 is connected in series.
16 clocks are generated from the delay elements, and the clock selection circuit 7433 selects one from the 16 clocks. The clock selection circuit 7433 that selects one of the 16 clocks is d from the lower order of the clock selection signal Sj.
The data of the bit (however, 1≤d≤16) is (d-
1) Retiming is performed at the falling edge of the fixed clock that has passed through the delay elements, and each of the retimed signals,
The logical product with each clock that retimed it is 1
It is obtained by 6 AND gates, and the logical sum of 16 AND gate outputs is obtained by an OR gate. From the above, when α = 0, Kj is 0, 1, 2, ... 14, 1
When counting up to 5,0, the phase of the reproduction double clock from the fixed clock changes from 0 to 4π (that is, rotates twice).

Next, the correction delay value calculation circuit 742 starts its operation when a meaningless signal is received by the burst gate signal, and the processing of the following formula (20) is performed for a certain threshold value ε (≦ 4). To Kj. Kj ← Kj + 2 ^n-1 (Kj ≦ ε) Kj ← Kj-2 ^n-1 (Kj ≧ 15−ε) Kj ← Kj (ε <Kj <15−ε) (20) That is, if n = 4, correct The delay value calculation circuit 742 outputs the output value Hj by the following equation (21) when a meaningless signal is received, and the delay time setting signal calculation circuit 741 is output.
By giving it to the subtractor 741b in A, the processing of Expression (20) is realized. Hj = −8 (Kj ≦ ε) Hj = + 8 (Kj ≧ 15−ε) Hj = 0 (ε <Kj <15−ε) (21) In the phase control unit, the variation range of Kj at the time of burst signal reception is , "8" or less (T / 2 or less in time) is effective. When the variation range of Kj at the time of receiving the burst signal is q> 8, the value of n may be designed so as to satisfy the equation (22). n ≧ log2 (2q) (22) Next, returning to FIG. 3, the reproduction symbol clock generation circuit 75 divides the reproduction double clock output from the phase control unit 74A by two to obtain the reproduction symbol clock. To generate.

The series of operations up to this point will be described with reference to FIG. 8. When the initial phase of the reproduced symbol clock is advanced from the Nyquist point as shown in the upper part of FIG. 8, sampling is performed at the rising edge of the reproduced symbol clock. Q
Since (t) (= M (jT)) is “positive”, READ
j = -1 is input to the random walk filter 73e. The random walk filter 73e averages this and outputs a DWj signal of logic "1" which delays the phase,
The phase control unit 74A delays the phase of the reproduction double clock by the DWj signal of logic "1". Since the regenerated symbol clock is generated by the regenerated symbol clock generation unit 75 by dividing the regenerated double clock into two, the phase of the regenerated symbol clock is also delayed. By this series of operations, after several to several tens of symbols, the rising point of the reproduced symbol clock and the position of the Nyquist point match (as shown in FIG. 8, for example). When the initial phase of the reproduced symbol clock is delayed from the Nyquist point as shown in the lower part of FIG. 8, Q (t) (= M (jT)) sampled at the rising edge of the reproduced symbol clock is “negative”. Therefore, LEADj = 1 is input to the random walk filter 73e. The random walk filter 73e averages this and logically advances the phase by "1".
, And the phase control unit 74A advances the phase of the reproduction double clock by the UPj signal of logic "1". The regenerated symbol clock is generated by the regenerated symbol clock generator 75 by dividing the regenerated double clock into two, so that the phase of the regenerated symbol clock advances at the same time. By this series of operations, after several to several tens of symbols, the rising point of the reproduced symbol clock and the position of the Nyquist point match (as shown in FIG. 8, for example).

When the burst signal is received, if the phase information and the filter information are stored at the end of a burst and the information is loaded at the beginning of the next burst, the timing recovery circuit 7A does not need to be pulled in for each burst signal and operates. Is more stable. In this case, based on the timing of the burst gate signal, the phase information memory 76 determines that the phase control unit 74A
The Kj value of is stored at the end of the burst, and the phase control unit 74A
Loads Kj of the phase information memory 76 at the beginning of the next burst. Further, based on the timing of the burst gate signal, the filter information memory 77 stores the Rj value in the random walk filter 73e at the end of the burst,
The random walk filter 73e loads Rj of the filter information memory 77 at the beginning of the next burst. In the first embodiment, the number of phase control steps is 1/16 of the symbol period T, but the number of phase control steps is Z
It is sufficient that the T / Z symbol step satisfying ≧ 16 is a sufficiently small value.

As described above, since the demodulator shown in the first embodiment also operates by using the received PSK signal whose amplitude is limited as in the conventional example, it can be configured by a simple circuit having a limiter in the preceding stage. Therefore, the circuit can be downsized. Further, since the demodulator shown in the first embodiment has a feedback type configuration that performs AD conversion at the timing of the reproduction double clock, it must operate at twice the symbol rate, which is half the sampling rate of the conventional example. Therefore, low power consumption can be realized. Further, while the conventional timing reproduction circuit 7 inputs a fixed clock of x times the symbol rate and performs the phase control step of 1 / x of the symbol period, the timing shown in the first embodiment The reproducing circuit 7A inputs a fixed clock that is twice the symbol rate, and stably realizes a phase control step interval (1/16 or less of the symbol period) that is sufficiently small with respect to the symbol period. Therefore, the timing recovery circuit 7A can realize low power consumption and facilitate circuit design especially when the symbol rate is high such as in a high-speed wireless transmission system.
Further, the timing reproduction circuit 7A can perform high-speed pull-in on a data pattern having a particularly large phase fluctuation, by using the baseband phase data oversampled by the symbol frequency generation unit 71A at twice the symbol rate. .

Embodiment 2. FIG. 2 is a diagram showing the configuration of the demodulator of the second embodiment, in which the operation clock of the timing recovery circuit is operated at the frequency of the symbol rate. In the figure, 4A is a sampling circuit, 4c and 4d.
Is an AD converter, 4e is an inverter, 5a is a polar coordinate conversion circuit, 7B is a timing recovery circuit, and 8B is a fixed clock oscillator having a symbol rate frequency. 4 is a block diagram of the timing recovery circuit according to the second embodiment, where 71B is a symbol frequency component generation unit, 72B is a multiplication unit, 73A is a low-pass filtering unit, 74B is a phase control unit, and 76 is phase information. The memory 77 is a filter information memory. The symbol frequency generator 71B further includes a phase difference circuit 711B and a data conversion circuit 712A,
It consists of 712B. 711d and 711e are D flip-flops, 711f and 711g are subtractors, and 711
h is an inverter, 72c is a subtracter, and 72f is a D flip-flop.

In the first embodiment, the sampling circuit 4 is composed of two AD converters that sample at the rising edge of the reproduction double clock, but in the second embodiment, as shown in FIG. As a configuration of a sampling circuit 4A composed of two AD converters 4a and 4b for sampling at 2 and two AD converters 4c and 4d for sampling at the falling edge, oversampling at twice the symbol rate is realized. The sampling operation at the falling edge can be realized by inputting the reproduced symbol clock to the inverter 4e to invert it and inputting the inverted reproduced symbol clock to the AD converters 4c and 4d. As shown in FIG. 2, the coordinate conversion circuit 5 is used for data sampled at the rising edge of the reproduced symbol clock, and a coordinate conversion circuit 5a for data sampled at the falling edge of the reproduced symbol clock is newly provided. Further, the fixed clock having the frequency of the symbol rate output from 8B is input to the timing recovery circuit 7B.

In the timing recovery circuit 7B, the symbol frequency component generator 71A and the multiplier 72A, which perform bit rate serial processing, perform equivalent processing by symbol rate parallel processing as shown in FIG. The symbol frequency component generation unit 71B and the multiplication unit 72B are changed. The symbol frequency component generation unit 71B samples the baseband phase data sampled at the rising edge of the reproduced symbol clock at the D flip-flop 711d at the falling edge of the reproduced symbol clock, and samples at the falling edge of the reproduced symbol clock at the D flip-flop 711e. The generated baseband phase data is sampled at the rising edge of the reproduced symbol clock. The subtractor 711f subtracts the baseband phase data sampled at the falling edge from the output of 711d,
1g subtracts the output of 711d from the output of 711e.
The first data conversion circuit 712A performs the same data conversion as the data conversion circuit 712 of the first embodiment on the 711f output. In addition, the second data conversion circuit 712B
Performs the same data conversion as the data conversion circuit 712 of the first embodiment on the 711g output. Therefore, by the above processing, the first data conversion circuit 712A output Δθa (j
T) can be expressed by Expression (8a), and the output Δθb (jT) of the second data conversion circuit 712B can be expressed by Expression (8b). Δθa (jT) = min {| θ (jT-T / 2) −θ (jT) |, 2π− | θ (jT-T / 2) −θ (jT) |} (8a) Δθb (jT) = min {| Θ (jT-T) −θ (jT-T / 2) |, 2π− | θ (jT-T) −θ (jT-T / 2) |} (8a)

The multiplication section 72B calculates Δ from this Δθa (jT).
If θb (jT) is subtracted by the subtractor 72c, the above equation (1
The value M (jT) obtained from 0) is obtained. The reproduction symbol clock generation unit 75 of FIG. 3 is not necessary in FIG. 4, and the reproduction clock output from the phase control unit 7B becomes the reproduction symbol clock. Next, changes from the phase / phase control unit 74A for realizing the phase control unit 74B will be described. In the control unit 74B, the delay time setting signal calculation circuits 741 and 7 in the phase / phase control unit 74A of the first embodiment are included.
The number of bits m and n of the data bus in 41A is doubled, and the output Hj of the correction delay value calculation circuit 742 is doubled. Further, a fixed clock having a symbol rate is input to the clock phase shift circuit, and the number of clocks generated by the delay clock group generation circuit 7432 is doubled by doubling the delay elements. Further, the clock selection circuit 7433 doubles the number of input clocks.

With the above changes, the second embodiment can reduce the frequency of the input clock from the frequency twice the symbol rate to the frequency of the symbol rate. Therefore, the operating frequency of the demodulator of the second embodiment is The power consumption can be reduced to half that of the demodulator of the first embodiment, and the power consumption can be further reduced, and the demodulator can be easily formed into a gate array using CMOS.

Embodiment 3. FIG. 13 is a diagram showing a configuration of a phase control unit of a timing reproducing circuit which can be applied to communication in which a significant signal state continuously continues such as FDM communication and can perform stable phase control. This can be realized by replacing the phase control unit of the timing reproduction circuit in FIG. 3 with the phase control unit of the third embodiment.

In FIG. 13, 743B is a first clock phase shift circuit, 743C is a second clock phase shift circuit, and 743C.
4 is a clock switching determination circuit, 745 is a cumulative addition circuit,
746 is a clock selection circuit, 747 is a clock phase comparison circuit, 748 is an averaging circuit, 749 is an error value accumulation circuit,
749a is an adder. 14 is a diagram showing a configuration example of the clock phase shift circuit 743B in FIG. 13, where 743E is a first clock selection circuit and 743F is a second clock selection circuit.

In the first embodiment, the abrupt phase change of the reproduced clock from Kj to (Kj ± 8) is given only when a meaningless signal is received. However, since significant data is always received. , Kj → (Kj ± 8), a rapid phase change of the reproduced clock cannot be given. Therefore, the phase control unit according to the third embodiment sets the addition of the fixed value of "± 8" to the variable value of "± y" to find y that does not give a sudden phase change of the reproduced clock, and Kj → ( Kj ±
The phase control to y) is performed. The operation of the phase control unit will be described with reference to FIG. The delay time setting signal calculation circuit 741A accumulates the input timing phase error signal and adds the output value of the adder 749a from the accumulated value. When the circuit of the delay time setting signal calculation circuit 741A is configured by an n-bit data bus and the output value of the adder 749a is y, the first delay time setting signal K1j that is the output of the delay time setting signal calculation circuit 741A is It is obtained by the following equation (23). K1j = mod (K1j-1 + Ej + y, 2n) (23) Further, the cumulative addition circuit 745 is composed of a cumulative addition circuit configured by an n-bit data bus having Ej as an input.
The cumulative addition circuit 745 performs cumulative addition of the following equation (24) and outputs the added value as K2j. K2j = mod (K2j-1 + Ej, 2n) (24)

The first clock phase shift circuit 743B and the second clock phase shift circuit 743C are realized by the same circuit configuration as the clock phase shift circuit 743A described in the first embodiment, and have a frequency twice the symbol rate. Input fixed clock. The first clock phase shift circuit and the second clock phase shift circuit can also be configured by the circuit shown in FIG. As shown in FIG. 14, since the delay clock group generation circuit 7432 is shared,
The circuit scale can be reduced. First clock selection circuit 74
3E and the second clock selection circuit 743F can be realized by the same circuit configuration as the clock selection circuit 743A.
In the first clock phase shift circuit 743B, when the error time of the delay amount of the delay element is α, K1j and the phase difference Δp1 (radian) from the input fixed clock of the reproduction double clock output from the clock selection circuit are obtained. Holds the following equation (25a). Δp1 = mod ((π / 2 (n-1) + 4απ / T) × K1j, 2π) (25a) Similarly, in the second clock phase shift circuit 743C, when the error time of the delay amount of the delay element is α, The following equation (26) is established between K2j and the phase difference Δp2 (radian) from the input fixed clock of the reproduction double clock output from the clock selection circuit. Δp2 = mod ((π / 2 (n-1) + 4απ / T) × K2j, 2π) (26a) Therefore, in the case of α = 0, n = 4, if the relationship of k1j = K2j ± 8 holds. , Δp1 = Δp2.

Next, the clock phase comparison circuit 747, the averaging circuit 748, and the error value accumulating circuit 7 in this phase control unit.
49, the adder 749a, even if α is not "0",
The relationship between K1j and K2j is made variable such that K2j = K1j ± y, y is obtained so that Δp1 and Δp2 substantially match, and this is given to the delay time setting signal calculation circuit 741A. This series of operations will be described with reference to the timing chart of FIG. As shown in FIG. 15, it is assumed that the first delay clock is delayed in phase with respect to the second delay clock. In this case, the value obtained by sampling the second delay clock at the rising edge of the first delay clock becomes logic "1". When the phase of the first delayed clock is advanced with respect to the second delayed clock, the value obtained by sampling the second delayed clock at the rising edge of the first delayed clock becomes logical "0". Therefore, the clock phase comparison circuit 747 samples the second delay clock at the rising edge of the first delay clock, and if the sampled value is logic "1", PE = -1.
If the sampling value is logic "0", PE = 1 is output. The averaging circuit 148 averages the PEs and outputs a logic "1" when the average value is positive and outputs a logic "-1" when the average value is negative. For the averaging, the above-described random walk filter, moving average filter, or the like may be used. In addition, the averaging circuit 148
Is unnecessary if the sampling accuracy of the clock phase comparison circuit 747 in the previous stage is high. FIG. 15 shows an averaging circuit 748.
Shows the case where is omitted. Error value accumulation circuit 749
Performs cumulative addition of PE and outputs the cumulative addition result. When the averaging circuit 148 is included, the error value accumulating circuit 749 is
The outputs of the averaging circuit 148, "1" and "-1", are cumulatively added. Since the adder 749a adds this cumulative addition value and "8", y changes from "8" to "7" at time D. Therefore, the output of the delay time setting signal calculation circuit 741A has a relation of "K1j + 8" to "K1j + 7".
At time E in FIG. 15, the phase of the first delayed clock advances, and the phase difference from the second delayed clock becomes “0”.
In the example of FIG. 15, when K2j is "9", K1j changes from "1" to "0".

If the following equation (27) is satisfied, the clock switching determination circuit 744 in this phase control unit:
If the first delay clock is not satisfied, an instruction to select the second delay clock as the reproduction double clock is issued. min {K1j, 15− K1j}> min {K2j, 15− K2j} (27) The clock selection circuit 746 includes the clock switching determination unit 74.
In response to the command from 4, the clock is selected and output as a reproduction double clock. The clock selection circuit 746
The circuit configuration is the same as that of the clock selection circuit 7433 of the first embodiment, and the clock phase is not disturbed even when the clock selection signal is asynchronously switched. By the above processing, when the clock is selected, the disturbance of the phase of the double reproduction clock does not occur even when α is not “0”.

From the above, in the third embodiment, as in the first embodiment, the timing recovery circuit inputs the fixed clock twice the symbol rate, and the phase control step interval is sufficiently small with respect to the symbol period. (1/16 or less of the symbol period) is stably realized. Therefore, the timing recovery circuit of the third embodiment can realize low power consumption and easy circuit design especially when the symbol rate is high such as in a high-speed wireless transmission system. In addition, the timing recovery circuit according to the third embodiment includes the symbol frequency generator 7
1A enables high-speed pull-in to be performed on a data pattern having a particularly large phase variation, by using baseband phase data oversampled at twice the symbol rate. Further, the timing recovery circuit according to the third embodiment has the phase control unit according to the third embodiment, so that even when a significant signal receiving state is continuously continued, such as in FDMA communication, the recovered clock is generated. It is possible to always realize a stable phase control step without causing a sudden phase change in the phase.

Fourth Embodiment By the way, the demodulator having the phase control unit of the third embodiment in which the input fixed clock has the frequency of the symbol rate can also be realized by a simple circuit modification from the third embodiment. Below, in order to operate the demodulator of the third embodiment with a fixed clock of the symbol rate,
The changes from the third embodiment will be described.

The structure of the demodulator in the fourth embodiment is the same as that of the second embodiment shown in FIG. The configuration of the timing recovery circuit according to the fourth embodiment is the same as that of the second embodiment shown in FIG. Only the configuration of the phase controller differs from that of the second embodiment. First, the changed portions other than the phase control unit of the third embodiment are similar to the changed portions of the first embodiment of the second embodiment. Next, in the phase controller (FIG. 13) of the third embodiment, the delay time setting signal calculation circuit 741
A, the bit number n of the data bus in the cumulative addition unit 745 is 2
The fixed value "8" input to the adder is changed to "16". Further, a fixed clock of the symbol rate is input to the first clock phase shift circuit 743B and the second clock phase shift circuit 743C, and the delay clock group generation circuit 743 is input.
The number of clocks generated by 2 is doubled by increasing the number of delay elements. In the clock selection circuits 743E and 743F, the number of input clocks is doubled.

With the above modification, in the fourth embodiment, the frequency of the input clock can be reduced from the frequency twice the symbol rate to the frequency of the symbol rate. Therefore, the operation of the demodulator of the fourth embodiment is performed. The frequency is half that of the demodulator of the third embodiment, further lower power consumption can be realized, and the demodulator can be easily formed into a gate array by CMOS.

Embodiment 5. The phase control unit of the third embodiment realizes stable phase control even when a significant signal receiving state continues continuously, such as in FDMA communication. Then, the third embodiment
It shows a phase control unit that realizes more stable phase control with a smaller circuit scale.

The structure of the demodulator in the fifth embodiment is the same as that of the first embodiment shown in FIG. The configuration of the timing recovery circuit according to the fifth embodiment is the same as that of the first embodiment shown in FIG. Only the configuration of the phase controller differs from that of the first embodiment. FIG. 16 shows the configuration of the phase controller according to the fifth embodiment. In the figure, 7400 is a π phase shift circuit,
Reference numeral 7401 is a first frequency dividing circuit, 7402 is a second frequency dividing circuit, 743A is a clock phase shift circuit, 7403 is a clock switching circuit, 7404 is a clock switching signal output circuit, and 745A is a cumulative addition circuit with a reset function. is there.

Next, the operation of this phase controller will be described. First, the π phase shift circuit 7400 shifts the fixed clock having twice the symbol rate by π radians. The π radian phase shift may be achieved by inverting a fixed clock with an inverter element or the like. The fixed clock and the fixed clock whose phase is shifted by π radians are input to the clock switching unit 7403. The clock switching circuit 7403 uses the clock selection signal output from the clock switching signal output circuit 7404 in the subsequent stage as a comparison clock for one of the fixed clock and the fixed clock that has been phase-shifted by π radians, and uses one of them as a phase-shifting clock. Output each. Cumulative addition circuit 74
5A is composed of a cumulative addition circuit of an n-bit data bus, cumulatively adds the timing phase error signal by the equation (28a), and outputs a cumulative addition value Lj. Further, the register is expressed by the formula (2) by the reset signal Rj of logic “0” output from the clock switching signal output circuit 7404 in the subsequent stage.
8b), reset to "0". Lj = mod (Lj-1 + Ej, 2n) (Rj = 1) (28a) Lj = mod (Ej, 2n) (Rj = 0) (28b) The clock phase shift circuit 743A accumulates the phase shift clock Lj. In accordance with the above, the phase shift clock is Δp phase shifted as shown in the equation (29a) and output as a reproduction double clock.
In this embodiment, n = 4. Therefore, Lj and the amount of phase shift Δ
The relation with p is the following equation (29b). Δp = mod ((2π / 2 (n-1) + 4απ / T) × Lj, 2π) (29a) Δp = mod ((π / 4 + 4απ / T) × Lj, 2π) (29b) First frequency division by two The circuit 7401 divides the comparison clock by two and outputs the divided clock as the comparison two-divided clock. The second divide-by-two circuit 7402 divides the reproduction double clock into two and outputs it as a reproduction two-divided clock.

Here, consider the case of Lj = 0. In this case, as shown in FIG. 17A, the phase shift relationship between the comparison clock and the regenerated double clock is Δp = 0, and thus is π (radian). Therefore, the comparison divided by 2 clock and the reproduction 2
The phase relationship of the divided clock is π / 2 (radian). At this time, if the comparison divided-by-2 clock is retimed with the reproduction divided-by-2 clock, the re-timed data W
j indicates all "1" or all "0" as shown in FIG. On the other hand, consider the case where Lj changes.
In this case, the phase shift relationship between the comparison clock and the reproduction double clock changes from π (radian) due to the change of Lj. If Lj falls within the range of 12 ≧ Lj ≧ 4, 2 for comparison
The data Wj obtained by retiming the divided clock with the reproduced divided-by-2 clock changes from "1" to "0" or from "0" to "1".

In FIG. 17B, for example, Lj increases,
6 is a timing chart in the case where the phase of the reproduction double clock is gradually delayed. In this case, the phase difference between the reproduction double clock and the comparison clock decreases from π to 0 and then becomes 0 →
After a phase jump of 2π, it decreases again. In this case, when the phase jump of 0 → 2π occurs, the data Wj
Changes from "0" to "1". It should be noted that when this Wj fluctuates, the phase difference between the comparison clock and the regenerated double clock is substantially in agreement. The clock switching signal output circuit 7404 retimes the comparison divided-by-2 clock with the reproduction divided-by-2 clock, and the retimed data Wj changes from “1” to “0” or “0” to “1”. Then, the logic of the output clock selection signal is switched. At the same time, the reset signal Rj is set to logic "0" at the time of switching, and the register in the cumulative addition circuit 745A is cleared.

For example, the clock switching circuit 7403 is
First, it is assumed that a fixed clock is selected as the comparison clock and a π phase-shifted fixed clock is selected as the phase shift clock. After that, when Wj changes from "1" to "0" or from "0" to "1" and the logic of the clock selection signal changes, the fixed clock that is phase-shifted by π to the comparison clock is used as the phase-shifting clock. Switch to select fixed clock. This clock switching is performed in the first embodiment.
The clock selection circuit 7433 is realized by the same circuit configuration (the circuit for selecting one out of eight clocks may be changed to the circuit for selecting one out of two clocks). As described above, since the phase difference between the comparison clock and the regenerated double clock at the time of switching is substantially the same, there is no sudden change in the regenerated double clock phase at the time of switching.

Further, when a certain condition as in the third embodiment, for example, K1j takes a value around "4" and K2j takes a value around "12", the relational expression of equation (27) is satisfied, Therefore, the clock selection circuit 746 frequently switches clocks, which may increase clock jitter. However, in the fifth embodiment, the timing after clock switching is shown in FIG. Because of returning to the timing, Wj shows a stable value of all "1" or all "0" again. Therefore, even when continuously receiving data, stable operation can be expected from the phase control unit according to the third embodiment. Furthermore, the phase control unit of the fifth embodiment can be configured with a simpler circuit than the phase control unit of the third embodiment.

From the above, in the fifth embodiment, as in the first embodiment, the timing reproduction circuit inputs the fixed clock twice the symbol rate, and the phase control step interval is sufficiently small with respect to the symbol period. (1/16 or less of the symbol period) is stably realized. Therefore, the timing recovery circuit of the fifth embodiment can realize low power consumption and easy circuit design especially when the symbol rate is high such as in a high-speed wireless transmission system. Further, the timing reproduction circuit of the fifth embodiment uses the baseband phase data oversampled by the symbol frequency generation unit 71A at twice the symbol rate to perform high-speed pull-in on a data pattern having a large phase variation. It can be carried out. Furthermore, the timing recovery circuit of the fifth embodiment has the phase control unit of the fifth embodiment, and thus the FDMA
Even when a significant signal reception state continues continuously, such as in communication, abrupt phase change of the reproduction clock phase does not occur, and more stable phase control than the timing reproduction circuit of the third embodiment is performed. It can be realized with a simpler circuit.

Sixth Embodiment By the way, the demodulator having the phase control unit of the fifth embodiment in which the input fixed clock has the frequency of the symbol rate can also be realized by a simple circuit modification from the fifth embodiment. Below, in order to operate the demodulator of the fifth embodiment with a fixed clock of the symbol rate,
The changes from the fifth embodiment will be described. The configuration of the demodulator in the sixth embodiment is the same as that of the second embodiment in FIG. The configuration of the timing recovery circuit according to the sixth embodiment is the same as that of the second embodiment shown in FIG. Only the configuration of the phase controller differs from that of the second embodiment.

First, the changed portions other than the phase control portion of the fifth embodiment are similar to the changed portions of the second embodiment from the first embodiment. Next, in the phase controller of the fifth embodiment, the number of bits n of the data bus in the cumulative addition circuit 745A is n.
Is doubled. Further, a clock switching circuit circuit 7403,
A fixed clock having a symbol rate is input to the π phase shift circuit 7400, and the number of clocks generated by the delay clock group generation circuit 7432 in the clock phase shift circuit 743A is doubled by doubling the delay elements. . Further, the clock selection circuit 7433 doubles the number of input clocks.

With the above modification, the sixth embodiment can reduce the frequency of the input clock from the frequency twice the symbol rate to the frequency of the symbol rate. Therefore, the operation of the demodulator of the sixth embodiment is performed. The frequency is half that of the demodulator of the fifth embodiment, further lower power consumption can be realized, and the demodulator can be easily formed into a gate array by CMOS.

Seventh Embodiment The phase control units according to the first to sixth embodiments basically use a delay element connected in series to generate a plurality of clocks, and a reproduced double clock or a reproduced symbol clock is generated from them. Was to select one. Therefore, if a delay time error ± α occurs due to a temperature change or the like, the control operation provided for each embodiment does not cause a significant abrupt change in the clock phase during signal reception, but the phase control step interval changes. Will end up. Therefore, the clock phase pull-in characteristic and the jitter characteristic of each timing recovery circuit having the phase control unit according to the first to sixth embodiments are affected to some extent by the delay time error α. Therefore, the seventh embodiment shows a phase control unit that does not use a delay element.

The phase control unit in the seventh embodiment controls the phase of the regenerated double clock by using the quadrature modulation circuit. In the first embodiment, the third embodiment and the fifth embodiment,
Although the fixed clock twice the symbol rate is input, the phase control unit of the seventh embodiment uses a local sine wave signal having a frequency twice the symbol rate instead of the fixed clock twice the symbol rate. Input it. Therefore, the configuration of the demodulator in the seventh embodiment is the same as that shown in FIG.
A fixed clock oscillator for timing reproduction having a frequency twice the symbol rate of A is changed to a fixed local sine wave oscillator for timing reproduction having a frequency twice the symbol rate. The configuration of the timing recovery circuit according to the seventh embodiment is the same as that of the first embodiment shown in FIG. Only the configuration of the phase controller differs from that of the first embodiment.

FIG. 18 is a block diagram of the phase control unit in the seventh embodiment, in which 745B is a cumulative addition circuit and 740.
5 is a cosine / sine conversion circuit, 7406 is a quadrature modulation circuit, 7408 is a hard decision circuit, 7406a and 7406b are DA converters, 7406c and 7406d are low-pass filters, 7406e and 7406f are multipliers, 7406g is an adder, and 7406h is π. / 2 phase shifter.

Next, the operation of this phase controller will be described. First, assuming that the number of phase control steps is T / Z (T; symbol period, Z = 2n), the cumulative addition circuit 745B
Is a cumulative addition circuit configured by a (n-1) -bit data bus having Ej as an input. Cumulative addition circuit 74
5B performs the cumulative addition of the following Expression (30) and outputs the added value as Pj. Pj = mod (Pj−1 + Ej, 2n−1) (30) The cosine / sine conversion circuit 7405 has
The following two digital data are output. Idj = cos (Pj × π / 4) Qdj = sin (Pj × π / 4) (31) The quadrature modulation circuit converts these data Idj and Qdj into a local sine wave signal having a frequency twice the symbol rate. Is used for quadrature modulation to generate a modulated signal having a frequency twice the symbol rate. The quadrature modulation circuit is conventionally used as a means for frequency-converting an in-phase component of a PSK-modulated baseband signal and a quadrature component into an IF signal having a certain frequency. In the present embodiment, this quadrature modulation circuit is reproduced. It is used for the phase controller of the double clock.

The detailed operation of the quadrature modulation circuit 7406 will be described. First, as shown in FIG. 18, the DA conversion circuit 7406a DA-converts Idj, and the DA conversion circuit 7406b DA-converts Qdj.
Reference numerals 6c and 7406d remove harmonic components of each DA-converted analog signal. The low-pass filter 7406c output is I (t), and the low-pass filter 7406d output is Q.
Assuming that (t), the signal SC (t) output from the quadrature modulation circuit 7406 is obtained from the following equation (32) from FIG. (However, fs; symbol frequency) SC (t) = I (t) × cos 2π (2fs) t + Q (t) × sin 2π (2fs) t (32) Therefore, SC (t) is a sine that is twice the symbol frequency. Assuming that Idj≈I (jT) and Qdj≈Q (jT), the local signal cos2π of the signal SC (t) is obtained.
The following expression (33) is established between the phase difference Δp from (2fs) t and the Pj. Δp = mod (Pj, 2n−1) × π / 4 (33) The hard decision circuit 7408 outputs the signal of logic “1” to the SC (t) signal when the amplitude of the SC (t) signal is positive. When the amplitude of is negative, a signal of logic "0" is output. in this way,
If the hard decision circuit 7408 makes a hard decision on the SC (t) signal, a reproduction double clock can be obtained. Therefore, since the phase control unit of the seventh embodiment does not use the delay element, it is not affected by the delay time error α and even if Pj is increased to 6,7,0,1,2,3 ... Even if it decreases to 2,1,0,7,6,5 ...
The clock phase control is always realized by the phase control steps at equal intervals.

From the above, in the seventh embodiment, the timing reproduction circuit inputs the local sine wave signal having twice the symbol rate, and the phase control step interval (one symbol cycle is 1) which is sufficiently small with respect to the symbol cycle. / 16
The following) is stably realized. Therefore, the timing recovery circuit of the seventh embodiment can realize low power consumption and easy circuit design especially when the symbol rate is high such as in a high-speed wireless transmission system. In the timing recovery circuit of the seventh embodiment, the symbol frequency generator 71A
Using the baseband phase data oversampled at twice the symbol rate, it is possible to perform high-speed pull-in especially for a data pattern having a large phase variation.
Further, in the timing recovery circuit of the seventh embodiment, the phase control unit having the quadrature modulation circuit of the seventh embodiment does not affect the characteristics depending on the temperature, and thus the FDMA communication or the like is performed.
Even when a significant signal reception state continues all the time, by the phase control steps at equal intervals of the recovered symbol clock,
It is possible to realize stable phase control.

Eighth Embodiment By the way, the demodulator having the phase control unit of the seventh embodiment, which uses the input local sine wave signal as the frequency of the symbol rate, can also be realized by a simple circuit modification from the seventh embodiment. The following is a description of changes from the seventh embodiment for operating the demodulator of the seventh embodiment with the local sine wave signal having the symbol rate. The configuration of the demodulator in the eighth embodiment is 8B shown in FIG.
The fixed clock oscillator for timing reproduction which is the frequency of the symbol rate is changed to the fixed local sine wave oscillator for timing reproduction which is the frequency of the symbol rate. The structure of the timing recovery circuit in the eighth embodiment is the same as that of the second embodiment shown in FIG. Only the configuration of the phase controller differs from that of the second embodiment.

First, the changed portions other than the phase controller of the seventh embodiment are similar to the changed portions of the second embodiment from the first embodiment. Next, the cumulative addition circuit 745B is changed from a cumulative addition circuit configured by a (n-1) -bit data bus having Ej input to a cumulative addition circuit configured by an n-bit data bus having Ej input. To do. In this case, P
j is obtained by the following equation (34). Pj = mod (Pj−1 + Ej, 2n) (34) Further, in the cosine / sine conversion circuit 7405,
The processing of 1) is changed to the processing of the following expression (35). Idj = cos (Pj × π / 8) Qdj = sin (Pj × π / 8) (35) Further, the quadrature modulation circuit uses a local sine wave signal having a frequency twice the symbol rate instead of the symbol rate. A local sine wave signal having a frequency may be input. in this case,
The signal SC (t) output from the quadrature modulation circuit is obtained by the following equation (36) (where fs is the symbol frequency). SC (t) = I (t) × cos2π (fs) t + Q (t) × sin2π (fs) t (36)

Therefore, in the eighth embodiment, SC (t) is a sine wave having a symbol frequency, and Idj≈I (jT),
Assuming Qdj≈Q (jT), the phase difference Δp of the signal SC (t) from the local signal cos2π (fs) t,
With respect to Pj, the following expression (37) is established. Δp = mod (Pj, 2n) × π / 8 (37) The hard decision circuit 7408 has the same SC as in the seventh embodiment.
When the amplitude of the (t) signal is positive, a signal of logic "1" is output, and when the amplitude of the SC (t) signal is negative, a signal of logic "0" is output. In this way, the hard decision circuit 7408 causes the SC
If the (t) signal is hard-decided, the reproduced symbol clock can be obtained.

With the above changes, the eighth embodiment changes the frequency of the input local sine wave signal to the symbol rate 2
Since the frequency can be reduced from the double frequency to the frequency of the symbol rate, the operating frequency of the demodulator of the eighth embodiment is
This is half the demodulator of the seventh embodiment, and it is possible to further reduce power consumption, and it is possible to easily form a gate array using a CMOS demodulator.

Ninth Embodiment The phase controller of the eighth embodiment requires two DA converters in the quadrature modulation circuit,
The circuit scale is relatively large. Further, since the π / 2 phase shift circuit is used, the characteristics may be degraded depending on the accuracy of the π / 2 phase shift.
Therefore, the ninth embodiment is smaller than the eighth embodiment,
A phase control unit having excellent characteristics is shown. The phase control unit according to the ninth embodiment inputs a fixed clock having a frequency twice the symbol rate, as in the first, third, and fifth embodiments. However,
The difference from the phase control unit up to now is that the output of the phase control unit of the ninth embodiment is not the reproduction double clock but the reproduction symbol clock.

Therefore, the structure of the demodulator according to the ninth embodiment is such that the fixed clock oscillator for timing reproduction having the frequency of the symbol rate of 8B shown in FIG. The configuration is changed to an oscillator. The configuration of the timing recovery circuit in the ninth embodiment is the same as that in the second embodiment shown in FIG.
The configuration is the same as that of. Only the configuration of the phase controller differs from that of the second embodiment. 19 in which parts corresponding to those in FIG. 18 are assigned the same reference numerals is a block diagram of the phase control unit in the present ninth embodiment. A second sign inversion circuit, 7412 a clock amplitude value selection circuit, 7413 a DA conversion circuit, 7
Reference numeral 414 is an analog low-pass filtering circuit.

Next, the operation of this phase controller will be described. The cumulative addition circuit 745B and the cosine-sine conversion circuit 7405 perform cumulative addition of the timing phase error Ej by the equation (34) as in the case of the seventh embodiment, and then the equation (35).
The data Idj and Qdj are obtained by the conversion. The divide-by-2 circuit 7409 divides the fixed clock having a frequency twice the symbol rate by two and outputs the fixed clock divided by two. The first sign inversion circuit 7410 receives Idj as an input, and if the logic of the fixed clock divided by two is “1”, Id
j is output as it is, and if the logic of the fixed clock divided by two is "0", Idj is inverted and output. Similarly, the second sign inversion circuit 7411 receives Qdj as an input and outputs Qdj as it is if the logic of the fixed clock divided by 2 is “1”, and outputs the logic of the fixed clock divided by 2 as “0”. Qdj is inverted and output. Clock amplitude value selection circuit 7
412 outputs the data of the first sign inversion circuit 7410 if the fixed clock having a frequency twice the symbol rate is a logical "1", and outputs the second data if the fixed clock having a frequency twice the symbol rate is a logical "0". The data of the sign inversion circuit 7411 is output.

Assuming that the output value of the clock amplitude value selection circuit 7412 is Sd, the series of operations up to this point is performed as shown in FIG.
(T is a symbol period in the figure). Id
When the timings of j and Qdj and the timing of the fixed clock having a frequency twice that of the symbol rate, and the fixed clock divided by two are shown in FIG. 20, the data sequence of Sd obtained by the above processing is as shown in FIG. The waveform has various symbol frequency components. DA conversion circuit 7413
Converts the Sd into a DA signal and converts it into an analog signal.
Further, an analog low pass filtering circuit 7414
Removes the harmonic component of the signal after DA conversion and outputs the removed analog signal s (t). In the example of FIG. 20, the data series Sd is converted into the curve s (t) shown by the dotted line. The hard decision circuit 7408 is similar to the seventh embodiment in that
(T) is subjected to a hard decision, and the data after the hard decision is output as a reproduction double clock. As in the example of FIG. 20, the signal s (t)
At the change point of positive → negative of, the reproduction double clock falls,
At the point of change from negative to positive, the double reproduction clock rises. As described above, the phase control unit of the ninth embodiment is the same as that of the seventh embodiment.
Similarly to the above, since the delay element is not used, the clock phase control is always realized by the phase control steps at equal intervals without being affected by the delay time error α.

From the above, in the ninth embodiment, the timing recovery circuit inputs the local sine wave signal having twice the symbol rate, and the phase control step interval (one symbol period is 1) which is sufficiently small with respect to the symbol period. / 16
The following) is stably realized. Therefore, the timing recovery circuit of the ninth embodiment can realize low power consumption and easy circuit design especially when the symbol rate is high such as in a high-speed wireless transmission system. In the timing recovery circuit of the ninth embodiment, the symbol frequency generator 71A
Using the baseband phase data oversampled at twice the symbol rate, it is possible to perform high-speed pull-in especially for a data pattern having a large phase variation.
Further, in the timing recovery circuit of the ninth embodiment, the phase control unit having the quadrature modulation circuit of the ninth embodiment does not influence the characteristics depending on the temperature, so that the timing reproduction circuit can be used in the FDMA communication.
Even when a significant signal reception state continues all the time, by the phase control steps at equal intervals of the recovered symbol clock,
It is possible to realize stable phase control. Further, the phase control unit of the ninth embodiment can be configured with only one DA converter and one low-pass filter, and the rest is performed by digital signal processing. Therefore, the circuit scale is smaller than that of the phase control unit of the seventh embodiment. . Furthermore, the phase controller of the ninth embodiment is
A process equivalent to that of the quadrature modulation circuit 7406 of the seventh embodiment is
Since the processing is performed by digital signal processing, the characteristics are not affected by the accuracy of analog elements such as π / 2 phase shifter.

Embodiment 10. FIG. The timing recovery circuit according to the first embodiment realizes a high-speed phase pull-in when the baseband phase data largely changes for each symbol, but like the π / 4 shift QPSK modulation system, When the fluctuation amount is relatively small, it may take time to pull in the timing phase. The tenth embodiment shows a timing reproduction circuit that pulls in a timing phase at high speed even in such a case.

The structure of the demodulator in the tenth embodiment is as follows.
The configuration is the same as that of the first embodiment shown in FIG. The configuration of the timing reproduction circuit is different from that of the first embodiment. FIG. 21, which is assigned the same reference numeral as FIG. 23, shows the configuration of the timing reproduction circuit in the tenth embodiment, and 78 is a phase data interpolation circuit,
71C is a symbol frequency component generator, and 77A is a filter information memory.

Next, the operation of the timing reproduction circuit according to the tenth embodiment will be described. This timing reproduction circuit also
Similar to the first embodiment, it operates using baseband phase data oversampled at twice the symbol rate, and the operation clock is a fixed clock with a frequency twice the symbol rate. The timing reproduction circuit calculates the phase between the sample phase data from the baseband phase data θi = θ (iT / 2) (i = 1,2,3,4, ...) Oversampled at twice the symbol rate. Data θ (iT / 2
+ T / 4) is obtained by interpolation processing such as linear interpolation to generate a baseband phase data sequence oversampled at 4 times the symbol rate, and this data sequence is used in the same manner as in a conventional timing reproduction circuit. The timing phase error is calculated at. The phase control unit according to the tenth embodiment may use any one of the first, third, fifth, and seventh embodiments. The detailed operation of the timing recovery circuit according to the tenth embodiment will be described below.

The phase data interpolator 78 of FIG. 21 calculates the phase data θ (iT / iT / i) between the baseband phase data θ (iT / 2) (i = 1,2,3,4, ...) Two
+ T / 4) is obtained by interpolation calculation. In the tenth embodiment, phase data between each sample phase data is obtained by simple linear interpolation. Equation (38) shows the processing in the phase data interpolating unit 78. However, ΔMi is θ (iT / 2
This is the amount of change from + T / 2) to θ (iT / 2), and is calculated by the equation (39). θ (iT / 2 + T / 4) = mod (θ (iT / 2) + ΔMi / 2 + 2π, 2π) (38) ΔMi = θ ((i + 1) T / 2) −θ (iT / 2) [−π <θ ( (I + 1) T / 2) -θ (iT / 2) <+ π] ΔMi = θ ((i + 1) T / 2) -θ (iT / 2) + 2π [-π ≧ θ ((i + 1) T / 2)- θ (iT / 2)] ΔMi = θ ((i + 1) T / 2) −θ (iT / 2) −2π [+ π ≦ θ ((i + 1) T / 2) −θ (iT / 2)] (39) In the present embodiment, primary interpolation is used for the interpolation calculation, but any other interpolation such as secondary interpolation that interpolates data may be used.

The symbol frequency component generator 71C, as shown in the following equation (40), outputs the baseband phase data θ (iT / 2) and the preceding phase data θ ((i-
1) Calculate ΔθR (iT / 2) using T / 2). ΔθR (iT / 2) = min {| θ (iT / 2) −θ ((i-1) T / 2) |, 2π− | θ (iT / 2) −θ ((i-1) T / 2 ) |} (40) Further, as shown in the following equation (41), interpolated phase data θ (iT / 2 + T /
4) and the immediately previous interpolated phase data θ (iT / 2−
ΔθH (iT / 2 + T / 4) is calculated using (T / 4). ΔθH (iT / 2 + T / 4) = min {| θ (iT / 2 + T / 4) −θ (iT / 2-T / 4) |, 2π− | θ (iT / 2 + T / 4) −θ (iT / 2-T / 4) |} (41) Therefore, according to the following equation (42), the data sequence Δθ (kT / 4) having the symbol frequency component on the transmission side at the timing of four times the symbol rate. ) (K = 1,2,3,4, ...) is obtained. Δθ (kT / 4) = ΔθR (iT / 2) [mod (k, 2) = 0] Δθ (kT / 4) = ΔθH (iT / 2 + T / 4) [mod (k, 2) = 1] (42 )

Note that due to the influence of the interpolation error, ΔθH (iT /
2 + T / 4), the amount of symbol frequency components included in Δθ is
From the symbol frequency component amount included in R (iT / 2),
It may be small. In that case, ΔθH (iT /
2 + T / 4) is multiplied by the weighting coefficient β. In this case, the equation (42) is changed to the equation (42a). Δθ (kT / 4) = ΔθR (iT / 2) [mod (k, 2) = 0] Δθ (kT / 4) = βΔθH (iT / 2 + T / 4) [mod (k, 2) = 1] (42a )

The subsequent operation is the same as that of the conventional example, and Δθ
The correlation between (kT / 4) and the symbol frequency component on the receiving side is obtained by the complex multiplication unit 72 and the low-pass filtering unit 73. When the timing phase difference Δθj is calculated, Δ
The value for canceling θj is set to the delay time setting signal calculation circuits 741 and 741A of the first to fourth embodiments or the cumulative addition circuit 7 of the fifth to ninth embodiments.
45A and 745B, and the reproduced symbol clock is instantaneously phase-synchronized with the transmission timing.

As described above, the demodulator shown in the tenth embodiment also operates by using the received PSK signal whose amplitude is limited, as in the conventional example. Therefore, it can be configured by a simple circuit having a limiter in the preceding stage. Therefore, the circuit can be downsized. Further, since the demodulator shown in the tenth embodiment has a feedback type configuration for performing AD conversion at the timing of the reproduction double clock, it operates at twice the symbol rate, which is half the sampling rate of the conventional example. Therefore, low power consumption can be realized. Further, while the conventional timing recovery circuit 7 inputs a fixed clock of x times the symbol rate and performs the phase control step of 1 / x of the symbol period, the timing shown in the tenth embodiment. The reproduction circuit inputs a fixed clock twice the symbol rate and stably realizes a phase control step interval (1/16 or less of the symbol period) which is sufficiently small with respect to the symbol period. Therefore, the timing recovery circuit can realize low power consumption and facilitate circuit design especially when the symbol rate is high such as in a high-speed wireless transmission system.
The timing reproduction circuit uses the baseband phase data oversampled at the symbol rate twice by the phase data interpolator 78 to generate the baseband phase data at the timing four times the symbol rate, and the fourfold Since the timing phase difference is obtained in the same manner as the conventional method using the baseband phase data generated at the timing of, the phase fluctuation is relatively small like the baseband phase data modulated by π / 4 shift QPSK. High-speed acquisition can be performed on the data pattern.

[0111]

As described above, according to the present invention, the symbol on the transmitting side can be processed by simple signal processing including subtraction of 1/2 symbol difference from the baseband phase data oversampled at twice the symbol rate. Since a data series including frequency components can be obtained, the symbol frequency generation unit can be easily realized as a digital circuit or an LSI. Further, by using this data series for timing reproduction, it is possible to realize a timing reproduction circuit exhibiting a high-speed phase pull-in characteristic. Further, since the present symbol frequency generation unit operates at a frequency twice the symbol rate, the power consumption of the timing reproduction circuit can be reduced and the LSI of the timing reproduction circuit can be easily realized especially in a high-speed wireless transmission system. .

According to the following invention, in addition to the above,
With a feedback-type configuration that takes as input the baseband phase data that is oversampled at twice the symbol rate, it is possible to generate a regenerated symbol clock that is phase-synchronized with the transmission timing on the transmission side, so timing regeneration is possible with a small circuit scale A circuit can be realized. Further, a timing recovery circuit that exhibits a high-speed phase pull-in characteristic for a data pattern in which + π and −π phase fluctuations are repeated for each symbol is realized.

Further, according to the next invention, in addition to the above, the random-pass filtering unit is used in the low-pass filtering unit to average the multiplication data.
The configuration of the low-pass filtering unit is simplified, and a timing reproduction circuit having a smaller circuit scale can be realized.

Further, according to the next invention, in addition to the above, a data sequence having a symbol frequency component and four times the symbol rate is generated by phase interpolation calculation, and correlation calculation with the symbol frequency component on the receiving side is performed. In order to obtain the timing phase error, a timing recovery circuit exhibiting a high-speed phase pull-in characteristic is realized particularly for data having a relatively small phase fluctuation such as a π / 4 shift QPSK-modulated baseband signal. .

Further, according to the next invention, since the timing recovery circuit operates with a fixed clock having a frequency twice the symbol rate, particularly in a high speed wireless transmission system.
The power consumption of the timing reproduction circuit can be reduced, and the timing reproduction circuit can be easily integrated into an LSI.

Further, according to the next invention, in addition to the above, since the timing reproduction circuit operates with a fixed clock having the same frequency as the symbol rate, the power consumption of the timing reproduction circuit can be further reduced and the timing reproduction circuit can be further reduced. L
SI can be easily achieved.

According to the next invention, the timing recovery circuit operates with a fixed clock having a frequency twice the symbol rate, and the correction delay value calculation circuit causes the timing phase to be controlled during phase control during significant data reception. Realize a timing recovery circuit that realizes stable clock phase control without disturbance.

Further, according to the next invention, in addition to the above, the timing reproduction circuit operates with a fixed clock having the same frequency as the symbol rate, so that the power consumption of the timing reproduction circuit can be further reduced and the timing reproduction circuit can be further reduced. L
SI can be easily achieved.

Further, according to the next invention, the two clock phase shift circuits are used to generate a regenerated symbol clock continuously phase-synchronized with the transmission timing of the transmission side, and the temperature characteristic generated in the clock phase shift circuit is generated. Even if an error in the setting delay time occurs due to such factors as described above, a timing reproduction circuit in which the clock phase is not disturbed during phase control is realized. Further, since the timing recovery circuit operates with a fixed clock having a frequency twice the symbol rate, the power consumption of the timing recovery circuit can be reduced and the timing recovery circuit can be easily integrated into an LSI especially in a high-speed wireless transmission system. .

Further, according to the following invention, in addition to the above, the timing reproduction circuit operates with a fixed clock having the same frequency as the symbol rate, so that the power consumption of the timing reproduction circuit can be further reduced and the timing reproduction circuit can be further reduced. L
SI can be easily achieved.

Further, according to the next invention, a regenerated symbol clock continuously phase-synchronized with the transmission timing of the transmitting side is generated by a simple circuit configuration using one clock phase shifting circuit, and the clock phase shifting is performed. (EN) A timing reproduction circuit in which a clock phase is not disturbed during phase control even when an error in a set delay time occurs due to temperature characteristics or the like generated in the circuit. Further, since the timing recovery circuit operates with a fixed clock having a frequency twice the symbol rate, the power consumption of the timing recovery circuit can be reduced and the timing recovery circuit can be easily integrated into an LSI especially in a high-speed wireless transmission system. .

Further, according to the following invention, in addition to the above, since the timing reproduction circuit operates with a fixed clock having the same frequency as the symbol rate, the power consumption of the timing reproduction circuit can be further reduced and the timing reproduction circuit can be further reduced. L
SI can be easily achieved.

According to the next invention, in addition to the above, in the clock phase shift circuit, the delay element is (N-1).
A fixed amount of delay is given to the fixed clock by generating (N-1) delayed fixed clocks by using one clock and selecting one from N clocks including the fixed clock. The circuit can be realized by a simple circuit that does not require a high speed clock.

According to the next invention, the phase control section is
A quadrature modulation circuit composed of two DA converters, two low-pass filters, two multipliers, and one adder, and a simple circuit consisting of a hard decision circuit are used to perform the reproduction clock phase control according to the delay time setting signal. , Can be continuously performed with a constant phase control step interval. Further, since the timing recovery circuit operates with a local sine wave having a frequency twice the symbol rate, the power consumption of the timing recovery circuit can be reduced and the timing recovery circuit can be easily integrated into an LSI especially in a high-speed wireless transmission system. Becomes

Further, according to the following invention, in addition to the above, since the timing reproduction circuit operates with the local sine wave having the same frequency as the symbol rate, the power consumption of the timing reproduction circuit can be further reduced and the timing reproduction can be further achieved. The circuit can be easily integrated into an LSI.

According to the next invention, the phase control section
A simple circuit consisting of a digital circuit that performs processing equivalent to that of a quadrature modulation circuit, one DA conversion section, one analog low-pass filtering section, and a hard decision circuit, and controls the recovered clock phase according to the delay time setting signal. It can be continuously performed with a constant phase control step interval. Further, since the timing recovery circuit operates with a local sine wave having a frequency twice the symbol rate, the power consumption of the timing recovery circuit can be reduced and the timing recovery circuit can be easily integrated into an LSI especially in a high-speed wireless transmission system. Becomes

Further, according to the next invention, a demodulator for rapidly generating a regenerated symbol clock phase-synchronized with the transmission timing on the transmission side and outputting demodulated data in synchronism therewith is realized. Further, since this demodulator operates by using the baseband signal whose amplitude is limited, it is possible to have a limiter amplifier in the preceding stage, and the demodulator can be miniaturized. Further, since the demodulator oversamples data at twice the symbol rate, the power consumption of the demodulator can be reduced and the demodulator can be easily integrated into an LSI especially in a high-speed wireless transmission system.

According to the next invention, the amplitude-limited baseband signal is oversampled at twice the symbol rate to generate a regenerated symbol clock phase-synchronized with the transmission timing on the transmitting side, and synchronized with it. A demodulator that outputs the demodulated data is realized. Furthermore, this demodulator
Since a fixed clock having a frequency twice the symbol rate or a local sine wave having a frequency twice the symbol rate operates, the power consumption of the demodulator can be reduced and the LSI of the demodulator can be realized especially in a high-speed wireless transmission system. It becomes easy to convert.

According to the next invention, in addition to the above,
The number of AD converters used for sampling by the sampling circuit that samples the baseband in-phase signal and the baseband quadrature signal at the rising and falling edges of the recovered symbol clock and outputs them as baseband in-phase data and baseband quadrature data, respectively. However, the frequency of the fixed clock or the local sine wave can be reduced from twice the symbol rate to the same frequency as the symbol rate. It is possible to realize a demodulator with low power consumption and easy LSI implementation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a first embodiment of a demodulator according to the present invention.

FIG. 2 is a block diagram showing an overall configuration of a second embodiment of a demodulator according to the present invention.

3 is a block diagram showing a configuration of a timing recovery circuit in the demodulator of FIG.

4 is a block diagram showing a configuration of a timing recovery circuit in the demodulator of FIG.

FIG. 5 is a block diagram showing the phase control unit of the first embodiment in the timing recovery circuit according to the present invention.

FIG. 6 is a block diagram showing a phase control unit in the timing reproduction circuit according to the present invention, in which the clock phase is not disturbed even if a time error occurs in the delay element of the first embodiment.

FIG. 7 is a block diagram showing a clock phase shift circuit in the phase control unit according to the present invention.

FIG. 8 is a timing chart for explaining the operation of the timing reproduction circuit of FIG.

FIG. 9 is a flowchart for explaining the operation of the random walk filter according to the first embodiment.

FIG. 10 is a timing chart provided for explaining the operation of the clock phase shift circuit of FIG.

FIG. 11 is a timing chart for explaining a conventional clock selection operation.

12 is a graph of delay time setting signal vs. clock phase difference characteristics when the delay time error of the delay element is used as a parameter in the phase control unit of FIG.

FIG. 13 is a block diagram showing a phase control unit of the third embodiment in a timing reproduction circuit according to the present invention.

14 is a block diagram showing a first clock phase shift circuit and a second clock phase shift circuit in the phase control section of FIG. 13. FIG.

FIG. 15 is a timing chart for explaining the operation of the phase control unit in FIG.

FIG. 16 is a block diagram showing a phase control unit of the fifth embodiment in a timing recovery circuit according to the present invention.

FIG. 17 is a timing chart for explaining the operation of the phase control unit in FIG.

FIG. 18 is a block diagram showing a phase control unit according to a seventh embodiment of the timing reproduction circuit according to the present invention.

FIG. 19 is a block diagram showing a phase control unit of the ninth embodiment in a timing reproduction circuit according to the present invention.

20 is a timing chart for explaining the operation of the phase controller of FIG.

FIG. 21 is a block diagram showing the overall structure of a tenth embodiment of a timing recovery circuit according to the present invention.

FIG. 22 is a block diagram showing the overall configuration of a conventional demodulator.

FIG. 23 is a block diagram showing an overall configuration of a conventional timing reproduction circuit.

FIG. 24 is a waveform diagram for explaining the operation of the symbol frequency component generation unit in the conventional timing reproduction circuit.

FIG. 25 is a timing chart for explaining the operation of the phase control unit in the conventional timing reproduction circuit.

[Explanation of symbols] 1 limiter 2 Quadrature detection circuit 3 Local oscillator for quadrature detection 4 Sampling circuit 5 Polar coordinate conversion circuit 6 Data judgment circuit 7,7A timing recovery circuit 71 symbol frequency component generator 72 Multiplier 73 Low-pass filtering section 74 Phase control unit 75 Regenerated symbol clock generator 76 Phase information memory 77 Filter information memory 78 Phase data interpolation unit.

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-6-252964 (JP, A) JP-A-8-331190 (JP, A) JP-A-4-271537 (JP, A) JP-A-5- 336183 (JP, A) JP 6-268700 (JP, A) JP 9-135276 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/22 H04L 7 / 00 H04L 7/027

Claims (17)

(57) [Claims] 1. A phase difference unit that performs 1/2 symbol difference on baseband phase data oversampled at twice the symbol rate and outputs the difference result as phase difference data, and the phase difference data is subjected to absolute value conversion. The smaller of the phase difference absolute value data and the value obtained by subtracting the phase difference absolute value data from 2π in radians is used as the symbol frequency component data, and a data conversion unit for outputting at a timing twice the symbol rate. A timing recovery circuit comprising a symbol frequency generation unit having the same. 2. A multiplication unit that multiplies the symbol frequency component data by a symbol frequency component output from a phase control unit to be described later, and outputs the multiplication data, an average of the multiplication data, and timing of the averaged data. wherein a low-pass filtering unit for outputting a phase error signal, further comprising a on the basis of the timing phase error signal, the transmit-side phase controller that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of The timing recovery circuit according to claim 1, wherein 3. The timing recovery circuit according to claim 2, wherein the low-pass filtering unit includes a random walk filtering unit that averages the multiplication data. 4. The phase data at the time of symbol period / 4 from each sampling point is calculated using an interpolation calculation by using two or more pieces of baseband phase data oversampled at twice the continuous symbol rate. , The calculated value is the phase interpolation data, the phase interpolation data is 1/2 symbol difference, the difference result is the interpolation phase difference data, the interpolation phase difference absolute value data obtained by converting the interpolation phase difference data into an absolute value, and radian display 2π from the interpolation phase difference absolute value data, whichever is smaller is output as symbol frequency component interpolation data at a timing of twice the symbol rate. Multiply the component interpolation data by the in-phase component of the symbol frequency output from the phase control unit described later, Output as calculation data, the symbol frequency component data is multiplied by a quadrature component of a symbol frequency output from the phase control unit described later, and a complex multiplication unit that outputs as quadrature multiplication data; A first integral filtering unit that averages with an integral filter and outputs as timing in-phase data, a second integral filtering unit that averages the quadrature multiplication data with a second integral filter, and outputs as timing quadrature data, An arctangent part for obtaining an arctangent value of the timing in-phase data and the timing quadrature data, and a timing phase error signal is obtained from the arctangent value at r symbol periods and output, and at the same time, to the first integral filter. , A vector length indicated by the timing in-phase data and the timing quadrature data is set, and the second And integrating filter outputs the integration filter set signal for resetting the integrating filter control unit, based on the timing phase error signal, that Gyosu phase system as the recovered symbol clock to the transmission timing of the signal side is phase-synchronized transmission The timing recovery circuit according to claim 1, further comprising a phase control unit. 5. Based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmission <br/> signal side, the phase control unit, A delay time setting signal calculator that subtracts the later-described correction delay value from the timing phase error signal and outputs the value obtained by cumulatively adding the subtraction results as a delay time setting signal, and the time when the fixed clock is set by the delay time setting signal. A clock phase shifter for outputting a signal obtained by dividing the reproduction clock by 2 as the reproduction symbol clock, and a corrected delay value of 0 during significant data reception. When the delay time setting signal indicates a time exceeding one cycle of the fixed clock during meaningless data reception, the fixed clock is output. 1 is output as a correction delay value, and when the delay time setting signal indicates a time exceeding -1 cycle of the fixed clock, a value corresponding to -1 cycle of the fixed clock is output as the correction delay value. A timing reproduction circuit having a correction delay value calculation unit that outputs 0 as a correction delay value while the delay time setting signal indicates a time within ± 1 cycle of the fixed clock. 6. Based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmission <br/> signal side, the phase control unit, A delay time setting signal calculator that subtracts the later-described correction delay value from the timing phase error signal and outputs the value obtained by cumulatively adding the subtraction results as a delay time setting signal, and the time when the fixed clock is set by the delay time setting signal. And a clock phase shifter that outputs a delayed fixed clock as the reproduced symbol clock, and outputs 0 as a correction delay value during significant data reception, and delays during meaningless data reception. When the time setting signal indicates a time exceeding one cycle of the fixed clock, a value corresponding to one cycle of the fixed clock is output as a correction delay value, and the delay When the delay time setting signal indicates a time exceeding -1 cycle of the fixed clock, a value corresponding to -1 cycle of the fixed clock is output as a correction delay value, and the delay time setting signal is within ± 1 cycle of the fixed clock. A timing reproduction circuit comprising: a correction delay value calculation unit that outputs 0 as a correction delay value while indicating time. 7. Based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmission <br/> signal side, the phase control unit, A delay time setting signal calculation unit that outputs a value obtained by subtracting a correction delay value described later from the timing phase error signal and accumulating the subtraction results as a first delay time setting signal, and a fixed clock by the delay time setting signal. The first clock phase shifter that delays for the set time and outputs as the first delay clock, and the value that cumulatively adds the timing phase error signal, and outputs as the second delay time setting signal. A second clock phase shifter that delays a fixed clock by a set time by the setting signal calculator and the second delay time setting signal, and outputs the delayed clock as a second delay clock. And the absolute value of the time difference between the delay time indicated by the value of the first delay time setting signal and the cycle of the fixed clock is the delay time indicated by the value of the second delay time setting signal and the cycle of the fixed clock. If it is smaller than the absolute value of the time difference from the first delay clock, if it is larger, a clock switching determination unit that outputs a clock selection signal that specifies the second delay clock, and based on the clock selection signal A clock selection unit that selects one of the first delay clock and the second delay clock, and outputs the selected clock divided by two as the reproduced symbol clock; and the second delay. A clock phase comparison unit that detects whether the first delayed clock phase leads or lags the clock and outputs detection information as a phase detection signal; An averaging unit that averages the phase detection signals and outputs an averaged phase detection signal, accumulates the averaged phase detection signals, and adds the time corresponding to the accumulated value and the fixed clock cycle. A timing recovery circuit which outputs a correction delay value. 8. Based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmission <br/> signal side, the phase control unit, A delay time setting signal calculation unit that outputs a value obtained by subtracting a correction delay value described later from the timing phase error signal and accumulating the subtraction results as a first delay time setting signal, and a fixed clock by the delay time setting signal. The first clock phase shifter that delays for the set time and outputs as the first delay clock, and the value that cumulatively adds the timing phase error signal, and outputs as the second delay time setting signal. A second clock phase shifter that delays a fixed clock by a set time by the setting signal calculator and the second delay time setting signal, and outputs the delayed clock as a second delay clock. And the absolute value of the time difference between the delay time indicated by the value of the first delay time setting signal and the cycle of the fixed clock is the delay time indicated by the value of the second delay time setting signal and the cycle of the fixed clock. If it is smaller than the absolute value of the time difference from the first delay clock, if it is larger, a clock switching determination unit that outputs a clock selection signal that specifies the second delay clock, and based on the clock selection signal A clock selection unit that selects one of the first delayed clock and the second delayed clock and outputs the selected clock as the reproduced symbol clock; and the second delayed clock with respect to the second delayed clock. A clock phase comparison unit that detects whether one delayed clock phase is advanced or delayed and outputs detection information as a phase detection signal, and the phase detection signal is averaged. And an averaging unit that outputs an averaged phase detection signal, accumulates the averaged phase detection signals, adds a time corresponding to this accumulated value, and a fixed clock cycle, and outputs the corrected delay value. A timing recovery circuit having an output error value accumulating section. 9. Based on the timing phase error signal, a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the transmission <br/> signal side, the phase control unit, A π phase shifter that outputs a π phase-shifted signal of a fixed clock in radians as a π phase-shifted clock.
One of the phase-shifted clocks is used as the comparison clock,
The other one is used as the phase-shifting clock, and the clock switching unit that outputs each is cumulatively added to the timing phase error signal, and the surplus value when the value after the cumulative addition is divided by the time corresponding to one cycle of the fixed clock is calculated. A cumulative addition unit that outputs a delay time setting signal, and a signal obtained by delaying the phase shift clock by the set time by the delay time setting signal, using the delayed signal as a reproduction clock, and dividing the reproduction clock by two. And a first phase-dividing unit that divides the comparison clock by two and outputs the divided clock as a comparison two-division clock, The reproduction clock is divided by two, and the divided clock divided by two is output as a reproduction clock divided by two, and the comparison division clock is divided by two. When the sampling is performed by a frequency clock and the sampled data changes, a reset signal for resetting the cumulative addition value in the cumulative addition unit to 0 at the time of the change, and a logic "1" at the time of the change, And a clock switching signal output section for outputting a clock selection signal for switching "0". 10. Based on the timing phase error signal ,
Sending a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the signal side, the phase control unit, a fixed clock and [pi phase shift in radians signal, [pi phase shift clock And a π phase shifter that outputs a fixed clock and
One of the phase-shifted clocks is used as the comparison clock,
The other one is used as the phase-shifting clock, and the clock switching unit that outputs each is cumulatively added to the timing phase error signal, and the surplus value when the value after the cumulative addition is divided by the time corresponding to one cycle of the fixed clock is calculated. A cumulative addition unit that outputs a delay time setting signal, and the delay time setting signal delays the phase shift clock by a set time, and uses the delayed signal as a reproduction clock and the reproduction clock as the reproduction symbol clock. A clock phase shifter for outputting, a first divide-by-two divider for dividing the comparison clock by two and outputting the divided clock as a divide-by-two clock for division, and the divided clock for dividing the reproduced clock by two. A second divide-by-two division unit that outputs a clock divided by two as a reproduced divide-by-two clock, and the comparison divided-by-two divide-by-clock with the reproduced divide-by-two clock. When the ringed and sampled data changes, a reset signal for resetting the cumulative addition value in the cumulative addition unit to 0 at the time of the change, and a logical "1" and a logical "0" at the time of the change. And a clock switching signal output section that outputs a clock selection signal that switches the timing recovery circuit. 11. The clock phase shifter delays the fixed clock in y time steps from time y to time y × (N−1) to generate (N−1) delay clocks, A delay clock group generation unit that outputs N clocks including the fixed clock and the N clocks as a delay clock group; and a clock selection signal that is generated based on the delay time setting signal. And a clock selection signal generation unit that outputs the delayed clock group, and a clock selection unit that selects one of the delayed clock groups based on the clock selection signal and outputs the selected delayed clock group as a delayed clock. And N delay units for giving a delay time y in the delay element, and the fixed clock is input to the N delay units connected in series to generate N delay clocks. The timing recovery circuit of claim 10 Symbol mounting that. 12. Based on the timing phase error signal ,
Sending a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the signal side, the phase control unit, the timing phase error signal by accumulating, below a value after the cumulative addition A cumulative addition unit that outputs a surplus value when divided by a time corresponding to one cycle of the local sine wave as a delay time setting signal, and a value indicated by the delay time setting signal in a phase with respect to the cycle of the local sine wave described below. The cosine value in the case of notation, the sine value is obtained, the cosine data and the cosine / sine conversion unit which outputs as sine data respectively, the cosine data and the sine data are quadrature-modulated by a local sine wave, and quadrature-modulated Output signal as a timing reproduction signal, two DA converters, two low-pass filters, two multipliers, one adder A quadrature modulation unit configured by one π / 2 phase shifter, and a hard decision unit that performs a hard decision on the timing reproduction signal and outputs a signal obtained by dividing the data after the hard decision by two as the reproduction symbol clock. And a timing recovery circuit. 13. Based on the timing phase error signal ,
Sending a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the signal side, the phase control unit, the timing phase error signal by accumulating, below a value after the cumulative addition A cumulative addition unit that outputs a surplus value when divided by a time corresponding to one cycle of the local sine wave as a delay time setting signal, and a value indicated by the delay time setting signal in a phase with respect to the cycle of the local sine wave described below. The cosine value in the case of notation, the sine value is obtained, the cosine data and the cosine / sine conversion unit which outputs as sine data respectively, the cosine data and the sine data are quadrature-modulated by a local sine wave, and quadrature-modulated Output signal as a timing reproduction signal, two DA converters, two low-pass filters, two multipliers, one adder It has a quadrature modulation section composed of one π / 2 phase shifter, and a hard decision section for making a hard decision on the timing reproduction signal and outputting the data after the hard decision as the reproduction symbol clock. Timing reproduction circuit. 14. Based on the timing phase error signal ,
Sending a phase control unit that Gyosu phase system so as to phase lock the recovered symbol clock to the transmission timing of the signal side, the phase control unit, the timing phase error signal by accumulating, below a value after the cumulative addition A cumulative addition unit that outputs a surplus value when divided by the time corresponding to one cycle of the fixed clock as a delay time setting signal, and the value indicated by the delay time setting signal is described in the phase with respect to the cycle of the fixed clock described below. In this case, the cosine value and the sine value are obtained, the cosine data and the sine data are respectively output as cosine data and sine data. When the logic of the fixed clock is “1”, the cosine data is output as it is, and the fixed clock theory is generated. Is “0”, a first sign inversion unit that multiplies the cosine data by “−1” and outputs the result; and if the logic of the fixed clock is “1”, outputs the sine data as it is, If the logic of the fixed clock is “0”, the second sign inversion unit that multiplies the sign data by “−1” and outputs the result; and if the double fixed clock has the logic “1”, the first sign A clock amplitude that outputs the output value of the sign inverting unit as quadruple reproduction timing data, and outputs the output value of the second sign inverting unit as quadruple timing reproduction data when the doubling fixed clock is logical "0". A value selection section, a DA conversion section which DA-converts the 4 times timing reproduction data and converts it into an analog timing signal, and a signal from which the analog timing signal is low-pass filtered to remove a harmonic component. A timing reproduction circuit comprising: an analog low-pass filtering unit that outputs a timing reproduction signal; and a hard decision unit that makes a hard decision on the timing reproduction signal and outputs the data after the hard decision as the reproduction symbol clock. 15. The timing according to claim 2, wherein the baseband phase data oversampled at twice the symbol rate is input, and a regenerated symbol clock phase-synchronized with the transmission timing on the transmission side is output. The playback circuit and the PSK-modulated received IF signal are complex-multiplied by a local signal having the same frequency as the IF signal, and the in-phase component after the complex multiplication and the quadrature component after the complex multiplication are low-pass filtered to obtain the same baseband signal. A quadrature detection unit that outputs a phase signal and a baseband quadrature signal, the baseband in-phase signal, and the baseband quadrature signal are oversampled at a timing twice as high as the symbol rate synchronized with the reproduced symbol clock. Outputs baseband in-phase data and baseband quadrature data. A pulling unit, the baseband in-phase data and the baseband quadrature data are converted into polar coordinates, and the polar coordinate conversion unit outputs the data after the polar coordinate conversion as baseband phase data; And a data determination unit that determines the demodulated data from the latched phase data and outputs the determined demodulated data. 16. A regenerated symbol clock that is phase-synchronized with the transmission timing on the transmission side is output, and a symbol rate of 2 is output.
6. The recovered symbol clock is generated from the fixed clock having a frequency doubled or the local sine wave having a frequency twice the symbol rate, claim 5, claim 7, claim 9, claim 11, claim 14, And the timing recovery circuit according to claim 16, an amplitude limiting unit that limits the amplitude of the PSK-modulated reception IF signal, and a local signal having the same frequency as the IF signal in the amplitude-limited reception IF signal. And a quadrature detection unit that low-pass filters the in-phase component after complex multiplication and the quadrature component after complex multiplication, and outputs as a baseband in-phase signal and a baseband quadrature signal, respectively, the baseband in-phase signal and the A baseband quadrature signal is sampled by the recovered clock, and baseband in-phase data and baseband quadrature are respectively sampled. A sampling unit that outputs as a data, the baseband in-phase data, the baseband quadrature data is subjected to polar coordinate conversion, the polar coordinate conversion unit that outputs the data after polar coordinate conversion as baseband phase data, the reproduction symbol clock, A demodulator comprising: a data determination unit that latches the baseband phase data, determines demodulated data from the latched phase data, and outputs the demodulated data. 17. A regenerated symbol clock that is phase-synchronized with the transmission timing on the transmission side is generated, and the regenerated symbol clock is generated from the fixed clock having the same frequency as the symbol rate or the local sine wave having the same frequency as the symbol rate. 請 Motomeko 6 you, claim 8, claim 1
0 , and the timing recovery circuit according to claim 13 , an amplitude limiting unit that limits the amplitude of the PSK-modulated reception IF signal, and the amplitude-restricted reception IF signal has the same frequency as the IF signal. A quadrature detection unit for complex-multiplying the local signal, low-pass filtering the in-phase component after the complex multiplication and the quadrature component after the complex multiplication, and outputting as a baseband in-phase signal and a baseband quadrature signal, respectively. And a sampling unit that samples the baseband quadrature signal at the rising and falling edges of the reproduction symbol clock and outputs baseband in-phase data and baseband quadrature data, respectively, the baseband in-phase data, and the baseband quadrature. Data is converted to polar coordinates and the data after polar conversion is It has a polar coordinate conversion unit that outputs as phase data, and a data determination unit that latches the baseband phase data with the reproduction symbol clock, determines demodulated data from the latched phase data, and outputs the demodulated data. Demodulator.