JP3489417B2 - A / D converter and A / D conversion method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D (analog / digital) conversion device for converting an analog signal into a digital signal and a conversion method thereof, and more particularly to a ΔΣ type A
The present invention relates to improvement of noise characteristics of a / D conversion circuit.

[0002]

2. Description of the Related Art As one of A / D converters, a ΔΣ type A
An A / D conversion device using an A / D conversion circuit has been proposed. For example, there is an A / D conversion circuit and the like as disclosed in "JP-A-2-126727". Hereinafter, an A / D conversion device using a conventional ΔΣ type A / D conversion circuit will be described.

FIG. 5 is a block diagram showing the structure of a conventional A / D converter. 50 is a ΔΣ type A / D conversion circuit, 5
Reference numeral 1 is an analog subtractor, 52 is an integrator, 53 is a quantizer for quantizing an input signal into 1 bit, 54 is a D-type flip-flop (hereinafter referred to as DFF), and 55 is a D / A converter.

FIG. 6 is a block diagram showing the structure of the integrator 52. In FIG. 6, reference numeral 56 is an analog adder, and 57
Is a delay device that delays by one sampling period. The input signal from the analog subtractor 51 is the analog adder 56.
The output signal is output to the quantizer 53 via the delay unit 57 and is positively fed back to the analog adder 56 via the delay unit 57.
That is, the input signals are cumulatively added for each sampling cycle, and the transfer characteristic Hi (z) thereof is expressed by a Z function as shown in (Equation 1).

Hi (z) = 1 / (1-z ⁻¹ ) (Equation 1) where z = cos θ−j · sin θ j: imaginary number unit Conventional A / D conversion configured as above The operation of the device will be described below with reference to FIGS. The analog input signal is input to the integrator 52 via the analog subtractor 51, cumulatively added by the analog adder 56 in the integrator 52, and then added by the quantizer 53 at every sampling cycle.
It is quantized into a binary (1 bit) digital signal of 1 and -1. The quantized digital signal is output as a digital output signal and also input to the D / A converter 55 via the DFF 54 and converted into a binary (1 bit) analog signal of + Vt and -Vt. After that, it is fed back to the analog subtractor 51.

When the analog input signal of the ΔΣ type A / D conversion circuit 50 is X, the digital output signal is Y, and the quantization error (difference between input and output of the quantizer 53) generated by the quantizer 53 is Vqn. , The input / output relationship is described by a Z function as shown in (Equation 2).

Y = X + (1-z ⁻¹ ) Vqn (Equation 2) As is clear from (Equation 2), the digital output signal Y includes the quantization error Vqn in addition to the analog input signal component X. Although the term is included, the noise due to Vqn decreases as the frequency becomes low because it is multiplied by the first-order differential characteristic (1-z ^-1 ), and even if the quantization is only 1 bit, it has a wide dynamic range in the low frequency region. Can be obtained.

In order to obtain a wider dynamic range, the sampling period is made shorter (the sampling frequency is made higher) than the digital output signal to be obtained, and the A / D
A conversion may be performed and the output digitally processed to use only the low frequency region. Therefore, this method is also called an oversampling method and is widely applied particularly in the field of digital audio.

[0009]

However, in the conventional structure as described above, when a DC component (DC voltage) is applied to the analog input signal, the digital output signal has a characteristic of having periodicity. There is a problem that a specific frequency component (idle tone) appears in Vqn which is (white) noise having no frequency characteristic.

The principle of occurrence of this problem will be briefly described with reference to FIG. FIG. 7 is a waveform diagram of the input signal and the output signal of the quantizer 53 of the ΔΣ type A / D conversion circuit 50.

First, when the DC component Vdc is input to the ΔΣ type A / D conversion circuit 50, it is cumulatively added by the integrator 52 and input to the quantizer 53. In the quantizer 53, when the input signal exceeds a predetermined threshold value, the output signal is inverted and fed back to the analog subtractor 51, so that the input waveform of the quantizer 53 becomes a sawtooth wave as shown in FIG. The output waveform is a pulse train.

The pulse interval at this time is a fixed cycle determined by the ratio of the input DC component Vdc and the quantized output Vt, and the cycle t ₀ is expressed by (Equation 3).

T ₀ = Ts × Vt / Vdc (Equation 3) However, Vdc: DC component (DC voltage) Ts: Sampling period Since the pulse train has a constant period t _{0 in} this way, the digital output signal has Noise of the fundamental frequency 1 / t ₀ and its integral multiples (harmonics) appears. This is generally called an idle tone. This idle tone does not appear if there is no DC component in the input signal, but it is extremely difficult to completely remove the DC component from the analog input signal, and the DC component of the circuit of the A / D conversion device itself has The impact is also difficult to avoid.

The simplest method for avoiding this idle tone is to add the DC component Vdc so that the frequency of the idle tone obtained by (Equation 3) is outside the desired signal band.

As described above, in the ΔΣ type A / D conversion circuit,
Since the low frequency region where a wide dynamic range can be obtained is used as the signal band, it is sufficient if the basic frequency 1 / t ₀ of the idle tone is higher than the upper limit frequency of this signal band.

However, if this means is simply used, the digital output signal naturally contains the added DC component Vdc, and a problem arises in that a digital process for removing this DC component Vdc is additionally required.
In order to remove the DC component Vdc contained in the digital output signal, it is necessary to first find its DC value. However, if the DC value is obtained and removed only from the digital output signal, the DC component contained in the original analog input signal. Will be removed. It is also possible in principle to obtain a direct current value contained in the digital output signal in advance from the ratio of the direct current component Vdc to be added and the quantized output Vt, and remove it, but this is a manufacturing error and temperature drift of the analog circuit. Therefore, it is not easy to remove the DC component with sufficient accuracy. It is even more difficult in view of the current situation where various means are taken to remove the DC component of the A / D conversion circuit itself.

The present invention solves the above-mentioned conventional problems. It avoids idle tones by adding a DC component to an analog input signal, and adds a DC component to an output digital output signal. It is an object of the present invention to provide an A / D conversion device that does not contain components.

[0018]

Means for Solving the Problems First A / according to the present invention
The D conversion device converts an analog signal into a positive-phase signal and a negative-phase signal, and then adds the same DC component to the positive-phase signal and the negative-phase signal, and a positive-phase signal output from the balanced circuit. A first ΔΣ-type A / D conversion circuit that receives a signal, a second ΔΣ-type A / D conversion circuit that receives a negative-phase signal output from the balancing circuit, and the first and second And a digital subtraction means for subtracting the digital signal output from the ΔΣ type A / D conversion circuit, wherein the first and second ΔΣ type A / D conversion circuits have the same circuit configuration. .

According to the first configuration, after converting the analog signal into the positive phase signal and the negative phase signal, the same DC component is added to the positive phase signal and the negative phase signal, and then A / D conversion is performed. As a result, the frequency of the idle tone component included in the output of the A / D conversion circuit falls outside the predetermined signal band,
Idle tones (noise) can be avoided. Moreover, since the DC component added to the positive phase signal and the negative phase signal is canceled by the subtraction processing by the digital subtraction means, it is possible to obtain a digital output signal that does not include the added DC component.

In a second A / D converter according to the present invention, the first A / D converter is the first and second ΔΣ type A converters.
An analog subtracting means for subtracting the analog signal of the quantization error component output from the / D conversion circuit, and a third inputting the analog signal output from the analog subtracting means
Of the ΔΣ-type A / D conversion circuit and the digital signal output from the third ΔΣ-type A / D conversion circuit as an input, and differentiating means for differentiating the digital signal, and output from the digital subtracting means and the differentiation. And a digital adding means for adding the output from the means.

According to the second configuration, the first ΔS-type A / D conversion circuit, the differentiating means, the analog subtracting means, and the digital adding means are added to the first configuration.
A / D having second-order differential characteristics in addition to the effects of the configuration
A conversion circuit can be configured.

A third A / D converter according to the present invention is the same as the second A / D converter, except that the fourth to nth ΔΣ A / D converters are used.
The fourth to nth ΔΣ A / D conversion circuits are respectively connected to the conversion circuit and the outputs of the fourth to nth ΔΣ A / D conversion circuits, and the fourth to nth ΔΣ A
A fourth to nth differentiating means for differentiating the digital signal output from the D / D conversion circuit to a predetermined differentiating characteristic (n ≧ 4 integer), and the fourth to nth ΔΣ type A / D
The conversion circuit receives the analog signals of the quantization error components output from the third to (n−1) th ΔΣ A / D conversion circuits as inputs, and outputs the signals from the fourth to nth differentiating means. It is characterized in that the output is input to the digital adding means to perform addition processing.

According to this third configuration, the second A /
The D converter includes a ΔΣ type A / D conversion circuit and the ΔΣ type A / D.
A circuit having a third-order differential characteristic can be configured by adding one set of the differentiating means for the conversion circuit and a circuit having a fourth-order differential characteristic by adding two sets. That is, if (n-3) sets of circuits including the 4th to nth ΔΣ A / D conversion circuits and the 4th to nth differentiating means are added, in addition to the effects of the second configuration. (N-
1) An A / D conversion circuit having a second derivative characteristic can be constructed.

The balance circuit of any of the first to third A / D converters converts the analog input signal and outputs a positive-phase signal and a negative-phase signal, and the positive-phase signal and the direct-current signal. A first analog addition means for performing addition processing with the component and outputting to the first ΔΣ type A / D conversion circuit, and a second ΔΣ type A with addition processing for the negative phase signal and the DC component. And a second analog adding means for outputting to the / D conversion circuit.

By using this balanced circuit, the same DC component can be added to the positive phase signal and the negative phase signal by the analog adding means after the analog signal is converted into the positive phase signal and the negative phase signal. At this time, the DC component superimposed on the analog input signal is A / D-converted as it is, included in the digital output signal, and output.

Further, any one of the balanced circuits of the first to third A / D converters has a capacitor for inputting an analog input signal and an output from the capacitor as an input of an inverting input terminal, and a DC component is generated. A first inverting amplifier circuit having a first operational amplifier as an input to the non-inverting input terminal, and an output from the first inverting amplifier circuit as an input to the inverting input terminal, and a DC component that is the same as the DC component is generated. A second inverting amplifier circuit having a second operational amplifier as an input to the non-inverting input terminal, wherein the first and second inverting amplifier circuits have the same circuit configuration, and the first inverting amplifier circuit It is characterized in that the circuit outputs a negative-phase signal added with a DC component, and the second inverting amplifier circuit outputs a positive-phase signal added with a DC component. Further, the input resistance and the feedback resistance incorporated in the first and second inverting amplifier circuits have the same resistance value.

When this balanced circuit is used, the DC component superimposed on the analog input signal is removed by the capacitor, and the normal phase signal and the negative phase signal are the same with a simple circuit configuration without using an adder. The direct current component of can be added. Therefore, after A / D conversion, a digital output signal having only an AC component that does not include the DC component that has been superimposed on the analog input signal can be obtained.

The A / D conversion method of the A / D conversion apparatus according to the present invention is the same as the A / D conversion method in the A / D conversion apparatus having the ΔΣ type A / D conversion circuit. After converting to a negative phase signal and adding the same direct current component to each of the positive phase signal and the negative phase signal, A /
It is characterized in that the added DC component is removed by performing D conversion and performing a subtraction process of the A / D converted positive phase signal and negative phase signal.

According to this A / D conversion method, an analog signal is converted into a positive-phase signal and a negative-phase signal, the same DC component is added to the positive-phase signal and the negative-phase signal, and then A / D-converted. Therefore, the frequency of the idle tone component included in the A / D converted output is outside the predetermined signal band, and the idle tone can be avoided. Moreover, since the DC component added to the positive-phase signal and the negative-phase signal is canceled by the subtraction process before obtaining the digital output signal, it is possible to obtain a digital output signal that does not include the added DC component.

Further, in the above A / D conversion method, the direct current component superimposed on the analog input signal is removed by a capacitor, and then the analog input signal is converted into a positive phase signal and a negative phase signal.

According to this A / D conversion method, the DC component superimposed on the analog input signal is removed by the capacitor, and after the A / D conversion, the DC component superimposed on the analog input signal is not included. A digital output signal of only the AC component is obtained.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of an A / D converter according to Embodiment 1 of the present invention. In FIG. 1, 1 and 2 are ΔΣ type A / D conversion circuits having the same circuit configuration, 3 is a balanced circuit, and 4 is a digital subtractor. The ΔΣ A / D conversion circuits 1 and 2 are blocks having the same configuration and function as the A / D conversion circuit 50 shown in FIG. The balance circuit 3 adds a positive-phase (in-phase) signal of an analog input signal and an inverting amplifier circuit 5 that outputs a negative-phase signal whose sign is inverted, and a positive-phase signal and a DC component Vdc to perform ΔΣ A / D conversion. Analog adder 6 for output to circuit 1
And the negative-phase signal and the DC component Vdc are added to obtain a ΔΣ type A / D
It is composed of an analog adder 7 for outputting to the conversion circuit 2. The digital subtractor 4 subtracts the outputs from the ΔΣ type A / D conversion circuit 1 and the ΔΣ type A / D conversion circuit 2 and outputs the result.

An example of the operation of the A / D conversion device of the first embodiment having the above-described structure will be described below.

First, the analog input signal is converted into a positive phase signal and a negative phase signal by the inverting amplifier circuit 5 of the balancing circuit 3, and then the positive phase signal and the DC component Vdc are added by the analog adder 6, and In the adder 7, the negative phase signal and the DC component Vdc are added.

Therefore, if the analog input signal is X, Δ
The positive phase signal input to the Σ-type A / D conversion circuit 1 is (X + V
dc), and the negative phase signal input to the ΔΣ type A / D conversion circuit 2 is (−X + Vdc). These signals are
After being converted into a digital signal by the Σ-type A / D conversion circuit 1 and the ΔΣ-type A / D conversion circuit 2, the digital signal is output to the digital subtractor 4. Since the input signal is subtracted by the digital subtractor 4, the signal component of the digital output signal is canceled by the DC component Vdc added by the balance circuit 3 as is clear from (Equation 4) and is included in the output. Will not stop.

(X + Vdc) − (− X + Vdc) = 2X (Equation 4) Moreover, even if the DC component Vdc fluctuates due to a manufacturing error, temperature drift, or the like, it is opposite to the positive phase signal output from the balancing circuit 3. Since the same DC component Vdc is included in the phase signal, it does not affect the cancellation of the DC component processed by the digital subtractor 4.

In the first embodiment, the balanced circuit 3 is used.
As described above, the circuit composed of the inverting amplifier circuit 5 and the analog adders 6 and 7 is used. However, after the analog input signal is converted into the positive phase signal and the negative phase signal as described above, the positive phase signal and the negative phase signal are converted. Similar effects can be obtained as long as the conversion means has a function of adding the same DC component to each signal and outputting the result.

(Second Embodiment) Next, an A / D conversion device according to a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing the configuration of the balanced circuit according to the A / D converter of the second embodiment. By using the balance circuit 12 shown in FIG. 2 instead of the balance circuit 3 in the first embodiment shown in FIG. 1, when the direct current component included in the analog input signal is unnecessary, without using an adder,
The same DC component can be easily added to the positive phase signal and the negative phase signal.

In FIG. 2, 13 and 14 are operational amplifiers (operational amplifiers), 15 and 16 are input resistors, 17 and 18 are feedback resistors, and 19 is a capacitor. Input resistance 1
The resistors 5 and 16 and the feedback resistors 17 and 18 are resistors having the same resistance value R.

The balance circuit 12 includes a first inverting amplifier circuit 20 composed of an operational amplifier 13, an input resistor 15 and a feedback resistor 17, and a second inverting amplifier circuit composed of an operational amplifier 14, an input resistor 16 and a feedback resistor 18. The inverting amplification circuit 21 is connected in series, and the analog input signal is given to the first inverting amplification circuit 20 via the capacitor 19. The same DC component Vdc is input to the non-inverting input terminals of the operational amplifiers 13 and 14.

With the above configuration, the first inverting amplifier circuit 2
A negative phase signal is output as an output signal from 0, and
It is input as an input signal of the second inverting amplifier circuit 21 connected in series, and the positive phase signal is output from the second inverting amplifier circuit 21 as an output signal.

An example of the operation of the balanced circuit 12 according to the second embodiment having the above configuration will be described below.

The input resistor 15 and the feedback resistor 17 of the first inverting amplifier circuit 20 and the input resistor 16 and the feedback resistor 18 of the second inverting amplifier circuit 21 are resistors having the same resistance value R. The amplification factor (gain) is "1". Further, since the analog input signal is input to the first inverting amplifier circuit 20 via the capacitor 19, the DC component superimposed on the analog input signal is removed by the capacitor 19, and the analog input signal of the analog input signal output from the capacitor 19 is removed. When the AC component is Xo, the positive-phase signal output and the negative-phase signal output become the signals shown in (Equation 5), and the DC component Vdc can be added equally to the AC component Xo of the analog input signal.

Positive phase signal output = + Xo + Vdc (Equation 5) Reverse phase signal output = −Xo + Vdc In the second embodiment, the same amplification factor is set to “1” for the sake of simplicity. However, different circuit configurations may be used as long as they do not impair the function of adding the same DC component as described above. For example, the gain can be changed by changing the resistance value of the resistor 15, and the frequency characteristic can be given by connecting a capacitor in parallel with any of the resistors.

In the above description of the first and second embodiments, the accuracy of each analog element and the DC component of the operational amplifier are neglected, but in reality, these factors are the cause. Thus, the digital output signal contains a DC component. In particular, in operational amplifiers of CMOS integrated circuits, DC components generated due to manufacturing errors and temperature drift cannot be ignored.
When configuring an A / D converter with an OS type integrated circuit, it is almost essential to remove the DC component by digital processing. However, if analog elements are formed close to each other on the same integrated circuit, it is possible to obtain relative accuracy far higher than absolute accuracy. Utilizing this feature, if the above-mentioned ΔΣ type A / D conversion circuit 1, ΔΣ type A / D conversion circuit 2 and balanced circuit 3 or balanced circuit 12 are arranged close to each other on the same integrated circuit, they will be generated by analog elements. The direct current components to be performed are very close in relative value, and can be accurately canceled by the digital subtractor 4.

(Embodiment 3) In the A / D converter shown in FIG. 5, the differential characteristic multiplied by Vqn is a primary characteristic as shown in (Equation 2), and the noise suppression amount in the low frequency region is not always required. Since this is not sufficient, generally a circuit having a third to fourth order differential characteristic is used. Needless to say, the circuit configuration of the third to fourth order differential characteristics becomes complicated and large-scaled as compared with the circuit configuration of the first order differential characteristics. Therefore, if a circuit that uses two identical ΔΣ-type A / D conversion circuits as shown in FIG. 1 and that simply obtains a differential characteristic equal to or higher than the second-order characteristic, the circuit scale becomes double or more. . Therefore, in the A / D conversion device of the third embodiment, a circuit configuration in which the A / D conversion device shown in FIG. 1 is used as a basic circuit and a differential characteristic of second order or higher is obtained by adding a small number of circuits is adopted. provide.

FIG. 3 shows A / A according to the third embodiment of the present invention.
It is a block diagram which shows the structure of a D converter. 3, blocks having the same configurations and functions as those in FIG. 1 are designated by the same reference numerals. Reference numerals 1, 2, and 8 are ΔΣ type A / D conversion circuits having the same circuit configuration, 3 is a balanced circuit, 4 is a digital subtractor, 9 is a differentiator, 10 is an analog subtractor, and 11 is a digital adder. The balance circuit 3 adds the positive phase signal and the direct current component Vdc to the inverting amplifier circuit 5 that outputs a positive phase (in-phase) signal of the analog input signal and a negative phase signal whose sign is inverted as in FIG. Analog adder 6 for outputting to the ΔΣ type A / D conversion circuit 1, the negative phase signal and the DC input Vdc
And an analog adder 7 for adding and outputting to the ΔΣ A / D conversion circuit 2.

The ΔΣ type A / D conversion circuits 1, 2 and 8 convert the analog signals input to the respective circuits into digital signals under the same sampling clock and output the digital signals.
At the same time, the quantization error component (the difference between the input and output of the quantizer 53) is output as analog signals Vq1, Vq2, Vq8 (Vq8 is not shown). The digital subtractor 4 is a ΔΣ type A
The digital output signals output from the / D conversion circuit 1 and the ΔΣ type A / D conversion circuit 2 are input, subjected to subtraction processing, and then output to the digital adder 11. Analog subtractor 10
Is a ΔΣ type A / D conversion circuit 1 and a ΔΣ type A / D conversion circuit 2
Analog signals Vq1 and V of the quantization error component output from
It receives q2 as an input, performs subtraction processing, and then outputs it to the ΔΣ type A / D conversion circuit 8. The differentiator 9 receives the digital output signal output from the A / D conversion circuit 8 as input, performs ideal first-order differentiation, and then outputs it to the digital adder 11.

FIG. 4 is a block diagram showing the configuration of the differentiator 9 according to the present invention. In FIG. 4, 22 is a digital subtractor and 23 is a DFF. ΔΣ type A / D conversion circuit 8
From the input signal directly input to the digital subtractor 22 via the DFF 23, and then to the digital subtractor 22. Is subtracted and output to the digital adder 11. The transfer characteristic Hd of the differentiator 9 is expressed by (Equation 6) using the Z function.

Hd (z) = 1−z ⁻¹ (Equation 6) In the A / D converter of FIG. 3, the balanced circuit 3 and the ΔΣ type A
The operations and functions up to the A / D conversion circuit 1, the ΔΣ A / D conversion circuit 2, and the digital subtractor 4 are the same as those of the A / D conversion circuit 50 shown in FIG.
The digital output signal Y _{1 from} is as in (Equation 7).

Y ₁ = 2X + (1-z ^-1 ) (Vq1-Vq2) (Equation 7) Further, the digital output signal Y ₂ from the ΔΣ type A / D conversion circuit 8 is as shown in (Equation 8). become.

Y ₂ = (Vq 1 −Vq ₂ ) + (1−z ⁻¹ ) Vq 8 (Equation 8) Further, the digital output signal Y ₂ from the ΔΣ type A / D conversion circuit 8 has the differentiator 9 It is output to the digital adder 11 via the digital adder 11 and added to the digital output signal Y ₁ from the digital subtractor 4 to form a digital output signal Y ₃ . Therefore, from (Equation 6), (Equation 7), and (Equation 8), the digital output signal Y ₃ is represented by (Equation 9).

Y ₃ = Y ₁ + Hd × Y ₂ = 2X + (1−z ⁻¹ ) ² Vqn (Equation 9) That is, as shown in (Equation 9), A having a secondary characteristic is obtained.
A / D converter can be obtained. In this way, the addition of a small number of circuits to the A / D conversion circuit 50 of FIG.
It is possible to realize an A / D conversion device having a second-order differential characteristic.

Therefore, the digital signal output obtained by subtracting the outputs from the ΔΣ type A / D conversion circuit 1 and the ΔΣ type A / D conversion circuit 2 by the digital subtractor 4 is Δ
If the technical idea of adding the digital output signals obtained by the Σ-type A / D conversion circuit 8 and the differentiator 9 to obtain the digital output signal of the second-order differential characteristic is developed, it is possible to easily add 3 circuits by adding a small number of circuits. A digital output signal having a second derivative characteristic can be obtained.

For example, a circuit configuration for obtaining a digital output signal having a third-order differential characteristic will be briefly described. In the A / D converter of FIG. 3, a ΔΣ-type A / D conversion circuit for a third-order characteristic and a third-order characteristic are used. Add one set of circuits consisting of characteristic differentiator
The quantization error output Vq8 of the type A / D conversion circuit 8 is input to the ΔΣ type A / D conversion circuit for the third-order characteristic and the ΔΣ type A / D for the third-order characteristic is input.
The output from the D conversion circuit is output to the digital adder 11 via the third-order characteristic differentiator to perform addition processing. Since the third-order characteristic differentiator needs to obtain the second-order differential characteristic in order to cancel the term of the quantization error Vq8 included in the digital output signal of the differentiator 9, the second-order differentiator shown in FIG. It is configured by connecting them in series.

That is, in the A / D converter of FIG.
A type A / D conversion circuit and a differentiator for the conversion circuit as one set of circuits, a circuit having a third-order differential characteristic is formed by adding one set, and a circuit having a fourth-order differential characteristic by adding two sets Can be configured. Therefore, the fourth to nth ΔΣ type A
/ D conversion circuit and (n-3) sets of circuits consisting of fourth to nth differentiating means are added, and outputs from the (n-3) sets of conversion circuits are input to the digital adder 11 for addition. If processed, an A / D conversion circuit having an (n-1) th order differential characteristic can be configured (an integer of n ≧ 4).

In the third embodiment, the ΔΣ type A / D
Although the A / D conversion circuit shown in FIG. 5 has been used as the conversion circuits 1, 2, and 8 to describe the same circuit, the gist of the present invention is to perform subtraction processing on the outputs of the ΔΣ type A / D conversion circuits 1 and 2. This is to cancel the DC component, and the ΔΣ type A / D conversion circuits 1 and 2 may be the same circuit, and the ΔΣ type A / D conversion circuit for obtaining the secondary characteristic or higher is not limited to this. For example, the ΔΣ A / D conversion circuit 8 may be a double integration circuit.

When the DC component contained in the analog input signal is unnecessary in the third embodiment, the balance circuit 1 shown in FIG. 2 is used instead of the balance circuit 3 as in the second embodiment.
2 may be used.

[0061]

As described above, according to the A / D converter and the A / D conversion method of the present invention, the idle tone is effectively avoided and added by adding the DC component to the analog input signal. Since the generated DC component is canceled and removed by the subtraction process before obtaining the digital output signal, it has an excellent feature that the added DC component is not included in the output digital output signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an A / D conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a balanced circuit of an A / D conversion device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an A / D conversion device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a differentiator 9 in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional A / D conversion device.

6 is a block diagram showing a configuration of an integrator 52 in FIG.

7 is a waveform diagram of input signals and output signals of the quantizer 53 in FIG.

[Explanation of symbols]

1, 2, 8 ΔΣ type A / D conversion circuit 3, 12 Balance circuit 4 Digital subtractor 5 Inverting amplification circuit 6, 7 that outputs a positive phase (in-phase) signal and a negative phase signal Analog adder 9 Differentiator 10 Analog subtraction Device 11 Digital adder 13, 14 Operational amplifier 15, 16 Input resistor 17, 18 Feedback resistor 19 Capacitor 20, 21 Inverting amplifier circuit 22 Digital subtractor 23 DFF

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-9-153812 (JP, A) JP-A-6-53836 (JP, A) JP-A-7-106975 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03M 3/02 H03M 1/12

Claims (5)

(57) [Claims] 1. An analog signal is converted into a positive phase signal and a negative phase signal.
Then, the same direct signal is added to the positive-phase signal and the negative-phase signal.
The balance circuit for adding the flow components and the output from the balance circuit.
First delta-sigma A / D conversion circuit that receives a positive-phase signal that is input
And the negative phase signal output from the balance circuit is input
A second ΔΣ type A / D conversion circuit, and the first and second
The digital signal output from the ΔΣ type A / D conversion circuit
Digital subtraction means for performing subtraction processing, and first and second
Of the quantization error component output from the ΔΣ type A / D conversion circuit
Analog subtraction means for subtracting an analog signal;
The analog signal output from the analog subtraction means is input
And a third ΔΣ type A / D conversion circuit for
The digital signal output from the A / D conversion circuit is input
A differentiating means for differentiating the digital signal,
The output from the subtractor and the output from the differentiator.
It has a digital adding means for performing arithmetic processing.
A / D converter to collect. 2. A fourth to nth ΔΣ type A / D conversion circuit,
The outputs of the fourth to nth ΔΣ type A / D conversion circuits are respectively provided.
The fourth to nth ΔΣ type A / D conversion circuits connected to this
Differentiate the digital signal output from the
And fourth to n-th differentiating means (n ≧ 4
Is an integer), and the fourth to nth ΔΣ A / D conversion circuits are
Output from the 3rd to (n-1) th ΔΣ A / D conversion circuits.
Input the analog signal of the quantization error component
Then, the output from the fourth to nth differentiating means is digitized.
It is characterized in that the addition processing is performed by inputting to the tar addition means.
The A / D conversion device according to claim 1. 3. A balance circuit converts the analog input signal.
Converting the positive phase signal and the negative phase signal to output a positive phase signal
The first ΔΣ A / D is obtained by adding the signal and the DC component.
A first analog addition means for outputting to the conversion circuit;
The second ΔΣ type is obtained by adding the phase signal and the DC component.
With the second analog addition means for outputting to the A / D conversion circuit
It is comprised, either of Claims 1-2 characterized by the above-mentioned.
The A / D converter according to claim 1. 4. The balance circuit inputs an analog input signal.
Capacitor and the output from the capacitor is inverted
The input is to the terminal and the DC component is the input to the non-inverting input terminal.
A first inverting amplifier circuit having a first operational amplifier,
The output from the first inverting amplifier circuit is used as the input of the inverting input terminal.
The same DC component as the DC component of the non-inverting input terminal
Second inverting amplifier circuit having second operational amplifier for input
And the first and second inverting amplifier circuits are the same
Has a circuit configuration, and a DC voltage is generated from the first inverting amplifier circuit.
The reverse phase signal to which the minutes are added is output,
The width circuit outputs a positive-phase signal with added DC component.
A according to any one of claims 1 to 2, characterized in that
/ D converter. 5. The first and second inverting amplifier circuits are built-in.
The input resistance and the feedback resistance are the same resistance value.
The A / D conversion device according to claim 4, which is a characteristic.