JP3488916B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a double gate field effect transistor.

[0002]

2. Description of the Related Art In order to realize an insulated gate field effect transistor having a minute channel length, it is necessary to prevent a so-called short channel effect (a sharp drop in threshold voltage when the channel length is shortened). Required.
As one element structure therefor, FIG. 10 and FIG.
There is a double gate field effect transistor of the structure shown.

FIG. 10 is a plan view, and a cross section taken along the line XX 'is shown in FIG. In the figure, 1 is a substrate, 2 is an insulating layer, and 9, 10 and 11 are channel regions and source regions which form island-shaped semiconductor crystal layers separately provided in the groove 6 (see FIG. 13). And the drain region. At least the channel region is provided with a predetermined thickness T. Again 7
Reference numerals 1 and 72 are two gate insulating films provided on both side surfaces of the channel region 9, and 81 and 82 are two gate electrodes provided in the trench 6 separated by an island-shaped semiconductor crystal layer. Further, 100 is the remaining part of the semiconductor crystal layer 3 provided on the substrate 1 separated by the insulating film 2. Although the groove 6 is often partially filled with the insulator 21 etc. after it is once formed, the part once formed is called a groove even in that case.

This structure is said to be the most effective method for suppressing the short channel effect. That is, by shielding the channel region 9 by the left and right gate electrodes 81 and 82 and suppressing the influence of the drain electric field on the potential distribution at the source / channel region interface, the potential distribution at the source / channel region interface is reduced even if the channel is shortened. Stable control is possible only with the gate electrode, and abrupt drop of the threshold voltage is prevented.

However, in order for the features of this structure to function effectively as an integrated circuit device, it is essential that the channel region and the two gate electrodes are self-aligned and positioned. Otherwise, the positional mismatch between the two gate electrodes, the parasitic capacitance and parasitic resistance are increased due to an increase in the alignment margin, etc., and the fluctuation thereof causes a significant deterioration in the performance of the circuit operation.

Therefore, as a manufacturing method for realizing this structure by self-aligning the channel region and the two gate electrodes, a twelfth method using a conventional planarization technique such as a mechanical chemical polishing method (a damascene process or the like) is used. The method shown in FIGS.

First, as shown in FIG. 12, a silicon crystal layer 3 formed on a silicon substrate 1 via an oxide film 2 is prepared, and a silicon oxide film 4 and a silicon nitride film 5 are sequentially deposited. Next, as shown in FIGS. 13 and 14, a part of the silicon nitride film 5, the silicon oxide film 4 and the silicon crystal layer 3 is removed to form an island layer 200 separated from the surroundings by a groove 6 formed. . Reference numeral 100 denotes a remaining portion of the crystal layer 3, and reference numerals 31, 41 and 51 denote portions of the crystal layer 3, the silicon oxide film 4 and the silicon nitride film 5 left in the island layer 200, respectively.

Next, as shown in FIG. 15, a silicon oxide film 22 is buried in the groove 6 and flattened by a mechanical chemical polishing (CMP) method or the like. FIG. 16 is the XX 'cross section. Next, as shown in FIG. 17, the grooves 12 and 13 according to the gate electrode pattern are formed.
Is formed by removing the silicon oxide film 22 so that at least the depth reaches the surface of the oxide film 2. In this case grooves 12 and 13
Are formed by a pattern across the island layer 200. At that time, when the oxide film 22 is removed by etching, the surface of the island layer is also exposed to the etching medium at the same time, but the silicon nitride film acts as an etching mask to remove the island layer (the part which becomes the channel region 9 later). To prevent.

FIG. 18 shows the XX 'cross section. Further, as shown in FIG. 19, the groove 1 of the crystalline silicon layer 31 of the island layer 200
The side surface exposed at 2 and 13 is oxidized to form a silicon oxide film 7
Form 1 and 72. Next, as shown in FIG. 20, a polycrystalline silicon layer is deposited on the entire surface and is planarized by a mechanical chemical polishing method or the like to fill the trenches 12 and 13 with polycrystalline silicon layers 81 and 82, respectively. At this time, the silicon nitride film
5, and the silicon nitride film 51 left on the island layer 200 acts as an etching stopper for planarization. Second
FIG. 1 shows the XX ′ cross section of FIG.

Next, as shown in FIG. 22, the silicon oxide film 22 in the groove 6 is removed to form a groove 61 in which the polycrystalline silicon layers 81 and 82 are left, and the polycrystalline silicon layers 81 and 82 are formed. The island-shaped layer 200
Then, a source region 10 and a drain region 11 are formed. The masked portion of the silicon crystal layer 31 becomes the channel region 9. At the same time, the high-concentration n-type impurities are added to the polycrystalline silicon layers 81 and 82, so that they can be used as gate electrodes, respectively. Next, the silicon oxide film 21 is formed in the groove 61.
Is embedded and planarized by a mechanical chemical polishing method or the like.

Thus, the structure shown in FIGS. 10 and 11 in which the source region 10, the drain region 11, the channel region 9 and the gate electrodes 81 and 82 are separated by the insulator 21 which is self-aligned on the same main surface. realizable.

[0012]

However, in the conventional manufacturing method, the planarization technique such as the mechanical chemical polishing method is used for the first time in FIGS. 15 and 16 and in FIGS. 20 and 21.
A total of three steps including the second time in the figure and the third time in FIG. 23 are required. The flattening process using a mechanical chemical polishing method is a process in which contamination easily enters, and it also imposes a burden on the subsequent cleaning process. An object of the present invention is to reduce the number of flattening processes such as the mechanical chemical polishing method.

[0013]

Considering the reason why three steps are required for flattening, in the method in which the conventional method is simply applied, the groove of the desired final shape pattern is formed, and It can be said that this is because there is no concept that the material after the embedding is further processed to form the pattern of the final intended shape, since only the intended material is embedded therein. In the present invention, a groove having a large area including the target shape pattern is formed once, the target material is embedded therein, and the target shape pattern made of the target material is left, and the others are removed from the groove. The number of planarization processes such as the mechanical chemical polishing method is reduced by using the method described above.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention is shown in FIGS. First, as shown in FIG. 1, a silicon crystal layer 3 formed on a silicon substrate 1 via an oxide film 2 is prepared, and a silicon oxide film 4 and a silicon nitride film 5 are sequentially deposited. Second
As shown in FIGS. 3 and 4, the silicon nitride film 5, the silicon oxide film 4 and the silicon crystal layer 3 are partially removed to form the island layer 200 separated from the surroundings by the groove 6 formed. 1
00 is a remaining portion outside the groove 6, and 31, 41 and 51 are portions where the crystal layer 3, the silicon oxide film 4 and the silicon nitride film 5 are left in the island layer 200, respectively. Up to this point, the method is the same as the conventional method.

After that, an oxide film 7 is formed on the side surface of the silicon layer exposed in the groove by thermal oxidation or the like. At this time, the silicon nitride film acts as a film for preventing the progress of oxidation on the surface of the silicon layer.
Next, as shown in FIG. 4, a silicon oxide film layer is conventionally formed in the groove 6, but in the present invention, a polycrystalline silicon layer 8 is embedded and flattened by the first mechanical chemical polishing (CMP) or the like. . In this case, the silicon nitride film on each surface of the island layer 200 and the outside 100 functions as an etching stopper layer.

FIG. 5 is a cross section taken along the line XX '. In this case, the polycrystalline silicon layer 8 is used due to the characteristics of the material such that the silicon nitride film can withstand a high temperature thermal process such as a later impurity diffusion process and the silicon nitride film can serve as an etching mask. Further, it is desirable that the gate electrode can have conductivity. Therefore, any material having these characteristics can be arbitrarily substituted.

Next, as shown in FIG. 6, the polycrystalline silicon layers 81 and 82 according to the gate electrode pattern are left, and the remaining portion of the polycrystalline silicon layer 8 embedded in the trench 6 is removed. In this case, the polycrystalline silicon layers 81 and 82 are self-aligned with each other because they are formed in one pattern across the island layer 200. At that time, when the polycrystalline silicon layer 8 is removed by etching, the portion of the island layer surface which is not protected by the resist 300 is also exposed to the etching medium at the same time, but the silicon nitride film acts as an etching mask, and that portion of the island layer (later source Region and a portion to be a drain region) are prevented from being removed. The same applies to a portion outside the groove 6 which is not protected by the resist. Further, the side surface of the silicon layer facing the inside of the groove 6 serves as a mask by the silicon oxide film 7 previously formed on the side surface thereof to prevent the progress of etching and maintain the shape.

FIG. 7 shows the XX 'cross section. 300 is a resist mask for forming the polycrystalline silicon layers 81 and 82. Further, the portions of the oxide film 7 in contact with the polycrystalline silicon layers 81 and 82 are gate oxide films 71 and 72, respectively.
Therefore, the portion of the silicon crystal layer 31 sandwiched by the polycrystalline silicon layers 81 and 82 becomes the channel region 9. next,
The resist mask 300 is removed and the polysilicon layers 81 and 8 are removed.
2 is used as a mask, and the silicon oxide film 7 on the side surface of the silicon layer 31 is formed.
Is removed, and a high-concentration n-type impurity is diffused from the side surface to form the source region 10 and the drain region 11 in the silicon layer 31 of the island layer 200. Masked silicon crystal layer
The portion 9 of 31 becomes the channel region. At the same time, high-concentration n-type impurities are added to the polycrystalline silicon layers 81 and 82, so that they can be used as the gate electrodes, respectively.

Next, as shown in FIG. 8, the silicon oxide film 2 is formed in the groove 6.
1 is embedded and planarized by a second mechanical chemical polishing method or the like. FIG. 9 is the XX 'cross section. Thus, the structure of FIGS. 10 and 11 in which the source region 10, the drain region 11, the channel region 9, and the gate electrodes 81 and 82 are separated from the rest 100 by the insulator 21 which is self-aligned on the same main surface. realizable. As is apparent from this embodiment, the planarization process by the mechanical chemical polishing method or the like is required only twice, and can be less than the conventional process of three times.

[0020]

According to the present invention, it is possible to reduce the number of planarization processes such as the mechanical chemical polishing method, prevent contamination, reduce the number of manufacturing steps, and reduce the manufacturing cost. Further, it is possible to form a double gate field effect transistor in which a source region, a drain region, a channel region and two gate electrodes are arranged on the same main surface in a self-aligned manner.

[Brief description of drawings]

FIG. 1 is an explanatory view (A) of a manufacturing process which is an embodiment of the present invention.

FIG. 2 is an explanatory view (B) of a manufacturing process which is an embodiment of the present invention.

FIG. 3 is an explanatory view (C) of a manufacturing process which is a sectional view taken along line XX ′ of FIG. 2;

FIG. 4 is an explanatory view (D) of a manufacturing process which is an embodiment of the present invention.

FIG. 5 is an explanatory view (E) of a manufacturing process which is a cross-sectional view taken along the line XX ′ of FIG. 4;

FIG. 6 is an explanatory view (F) of a manufacturing process which is an embodiment of the present invention.

FIG. 7 is an explanatory view (G) of a manufacturing process which is a cross-sectional view taken along the line XX ′ of FIG. 6;

FIG. 8 is an explanatory view (H) of a manufacturing process which is an embodiment of the present invention.

9 is an explanatory view (I) of the manufacturing process which is a cross-sectional view taken along the line XX ′ of FIG. 8;

FIG. 10 is a plan view of an example of a double gate field effect transistor formed according to the present invention.

11 is a cross-sectional view taken along the line X-X ′ in FIG.

FIG. 12 is an explanatory view (a) of a conventional process.

FIG. 13 is an explanatory view (b) of a conventional process.

14 is an explanatory view (c) of the conventional process which is a cross-sectional view taken along the line XX ′ of FIG. 13.

FIG. 15 is an explanatory view (d) of a conventional process.

16 is an explanatory view (e) of the conventional process which is a cross-sectional view taken along the line XX 'of FIG.

FIG. 17 is an explanatory view (f) of a conventional process.

FIG. 18 is an explanatory view (g) of the conventional process which is a cross-sectional view taken along the line XX ′ of FIG. 17;

FIG. 19 is an explanatory view (h) of a conventional process.

FIG. 20 is an explanatory diagram (i) of a conventional process.

21 is an explanatory view (j) of the conventional process which is a cross-sectional view taken along the line XX ′ of FIG. 20.

FIG. 22 is an explanatory view (k) of a conventional process.

FIG. 23 is an explanatory diagram (l) of a conventional process.

[Explanation of symbols]

1 substrate 2 oxides 3 Crystal silicon layer 4 Silicon oxide film 5 Silicon nitride film 6 grooves 7 Silicon oxide film 8 Polycrystalline silicon layer 9 channel area 10 Source area 11 drain region 12 grooves 13 groove 21 Silicon oxide film layer 22 Silicon oxide film layer 31 Silicon layer 41 Silicon oxide film 51 Silicon nitride film 71 Gate oxide film 72 Gate oxide film 81 gate electrode 82 Gate electrode 100 Outer part of groove 6 200 Island layer in groove 6 300 resist mask pattern

Continuation of front page (56) Reference JP-A-6-151738 (JP, A) JP-A-10-93093 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29 / 786 H01L 21/336

Claims (4)

(57) [Claims] 1. A substrate is separated from a substrate by a first insulating layer,
And in the semiconductor layer with the etching mask laminated on the surface,
Of the first island that will be the source, drain and channel
As both side surface portions are exposed, forming a groove depth reaches the surface of said first insulating layer, planarizing the buried polycrystalline silicon <br/> the groove, said first island the polycrystalline silicon by a pattern having a planar shape across the section
To form a second island-shaped portion consisting of down, leaving the first island-shaped portion by the mask, the polycrystalline is within groove Shi
A method of manufacturing a dual-gate semiconductor device, comprising the step of removing the other part of the recon . 2. The polycrystalline silicon according to claim 1, on the surfaces of the both side surfaces of the semiconductor layer exposed in the groove.
A method of manufacturing a double-gate semiconductor device, the method including a step of forming a second insulating layer which serves as an etching mask for the gate . 3. The double structure according to claim 1, further comprising a step of introducing an impurity from a side surface portion of the semiconductor portion using the island-shaped portion made of the polycrystalline silicon as a mask.
Method of manufacturing gate semiconductor device. 4. The double gate according to claim 1, including a step of filling the inside of the trench except the island-shaped portion made of the polycrystalline silicon with a third insulator to planarize the same. A method of manufacturing a semiconductor device.