JP3481448B2 - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JP3481448B2 JP3481448B2 JP03241498A JP3241498A JP3481448B2 JP 3481448 B2 JP3481448 B2 JP 3481448B2 JP 03241498 A JP03241498 A JP 03241498A JP 3241498 A JP3241498 A JP 3241498A JP 3481448 B2 JP3481448 B2 JP 3481448B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- alloy
- lead
- tab portion
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/48664—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85464—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば半導体等の
装置を搭載し、外部回路用の端子部を形成して前記装置
を樹脂封止するためのリードフレームに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for mounting a device such as a semiconductor, forming a terminal portion for an external circuit and resin-sealing the device.
【０００２】[0002]
【従来の技術】通常、半導体装置の多くは、電子機器へ
の実装のためのパッケージ形態の一つとして、リードフ
レームに搭載された状態でワイヤーボンディング等によ
る内部配線を施されてから樹脂で封止される。2. Description of the Related Art In general, most of semiconductor devices are one of package forms for mounting on electronic equipment, in which they are mounted on a lead frame and are internally wired by wire bonding or the like, and then sealed with resin. Be stopped.
【０００３】一般的なリードフレームは、主に、半導体
装置が載置されるタブ部と、その周囲に配置されたリー
ド部とから構成されている。リード部は、先端部（タブ
部側）がワイヤーボンディングで半導体装置に電気結線
されたインナーリードとその反対側で、樹脂封止後に封
止体の外方に延出して外部端子となるアウターリードか
らなる。各リードは、タイバーによって互いに且つフレ
ーム本体に連結されている。A general lead frame is mainly composed of a tab portion on which a semiconductor device is placed and lead portions arranged around the tab portion. The lead part is an outer lead whose tip (tab side) is electrically connected to the semiconductor device by wire bonding and the opposite side, and which extends outside the encapsulant after resin encapsulation and serves as an external terminal. Consists of. The leads are connected to each other and to the frame body by tie bars.
【０００４】このようなリードフレームは、Ｃｕ合金や
ＦｅＮｉ合金板から、打ち抜きプレスあるいはエッチン
グによりタブ部とリード部とが一体的に成形された状態
で得られる場合が多い。また、タブ部のみを別に成形し
た後に、リード部が成形されているフレーム本体に組み
合わされて構成されることもある。例えば、熱的及び電
気的特性から放熱板をタブとして兼用させる複合リード
フレームやマルチフレーム型ＬＯＣ（リード・オン・チ
ップ）リードフレーム等が挙げられる。Such a lead frame is often obtained from a Cu alloy or FeNi alloy plate in a state where the tab portion and the lead portion are integrally formed by punching press or etching. Further, it may be configured by separately molding only the tab portion and then combining the lead portion with the molded frame body. For example, a composite lead frame or a multi-frame type LOC (lead-on-chip) lead frame in which a heat sink is also used as a tab in view of thermal and electrical characteristics can be mentioned.
【０００５】さらに、リードフレームは、通常タブ部と
インナーリード部分にスポットＡｇメッキしてからパッ
ケージング工程に供される。この場合、樹脂封止の後に
アウターリード部分に半田メッキが施される。近年、Ｎ
ｉを下地メッキしてからその表面にＰｄ又はＰｄ合金を
メッキしたり、更に薄いＡｕメッキを追加する方法が実
用化されている。Further, the lead frame is usually subjected to spot Ag plating on the tab portion and the inner lead portion before being subjected to the packaging process. In this case, the outer lead portion is solder-plated after the resin sealing. In recent years, N
A method has been put to practical use in which i is plated as a base and then Pd or a Pd alloy is plated on the surface, or a thin Au plating is added.
【０００６】また、基材として抜き打ち時の破断性が良
好なＣｕ−Ｚｎ合金からなるリードフレーム全面にＰｄ
又はＰｄ合金をメッキして応力腐食割れを防ぐというも
のも考えられている。Further, as a base material, Pd is formed on the entire surface of the lead frame made of a Cu--Zn alloy which has a good rupture property when punching.
Alternatively, Pd alloy is plated to prevent stress corrosion cracking.
【０００７】このようなＰｄ又はＰｄ合金を全面にメッ
キしたリードフレームでは、従来のスポットＡｇメッキ
に比べてメッキ工程が平易でしかも猛毒のシアンを必要
としない。さらに、Ａｇメッキの場合の1/10〜1/30とい
う薄いメッキでもその接続性等の機能を十分に発揮する
だけでなく、樹脂封止後のアウターリード部分の半田メ
ッキ工程が省けるため、コストと共にリードタイム短縮
の効果が大きい。In such a lead frame having the entire surface plated with Pd or Pd alloy, the plating process is simpler than the conventional spot Ag plating, and highly poisonous cyanide is not required. In addition, even if the plating is as thin as 1/10 to 1/30 of Ag plating, not only the functions such as its connectivity are fully exhibited, but also the solder plating process of the outer lead part after resin sealing can be omitted. At the same time, the effect of shortening the lead time is great.
【０００８】リードフレームのＰｄ又はＰｄ合金メッキ
は、以上の理由に加えて、Ａｇマイグレーションによる
短絡障害を皆無化できるため、半導体装置の品質・信頼
性とコストの両面から実用的価値が高い。In addition to the above reasons, the Pd or Pd alloy plating of the lead frame can eliminate all short-circuit failures due to Ag migration, and is therefore highly practical in terms of both quality and reliability of the semiconductor device and cost.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、全面を
Ｐｄ又はＰｄ合金でメッキされたリードフレームに搭載
・封止された半導体装置が実装された電子機器において
は、特に近年のパッケージの小型・薄肉化に伴って過酷
な温湿度サイクルや高温高湿環境に晒す加速試験での劣
化障害の発生が増加する傾向にある。However, in an electronic device in which a semiconductor device mounted and sealed on a lead frame whose entire surface is plated with Pd or a Pd alloy is mounted, especially in recent years, the size and thickness of the package have been reduced. As a result, the occurrence of deterioration failures in accelerated tests exposed to severe temperature / humidity cycles and high temperature / high humidity environments tends to increase.
【００１０】Ｐｄ又はＰｄ合金メッキリードフレームで
助長される欠陥の典型的なものは、リフロー半田実装を
模した加湿−熱衝撃試験において見られる、所謂ポップ
コーン現象である。これは、樹脂封止体内において、リ
ードフレームと樹脂との界面に樹脂に浸透した水分が溜
り、高温環境下で蒸発膨張して空隙を形成し、場合によ
ってパッケージの破壊を来すものである。A typical defect promoted in a Pd or Pd alloy plated lead frame is a so-called popcorn phenomenon which is observed in a humidification-thermal shock test simulating reflow solder mounting. This is because the moisture that has penetrated into the resin is accumulated at the interface between the lead frame and the resin in the resin-sealed body, and evaporates and expands in a high temperature environment to form a void, which possibly causes the package to be destroyed.
【００１１】この現象は、特に、比較的面積の広いタブ
部裏面で最も生じやすい。そこで、タブ部裏面に凹凸を
設けたり、タブ部中央を打ち抜き欠損させて面積を減少
させたり、また特殊なカプリング剤で表面処理を施した
り、特殊なメッキ処理を施すなど、様々な方法が試みら
れているが、いずれも特殊な工程を更に付加するもので
あってコスト的に望ましくないばかりでなく、効果が一
様ではないため実用化には及ばない。This phenomenon is most likely to occur particularly on the back surface of the tab portion having a relatively large area. Therefore, various methods such as providing unevenness on the back surface of the tab part, punching out the center of the tab part to reduce the area, surface treatment with a special coupling agent, and special plating treatment are tried. However, all of them add a special process and are not desirable in terms of cost, and their effects are not uniform, so that they are not put into practical use.
【００１２】本発明は、上記問題点に鑑み、Ｐｄ又はＰ
ｄ合金でメッキされるものでありながら、樹脂封止後の
ポップコーン現象による欠陥の発生を低減し得るリード
フレームの提供を目的とする。In view of the above problems, the present invention provides Pd or Pd.
An object of the present invention is to provide a lead frame that can be plated with a d-alloy and that can reduce the occurrence of defects due to the popcorn phenomenon after resin sealing.
【００１３】[0013]
【課題を解決するための手段】上記問題を達成するた
め、請求項１に記載の発明に係るリードフレームでは、
半導体装置を搭載するためのタブ部と、その周囲に配置
され、タブ部上の半導体装置に一端側で電気結線される
リード部とを備え、Ｐｄ又はＰｄ合金で被覆されている
リードフレームにおいて、前記タブ部が、Ｚｎを３ｗｔ
％以上４０ｗｔ％以下の範囲内で含有するＣｕ−Ｚｎ系
合金からなり、少なくとも前記タブ部の裏面の一部にＰ
ｄ又はＰｄ合金の非被覆領域が設けられて前記Ｃｕ−Ｚ
ｎ系合金面が露出しているものである。In order to achieve the above-mentioned problems, in the lead frame according to the invention described in claim 1,
A tab portion for mounting the semiconductor device and a lead portion arranged around the tab portion and electrically connected to the semiconductor device on the tab portion at one end side are provided and covered with Pd or a Pd alloy. In the lead frame, the tab portion contains 3 wt% Zn.
% Or more and 40 wt% or less, a Cu-Zn-based alloy is contained, and at least a part of the back surface of the tab portion is formed of P.
The non-coated region of d or Pd alloy is provided to the Cu-Z
The n-based alloy surface is exposed .
【００１４】また、請求項２に記載の発明に係るリード
フレームでは、請求項１に記載のリードフレームにおい
て、前記リード部は、前記タブ部と異なる組成の金属材
からなるものである。According to a second aspect of the present invention, in the lead frame according to the first aspect, the lead portion is made of a metal material having a composition different from that of the tab portion.
【００１５】[0015]
【発明の実施の形態】本発明によるリードフレームは、
Ｐｄ又はＰｄ合金で被覆されてなるものであるが、以降
に一例を示す実測結果から、Ｐｄ又はＰｄ合金被覆のリ
ードフレームにおいて所謂ポップコーン欠陥の発生が助
長されるのは、封止樹脂とリードフレームとの密着性の
低減に起因することが明らかとなったことから、最もポ
ップコーン欠陥が発生し易いタブ部の裏面の少なくとも
一部領域へのＰｄ又はＰｄ合金メッキを施さない構成と
したものである。BEST MODE FOR CARRYING OUT THE INVENTION The lead frame according to the present invention is
Although the Pd or Pd alloy is coated with Pd or Pd alloy, the fact that so-called popcorn defects are promoted in the Pd or Pd alloy coated lead frame is promoted by the sealing resin and the lead frame. Since it has been clarified that this is due to the decrease in the adhesion with the Pd or Pd alloy plating, at least a part of the back surface of the tab portion where the popcorn defect is most likely to occur is not applied. .
【００１６】ここで、Ｐｄ被覆による密着性への影響と
して、リード材の封止用樹脂に対する剪断強度を測定し
た結果を示す。一般的に、半導体装置のパッケージング
工程における樹脂封止は２００℃〜３５０℃の高温度環
境下で行われる。この際、Ｐｄは酸化しないがＣｕ系合
金等の卑金属は酸化されて酸化膜が形成される。Here, the results of measuring the shear strength of the lead material with respect to the sealing resin will be shown as the effect of the Pd coating on the adhesion. Generally, resin sealing in a packaging process of a semiconductor device is performed in a high temperature environment of 200 ° C to 350 ° C. At this time, Pd is not oxidized, but a base metal such as a Cu-based alloy is oxidized to form an oxide film.
【００１７】そこで、上記高温度範囲条件下において、
ＣｕＺｎ系合金（２０ｗｔ％Ｚｎ，２ｗｔ％Ｓｎ含有の
Ｃｕ）製リード材，同ＣｕＺｎ系合金にＰｄメッキを施
したリード材、Ｃｕ系合金Ｃ１９４（２．４ｗｔ％Ｆ
ｅ，０．１２％ｗｔＺｎ，０．０７ｗｔ％Ｐ含有Ｃｕ）
製リード材、の各試料に一般的な封止用樹脂であるエポ
キシ樹脂でモールドを施し、それぞれのリード試料につ
いて、その表面と樹脂との界面密着性を剪断強度として
測定した。Therefore, under the above high temperature range condition,
CuZn-based alloy (Cu containing 20 wt% Zn, 2 wt% Sn) lead material, lead material obtained by plating the CuZn-based alloy with Pd, Cu-based alloy C194 (2.4 wt% F)
e, 0.12% wt Zn, 0.07 wt% P-containing Cu)
Each sample of the lead-made lead material was molded with an epoxy resin, which is a general sealing resin, and the interface adhesion between the surface and the resin was measured as the shear strength for each lead sample.
【００１８】代表的な測定例として、前記各種リード材
について、予め、それぞれ３００℃で最長２０分まで酸
化処理を行ったものを樹脂封止した後、この樹脂に対す
る剪断強度を測定した結果を図４に酸化処理時間（横
軸：分，縦軸；剪断強度Ｎ／mm2）に沿って経時的に示
した。As a typical measurement example, each of the various lead materials previously subjected to oxidation treatment at 300 ° C. for up to 20 minutes was sealed with a resin, and the shear strength of the resin was measured. 4 shows the time along with the oxidation treatment time (horizontal axis: minutes, vertical axis; shear strength N / mm 2 ).
【００１９】この図４の結果から明らかなように、Ｃｕ
Ｚｎ系合金製リード材（図中黒菱形）では、処理時間２
０分のものまで高い剪断強度を保っている。これに比べ
てＣｕＺｎ系合金にＰｄメッキを施したもの（図中黒四
角形）では、一定の剪断強度を保ってはいるが低い値に
止まっている。また、Ｃｕ系合金製リード材（図中白三
角形）では、最高値がＣｕＺｎ系合金製のものに及ばな
いだけでなく、最高値の際の処理時間を超えると急激に
剪断強度が低下している。As is clear from the results shown in FIG. 4, Cu
For a Zn-based alloy lead material (black diamond in the figure), the processing time is 2
High shear strength is maintained up to 0 minutes. In contrast, the CuZn-based alloy plated with Pd (black square in the figure) maintains a constant shear strength but remains at a low value. In addition, in the Cu-based alloy lead material (white triangle in the figure), not only the maximum value does not reach that of the CuZn-based alloy, but the shear strength sharply decreases when the treatment time at the maximum value is exceeded. There is.
【００２０】以上の結果から、ＣｕＺｎ合金表面が封止
樹脂とその界面において高い密着力を保持することがわ
かる。一方、Ｐｄ被覆表面は、一定でありながらも弱い
密着力であり、これはＰｄ表面に酸化が生じないために
界面における化学的結合に必要な酸素元素の不足が原因
であると考えられる。またＣｕ系合金Ｃ１９４はＣｕの
持つ典型的現象として酸化膜の過剰成長と共に脆弱化し
て密着力を急激に低下せしめる。From the above results, it can be seen that the surface of the CuZn alloy maintains a high adhesive force at the sealing resin and its interface. On the other hand, the Pd-coated surface has a constant but weak adhesion, and it is considered that this is due to the lack of oxygen element necessary for chemical bonding at the interface because oxidation does not occur on the Pd surface. Further, as a typical phenomenon of Cu, the Cu-based alloy C194 becomes brittle with excessive growth of the oxide film, and the adhesive force is sharply reduced.
【００２１】従って、本発明におけるリードフレーム
は、表面積が大きくて最も密着性の影響を受け、ポップ
コーン欠陥を生じやすいタブ部について、少なくとも裏
面一部領域をＰｄ又はＰｄ合金非被覆とするものである
ため、この非被覆領域ではＣｕＺｎ系合金が持つ封止樹
脂に対する高い密着性が現れることとなり、タブ部にお
けるポップコーン現象の発生は抑えられる。Therefore, the lead frame according to the present invention has a large surface area and is most affected by the adhesiveness, and at least the partial area of the back surface is not covered with Pd or Pd alloy in the tab portion where popcorn defects are likely to occur. Therefore, in this non-covered region, high adhesion of the CuZn-based alloy to the sealing resin appears, and the occurrence of the popcorn phenomenon in the tab portion is suppressed.
【００２２】なお、本発明のリードフレームは、特にタ
ブ部がＣｕＺｎ系合金からなるものであるが、合金のＺ
ｎ含有率を特定の範囲に限定したものである。この範囲
は、以下に示す封止樹脂との密着性へのＺｎ量の影響の
測定結果に基づくものである。In the lead frame of the present invention, the tab portion is made of CuZn-based alloy, and
The n content is limited to a specific range. This range is based on the measurement result of the influence of the Zn amount on the adhesion with the sealing resin described below.
【００２３】即ち、本発明者らは、Ｚｎ含有量の異なる
各種ＣｕＺｎ系合金（Ｚｎ以外は図４の測定に用いたも
のと同様の組成）製のリード材について、それぞれ予め
３００℃で５分の酸化処理を行った後にエポキシ樹脂封
止し、この樹脂に対する剪断強度を測定した。結果は図
５（横軸：Ｚｎ含有率ｗｔ％，縦軸；剪断強度Ｎ／m
m2）に示した。That is, the inventors of the present invention have prepared a lead material made of various CuZn-based alloys (having the same composition as that used in the measurement of FIG. 4 except for Zn) having different Zn contents in advance at 300 ° C. for 5 minutes. After carrying out the oxidation treatment of 1., the resin was sealed with an epoxy resin, and the shear strength for this resin was measured. The results are shown in Fig. 5 (horizontal axis: Zn content wt%, vertical axis; shear strength N / m).
m 2 ).
【００２４】図５から明らかなように、Ｚｎ含有率が３
ｗｔ％未満のＣｕＺｎ系合金製のものについては、実用
的に十分な密着力は得られなかった。これは、Ｚｎ含有
率が低くＣｎリッチであるほどＣｎの典型的特性が顕著
となり、酸化膜の過剰成長に伴う脆弱化が生じるためで
ある。As is apparent from FIG. 5, the Zn content is 3
For CuZn alloys with less than wt%, practically sufficient adhesion could not be obtained. This is because the typical characteristics of Cn become more prominent as the Zn content is lower and the content of Cn is rich, and weakening occurs due to excessive growth of the oxide film.
【００２５】他方、Ｚｎ含有率が４０ｗｔ％を超えるＣ
ｕＺｎ系合金では、加工性、耐腐食性等に劣り、リード
フレームの材質としても実用的ではない。以上のことか
ら、本発明のリードフレームにおいては、特にタブ部は
Ｚｎ含有率が１０ｗｔ％以上、４０ｗｔ％以下の範囲内
にあるＣｕＺｎ系合金からなるものとした。On the other hand, C having a Zn content of more than 40 wt%
The uZn-based alloy is inferior in workability and corrosion resistance and is not practical as a material for the lead frame. From the above, in the lead frame of the present invention, particularly the tab portion is made of a CuZn-based alloy having a Zn content in the range of 10 wt% or more and 40 wt% or less.
【００２６】なお、本発明に用いられるＣｕＺｎ系合金
とは、ＣｕとＺｎの２成分に限定されるものではなく、
Ａｌ，Ｎｉ，Ｓｎ，Ｓｉ，Ｃｏ，Ｆｅ，Ｐ，Ｐｂ，Ａ
ｓ，Ｂｉ，Ａｇ，Ｃａ，Ｍｇ，Ｓｒ，Ｉｎ，Ｔｉ，Ｃ
ｒ，Ｍｎ，Ｚｒ，Ｃｄ，レアアース元素のうち１種又は
２種以上を含有するものも含まれる。The CuZn alloy used in the present invention is not limited to the two components Cu and Zn.
Al, Ni, Sn, Si, Co, Fe, P, Pb, A
s, Bi, Ag, Ca, Mg, Sr, In, Ti, C
Those containing one or more of r, Mn, Zr, Cd and rare earth elements are also included.
【００２７】また、Ｐｄ合金としては、例えば、Ｐｄ−
Ｎｉ，Ｐｄ−Ａｇ，Ｐｄ−Ｃｏ，Ｐｄ−Ｎｉ−Ｃｏ，Ｐ
ｄ−Ａｕ等が挙げられる。Ｐｄ合金は、メッキ等の手法
でリードフレームに被覆されるが、通常、下地にＮｉ，
Ｃｏ又はＮｉ−Ｃｏ，Ｎｉ−Ｐ，Ｎｉ−Ｆｅ等の合金被
膜を０．３〜３μｍの厚さに施しておくと、被膜の均一
性が改善され、Ｐｄの厚さ０．０２〜０．１μｍ程度で
実用的な特性が満足でき、好ましい。また、従来同様に
ＡｕまたはＡｕ系合金、他のＰｄ系合金等の貴金属被覆
層をさらに追加しても良い。As the Pd alloy, for example, Pd-
Ni, Pd-Ag, Pd-Co, Pd-Ni-Co, P
d-Au etc. are mentioned. The lead frame is coated with a Pd alloy by a method such as plating.
When Co or Ni-Co, Ni-P, Ni-Fe or other alloy coating is applied to a thickness of 0.3 to 3 [mu] m, the uniformity of the coating is improved and the Pd thickness of 0.02 to 0. A thickness of about 1 μm is preferable because practical characteristics can be satisfied. Further, a noble metal coating layer such as Au or Au-based alloy or other Pd-based alloy may be further added as in the conventional case.
【００２８】また、本発明のリードフレームにおけるＰ
ｄ又はＰｄ合金の非被覆領域は、タブ部裏面に限定され
るものではなく、半導体装置のパッケージング工程や要
求条件によって、タブ部全面、あるいはリードフレーム
裏面全面、インナーリード先端部を除く樹脂封止領域全
体など、適宜選択すれば良い。Further, P in the lead frame of the present invention
The uncoated region of the d or Pd alloy is not limited to the back surface of the tab portion, but may be a resin sealing layer except for the entire tab portion, the entire back surface of the lead frame, or the tip of the inner lead, depending on the packaging process and requirements of the semiconductor device. The entire stop area may be appropriately selected.
【００２９】特に、タブ部を別工程で成形し、後にフレ
ーム本体に組み合わせてなるリードフレームにおいて
は、リード部を含むフレーム本体全面をＰｄ又はＰｄ合
金で被覆してから、非被覆のＣｕＺｎ系合金製のタブ部
を複合するとい簡便な工程で非被覆領域が得られる。Particularly, in a lead frame in which the tab portion is formed in a separate step and then combined with the frame body, the entire surface of the frame body including the lead portion is coated with Pd or Pd alloy, and then the uncoated CuZn alloy is used. The uncoated region can be obtained by a simple process of combining the tab portions made of metal.
【００３０】このように、タブ部と別工程で成形される
リード部を含むフレーム本体は、請求項２に記載したよ
うに、タブ部とは異なる組成の金属材から成形できる。
特にリード部にとって必要な機械的強度や加工性、また
導電性等の電気・熱的特性、メッキ性等、要求される特
性に応じて望ましい金属材を広く選択できる。As described above, the frame main body including the tab portion and the lead portion formed in a separate step can be formed from a metal material having a composition different from that of the tab portion.
In particular, a wide range of desirable metal materials can be selected according to required properties such as mechanical strength and workability required for the lead portion, electrical / thermal characteristics such as conductivity, and plating property.
【００３１】このような金属材として、例えば、Ｃｕ，
Ｃｕ−Ｓｎ，Ｃｕ−Ｃｒ，Ｃｕ−Ｚｒ，Ｃｕ−Ｚｒ，Ｃ
ｕ−Ｆｅ，Ｃｕ−Ｍｇ，Ｃｕ−Ｆｅ−Ｐ，Ｃｕ−Ｎｉ−
Ｓｉ，Ｃｕ−Ｃｒ−Ｓｎ，Ｃｕ−Ｓｎ−Ｎｉ−Ｐ等のＣ
ｕ系合金や、Ｆｅ４２Ｎｉ合金、コバール等の鉄系合金
が挙げられる。As such a metal material, for example, Cu,
Cu-Sn, Cu-Cr, Cu-Zr, Cu-Zr, C
u-Fe, Cu-Mg, Cu-Fe-P, Cu-Ni-
C such as Si, Cu-Cr-Sn, Cu-Sn-Ni-P
Examples include u-based alloys, Fe42Ni alloys, and iron-based alloys such as Kovar.
【００３２】タブ部をフレーム本体と別工程で成形する
ものとしては、例えば、パワートランジスタやＭＰＵの
如き高出力ＬＳＩ搭載用のリードフレームがある。これ
は、タブ部を厚くし、放熱板として、又はグランド回路
としても機能させるものである。この場合、全面あるい
は必要領域にＰｄメッキを施した薄いフレーム本体に、
ＣｕＺｎ系合金で厚く成形したタブ部を溶接、接着、カ
シメ等の方法で組み合わせて複合リードフレームとすれ
ば良い。An example of molding the tab portion in a separate process from the frame body is a lead frame for mounting a high power LSI such as a power transistor or MPU. This thickens the tab portion and makes it function as a heat sink or as a ground circuit. In this case, on a thin frame body with Pd plating on the entire surface or required area,
The tab portions formed thick with the CuZn-based alloy may be combined by a method such as welding, bonding, or caulking to form a composite lead frame.
【００３３】また、ＤＲＡＭ等のメモリー搭載用のマル
チフレーム型ＬＯＣリードフレームでは、フレーム本体
をＦｅＮｉやＣｕ系合金で成形し、全面あるいは必要領
域にＰｄメッキを施し、ＣｕＺｎ系合金で成形したタブ
部と溶接一体化すれば良い。Further, in a multi-frame type LOC lead frame for mounting a memory such as DRAM, the frame body is formed of FeNi or Cu type alloy, and Pd plating is applied to the entire surface or required area, and the tab portion is formed of CuZn type alloy. It should be integrated with welding.
【００３４】本発明によるリードフレームは、ＤＩＰ
（デュアル・インライン・パッケージ），ＳＯＰ（スモ
ール・アウトライン・パッケージ），ＳＯＪ（スモール
・アウトライン・Ｊリーデット・パッケージ），ＱＦＰ
（クワッド・フラット・パッケージ），ＰＬＣＣ（プラ
スチック・リーデット・チップ・キャリア）等のいずれ
の実装形態にも適応できる。The lead frame according to the present invention is a DIP.
(Dual Inline Package), SOP (Small Outline Package), SOJ (Small Outline J Leaded Package), QFP
(Quad flat package), PLCC (plastic lead chip carrier), etc. can be applied.
【００３５】さらに近年ではＣＳＰやＢＧＡ（ボール・
グリッド・アレイ）等の新しいパッケージの一部にリー
ドフレームを転用した実装が実用化されている。例え
ば、メモリーの小型ＣＳＰの一種として、ＬＯＣリード
フレームを応用したＳＯＮ（スモール・アウトライン・
ノンリーデット・パッケージ）タイプが実用化されてい
るが、本発明によるリードフレームはこれらの実装形態
にも適用できる。More recently, CSP and BGA (ball
Mounting that uses a lead frame as part of a new package such as a grid array has been put to practical use. For example, as a kind of small CSP for memory, SON (small outline
The non-leaded package type has been put into practical use, but the lead frame according to the present invention can be applied to these mounting forms.
【００３６】[0036]
【実施例】以下に、本発明の実施例によるリードフレー
ムを各種製造し、これらに対する加湿−熱衝撃試験を、
従来タイプのリードフレームを対照例として行った結果
を示す。[Examples] Various lead frames according to the examples of the present invention are manufactured below, and a humidification-thermal shock test for them is performed.
The result of having used the conventional type lead frame as a contrast example is shown.
【００３７】（実施例１）本発明の第１の実施例とし
て、全裏面側をＰｄ非被覆領域としたリードフレームを
製造した。まず、厚み０．１５ｍｍ、幅２４ｍｍのＣｎ
Ｚｎ合金条（１６ｗｔ％Ｚｎ，１．２ｗｔ％Ｓｎ，０．
０１ｗｔ％Ｐ含有）の片面のみを市販液クリーナー＃１
６０（メルテックス社製）を用いてアノード及びカソー
ド処理（双方とも各２．５Ａ／ｄｍ2，１０秒）によっ
て電解脱脂、次に１０秒間のＨ2ＳＯ4５０ｇ／Ｌによる
硫酸酸洗を行った後、Ｎｉの下地メッキを施し、その上
にＰｄメッキ、さらにＡｕメッキを施した。(Example 1) As a first example of the present invention, a lead frame in which the entire back surface side was a Pd non-coated region was manufactured. First, Cn having a thickness of 0.15 mm and a width of 24 mm
Zn alloy strip (16 wt% Zn, 1.2 wt% Sn, 0.
Commercial liquid cleaner # 1 on only one side (containing 01 wt% P)
60 (manufactured by Meltex Co.) is subjected to electrolytic degreasing by anode and cathode treatment (both 2.5 A / dm 2 , 10 seconds each), and then sulfuric acid pickling with H 2 SO 4 50 g / L for 10 seconds. After that, a Ni undercoat was applied, and then Pd plating and then Au plating were applied.
【００３８】Ｎｉメッキは、処理液ホウ酸３０ｇ・スル
ファミン酸Ｎｉ５００ｇ／Ｌ、ｐＨ４．０を用いて電流
密度１５Ａ／ｄｍ2で５０℃、１０秒間、Ｐｄメッキは
市販Ｐｄメッキ浴（日本高純度化学社製）ｐＨ７．５を
用いて電流密度２Ａ／ｄｍ2で６０℃、６秒間、Ａｕメ
ッキは、市販Ａｕメッキ浴（日本高純度化学社製）ｐＨ
６．２を用いて電流密度０．１Ａ／ｄｍ2で５０℃、５
秒間、をそれぞれ各処理液面上に前記片面を当てて表面
張力の作用で前記合金条を走行させることによって片面
にメッキ被覆層を順次形成した。Ni plating was carried out at a current density of 15 A / dm 2 at 50 ° C. for 10 seconds using a treatment solution of 30 g of boric acid / 500 g / L of sulfamic acid and pH of 4.0. 60 ° C. in a current density of 2A / dm 2 using a company manufactured) pH 7.5, 6 seconds, Au plating is commercially available Au plating bath (manufactured by Japan pure chemical Co., Ltd.) pH
6.2 with a current density of 0.1 A / dm 2 at 50 ° C., 5
For one second, the above-mentioned one surface was applied to each processing liquid surface, and the alloy strip was caused to run by the action of surface tension, whereby a plating coating layer was sequentially formed on one surface.
【００３９】以上の工程によって、片面側にＮｉメッキ
層０．５μｍ、Ｐｄメッキ層０．０５μｍ、Ａｕメッキ
層０．００３μｍが積層された片面Ｐｄメッキ合金条が
得られた。Through the above steps, a single-sided Pd-plated alloy strip was obtained in which the Ni-plated layer 0.5 μm, the Pd-plated layer 0.05 μm, and the Au-plated layer 0.003 μm were laminated on one side.
【００４０】この合金条を前記Ｐｄメッキ層が表面側
（ワイヤボンディング側）となるように、通常のスタン
ピング工程で打ち抜き成形により４４ピンのＳＯＪタイ
プリードフレームを得、これを半導体実装形態とした。A 44-pin SOJ type lead frame was obtained by punching and molding this alloy strip so that the Pd plated layer was on the front surface side (wire bonding side), and this was used as a semiconductor mounting form.
【００４１】即ち、図１に示すように、タブ部２および
インナーリード３，アウターリード４を含むリードフレ
ーム全上面がＰｄメッキ層（Ｎｉメッキ層及びＡｕメッ
キ層を含む）６で被覆されており、全裏面側が非被覆領
域となっている。このＰｄメッキ層６で被覆されている
タブ部２上に、半導体装置１をエポキシ系接着剤で接着
（２３０℃、約３分）搭載し、同様にＰｄメッキ層６で
上面が被覆されているインナーリード３と半導体装置１
の電極（不図示）とをＡｕワイヤ５で接続（２４０℃、
約１分）した後、エポキシ樹脂７でアウターリード４以
外を封止（１７５℃、約２分で金型内樹脂注入、１７５
℃、６時間キュア）した。That is, as shown in FIG. 1, the entire upper surface of the lead frame including the tab portion 2, the inner lead 3 and the outer lead 4 is covered with a Pd plating layer (including a Ni plating layer and an Au plating layer) 6. The entire back surface side is an uncovered area. The semiconductor device 1 is mounted on the tab portion 2 covered with the Pd plated layer 6 with an epoxy adhesive (230 ° C., about 3 minutes), and the upper surface is similarly covered with the Pd plated layer 6. Inner lead 3 and semiconductor device 1
To the electrode (not shown) of Au wire 5 (240 ℃,
After about 1 minute), the epoxy resin 7 is used to seal the parts other than the outer leads 4 (175 ° C, resin injection in the mold in about 2 minutes, 175
C., cured for 6 hours).
【００４２】以上の工程によって得られた本第１実施例
による封止体８について、リフロー半田実装工程を想定
して、加湿−熱衝撃試験を行った。ここでは、対照例と
して、本実施例と同じＣｕＺｎ合金をスタンピング工程
で同じリードフレーム型に成形した後、表裏全面にＮｉ
−Ｐｄメッキを施したものを用いた封止体（対照１−
１）と、Ｃ１９４合金を基材として同様のリードフレー
ム型に成形した後、Ａｇをタブ部およびインナーリード
先端部に３．５μｍスポットメッキしたものを用いた封
止体（対照１−２）との、２つの従来タイプについても
試験を行った。The sealing body 8 according to the first embodiment obtained by the above steps was subjected to a humidification-thermal shock test assuming a reflow solder mounting step. Here, as a control example, the same CuZn alloy as in the present example was formed into the same lead frame mold by a stamping process, and then Ni was formed on the entire front and back surfaces.
-A sealed body using a Pd-plated one (Control 1-
1) and a sealed body (Control 1-2) using a C194 alloy as a base material and molding the same lead frame mold, and then spot-plating 3.5 μm of Ag on the tab portion and the inner lead tip portion. The two conventional types were also tested.
【００４３】処理条件は、加湿処理：８５％ＲＨ，８５
℃，４８時間、加熱処理：２３０℃共晶半田浴デップ５
秒間、とし、処理後に各封止体内のクラック、剥離等の
欠陥の有無をＳＡＭ（Scanning Acoustic Micrograph）
で観察した。その結果は、表１に示すように、２つの対
照１−１，１−２にはいずれもリードフレーム表面と樹
脂との界面で剥離が見られたが、本実施例による封止体
８内には欠陥は見られなかった。The treatment conditions are humidification treatment: 85% RH, 85
℃, 48 hours, heat treatment: 230 ℃ eutectic solder bath Dep 5
SAM (Scanning Acoustic Micrograph) for the presence of defects such as cracks and peeling in each sealed body after processing
Observed at. As a result, as shown in Table 1, in both of the controls 1-1 and 1-2, peeling was observed at the interface between the lead frame surface and the resin, but in the sealing body 8 according to this example. No defects were found in.
【００４４】[0044]
【表１】 [Table 1]
【００４５】（実施例２）次に、本発明の第２の実施例
として、全タブ部をＰｄ非被覆領域とする複合型リード
フレームを製造した。まず、厚み０．１２５ｍｍ、幅３
６ｍｍのＣｎ合金条（０．３ｗｔ％Ｃｒ，０．２５ｗｔ
％Ｓｎ，０．２ｗｔ％Ｚｎ含有）をまずプレス打ち抜き
で１６０ピンのＱＦＰリードフレームタイプのタブ部な
しのフレーム本体を成形した。(Embodiment 2) Next, as a second embodiment of the present invention, a composite lead frame in which all tab portions are Pd non-coated regions was manufactured. First, thickness 0.125 mm, width 3
6 mm Cn alloy strip (0.3 wt% Cr, 0.25 wt
% Sn, containing 0.2 wt% Zn) was first stamped to form a 160-pin QFP lead frame type frame body without a tab portion.
【００４６】このフレーム本体について、表裏両面を、
第１実施例と同様の工程で市販液クリーナー＃１６０
（メルテックス社製）を用いてアノード及びカソード処
理（双方とも各２．５Ａ／ｄｍ2，１０秒）によって電
解脱脂、次に１０秒間のＨ2ＳＯ4５０ｇ／Ｌによる硫酸
酸洗を行った後、Ｎｉの下地メッキを施し、その上にＰ
ｄメッキを施した。Regarding this frame body, both front and back sides are
A commercially available liquid cleaner # 160 is used in the same process as in the first embodiment.
(Meltex Co., Ltd.) was used to perform electrolytic degreasing by anode and cathode treatment (both 2.5 A / dm 2 , 10 seconds each) and then sulfuric acid pickling with H 2 SO 4 50 g / L for 10 seconds. After that, Ni base plating is applied, and P is applied on top of it.
It was d-plated.
【００４７】Ｎｉメッキは、処理液ホウ酸３０ｇ・スル
ファミン酸Ｎｉ５００ｇ／Ｌ、ｐＨ４．０を用いて電流
密度１５Ａ／ｄｍ2で５０℃、１０秒間、Ｐｄメッキは
市販Ｐｄメッキ浴（日本高純度化学社製）ｐＨ７．５を
用いて電流密度２Ａ／ｄｍ2で６０℃、６秒間処理液中
に走行させることによってＮｉメッキ層０．５μｍ、Ｐ
ｄメッキ層０．０５μｍを順次積層形成した。ここでは
Ａｕメッキは省いた。Ni plating was carried out at a current density of 15 A / dm 2 at 50 ° C. for 10 seconds using a treatment solution of 30 g of boric acid / 500 g / L of sulfamic acid at pH 4.0 for 10 seconds. Pd plating was carried out on a commercially available Pd plating bath (Manufactured by K.K.) at a current density of 2 A / dm 2 at 60 ° C. for 6 seconds in a treatment solution using a pH of 7.5 to form a Ni plating layer of 0.5 μm, P
A d-plated layer of 0.05 μm was sequentially laminated. Here, Au plating is omitted.
【００４８】次に、フレーム本体とは異なる組成をもつ
厚み０．５ｍｍのＣｕＺｎ合金板（２５ｗｔ％Ｚｎ，
０．３ｗｔ％Ａｌ含有）から打ち抜き成形した１２ｍｍ
×１２ｍｍ正方形のタブ部をフレーム本体に組み合わせ
てＱＦＰリードフレームを得、これを半導体実装形態と
した。Next, a CuZn alloy plate (25 wt% Zn, having a composition different from that of the frame body and having a thickness of 0.5 mm)
12mm punched from 0.3wt% Al content)
A QFP lead frame was obtained by combining a tab portion of a × 12 mm square with a frame body, and this was used as a semiconductor mounting form.
【００４９】即ち、図２に示すように、前記全面Ｐｄ非
被覆のタブ部１２を、両面接着テープを用いて、表裏両
面がＰｄメッキ層（Ｎｉメッキ層を含む）で被覆された
インナーリード１３の先端裏面に接着して複合リードフ
レームを構成した。That is, as shown in FIG. 2, the tab portion 12 which is not covered with Pd on the entire surface is covered with a Pd plating layer (including a Ni plating layer) on both sides of the inner lead 13 by using a double-sided adhesive tape. A composite lead frame was constructed by adhering to the back surface of the tip of
【００５０】このタブ部２上に、ＭＰＵ装置１１をエポ
キシ系接着剤で接着（２３０℃、約３分）搭載し、Ｐｄ
メッキ層１６で被覆されているインナーリード１３上面
とＭＰＵ装置１１の電極（不図示）とをＡｕワイヤ１５
で接続（２４０℃、約３分）した後、エポキシ樹脂１７
でアウターリード１４以外を封止（１７５℃、約２分で
金型内樹脂注入、１７５℃、６時間キュア）した。The MPU device 11 is mounted on the tab portion 2 with an epoxy adhesive (230 ° C., about 3 minutes), and Pd is mounted.
The upper surface of the inner lead 13 covered with the plating layer 16 and the electrode (not shown) of the MPU device 11 are connected to the Au wire 15.
After connecting with (240 ℃, about 3 minutes), epoxy resin 17
Then, the parts other than the outer lead 14 were sealed (175 ° C., resin injection in the mold in about 2 minutes, curing at 175 ° C. for 6 hours).
【００５１】以上の工程よって得られた本第２実施例に
よる封止体１８について、第１実施例と同様の処理条
件、加湿処理：８５％ＲＨ，８５℃，４８時間、加熱処
理：２３０℃共晶半田浴デップ５秒間で、加湿−熱衝撃
試験を行い、ＳＡＭで封止体内部を観察した。ここで
は、対照例として、本第２実施例と同じフレーム本体だ
けでなく、タブ部の両面もＰｄメッキ層（Ｎｉ下地メッ
キ層を含む）で被覆し、両者を組み合わせて得たＱＦＰ
リードフレームを用いた封止体（対照２−１）と、同フ
レーム本体に０．１５ｗｔ％Ｚｎ含有Ｃｕ合金製のタブ
部を組み合わせて得たリードフレームを用いた封止体
（対照２−２）との、２つの従来タイプについても試験
を行った。With respect to the sealing body 18 according to the second embodiment obtained by the above steps, the same treatment conditions as in the first embodiment, humidification treatment: 85% RH, 85 ° C., 48 hours, heat treatment: 230 ° C. A eutectic solder bath dip was performed for 5 seconds to perform a humidification-thermal shock test, and the inside of the sealed body was observed by SAM. Here, as a comparative example, not only the same frame body as in the second embodiment, but also both sides of the tab portion are coated with a Pd plating layer (including a Ni undercoating layer), and a QFP obtained by combining both is obtained.
A sealed body using a lead frame (Control 2-1) and a sealed body using a lead frame obtained by combining the frame body with a tab portion made of a Cu alloy containing 0.15 wt% Zn (Control 2-2). ) And two conventional types were also tested.
【００５２】結果は、前記表１に示す通り、２つの対照
２−１，２−２にはいずれもリードフレーム表面と樹脂
との界面で剥離が見られたが、本第２実施例による封止
体１８内には欠陥は見られなかった。As shown in Table 1, the two controls 2-1 and 2-2 showed peeling at the interface between the surface of the lead frame and the resin. No defect was found in the stopper 18.
【００５３】（実施例３）次に、本発明の第３の実施例
として、タブ部裏面のみをＰｄ非被覆領域としたリード
フレームを製造した。まず、厚み０．１５ｍｍ、幅２４
ｍｍのＣｎＺｎ合金条（２２ｗｔ％Ｚｎ，０．２ｗｔ％
Ｆｅ含有）から通常のスタンピング工程で打ち抜き成形
により４４ピンのＳＯＪリードフレーム型を得た。(Embodiment 3) Next, as a third embodiment of the present invention, a lead frame in which only the back surface of the tab portion has a Pd non-coated region is manufactured. First, thickness 0.15 mm, width 24
mm CnZn alloy strip (22 wt% Zn, 0.2 wt%
A 44-pin SOJ lead frame mold was obtained by punching from a Fe-containing) in a normal stamping process.
【００５４】この表裏全面を第１実施例と同様の市販液
クリーナー＃１６０（メルテックス社製）を用いてアノ
ード及びカソード処理（双方とも各２．５Ａ／ｄｍ2，
１０秒）によって電解脱脂、次に１０秒間のＨ2ＳＯ4５
０ｇ／Ｌによる硫酸酸洗を行った後、Ｎｉの下地メッキ
（ホウ酸３０ｇ・スルファミン酸Ｎｉ５００ｇ／Ｌ、ｐ
Ｈ４．０の浴を用いて電流密度１５Ａ／ｄｍ2で５０
℃、１０秒間）を施し、その上にＰｄメッキ（市販Ｐｄ
メッキ浴ｐＨ７．５を用いて電流密度２Ａ／ｄｍ2で６
０℃、６秒間）を施した。The entire front and back surfaces were treated with an anode and a cathode using the same commercially available liquid cleaner # 160 (manufactured by Meltex) as in the first embodiment (both 2.5 A / dm 2 , respectively).
Electrolytic degreasing by 10 seconds), then H 2 SO 4 5 for 10 seconds
After sulfuric acid pickling with 0 g / L, Ni undercoating (boric acid 30 g, sulfamic acid Ni 500 g / L, p
50 with current density of 15 A / dm 2 using H4.0 bath
℃, 10 seconds), Pd plating on it (commercial Pd
6 at current density of 2 A / dm 2 using plating bath pH 7.5
0 ° C., 6 seconds).
【００５５】以上の工程によって、全面にＮｉメッキ層
０．５μｍ、Ｐｄメッキ層０．０５μｍを積層した後、
タブ部裏面のみをＰｄ非被覆領域としたＳＯＪリードフ
レームを半導体実装形態とした。After the Ni plating layer 0.5 μm and the Pd plating layer 0.05 μm are laminated on the entire surface by the above steps,
The SOJ lead frame in which only the back surface of the tab portion is not covered with Pd was used as a semiconductor mounting form.
【００５６】即ち、タブ部２２の裏面に対してのみスポ
ットメッキと同じラインで逆電解すべく１Ｎ−ＨＣｌを
噴射するメッキ治具を押し当て、Ｐｄメッキ層を溶解除
去した。これによって、図３に示すように、タブ部２２
の裏面のみを除く他の領域、タブ部２２表面およびイン
ナーリード２３，アウターリード２４の表裏全面にＰｄ
メッキ層（Ｎｉ下地メッキ層を含む）２６が被覆された
ＳＯＪリードフレームが得られた。That is, only on the back surface of the tab portion 22, a plating jig for injecting 1N-HCl was pressed against the same line as for spot plating to dissolve and remove the Pd plating layer. As a result, as shown in FIG.
Pd on the entire surface except for the back surface of the inner surface of the tab portion 22 and the inner and outer leads 24, 24
An SOJ lead frame coated with the plating layer (including the Ni undercoat plating layer) 26 was obtained.
【００５７】このＰｄメッキ層２６が残っているタブ部
２２上に、半導体装置２１をエポキシ系接着剤で接着
（２３０℃、約３分）搭載し、同様にＰｄメッキ層２６
で上面が被覆されているインナーリード２３と半導体装
置２１の電極（不図示）とをＡｕワイヤ２５で接続（２
４０℃、約１分）した後、エポキシ樹脂２７でアウター
リード２４以外を封止（１７５℃、約２分で金型内樹脂
注入、１７５℃、６時間キュア）した。The semiconductor device 21 is mounted (230 ° C., about 3 minutes) on the tab portion 22 on which the Pd plated layer 26 remains by bonding with an epoxy adhesive, and similarly the Pd plated layer 26 is mounted.
The inner lead 23 whose upper surface is covered with and an electrode (not shown) of the semiconductor device 21 are connected by an Au wire 25 (2
After sealing at 40 ° C. for about 1 minute), parts other than the outer leads 24 were sealed with epoxy resin 27 (175 ° C., resin injection in the mold at about 2 minutes, curing at 175 ° C. for 6 hours).
【００５８】以上の工程によって得られた本第３実施例
による封止体２８について、リフロー半田実装工程を想
定して、第１実施例と同様の加湿−熱衝撃試験を行い、
封止体２８内をＳＡＭで観察した。その結果は表１にも
示すように、欠陥は生じていなかった。With respect to the sealing body 28 according to the third embodiment obtained by the above steps, a humidification-thermal shock test similar to that of the first embodiment is performed, assuming a reflow solder mounting step,
The inside of the sealed body 28 was observed by SAM. As a result, as shown in Table 1, no defect occurred.
【００５９】以上の結果から明らかなように、本第１〜
第３実施例によるリードフレームでは、ＣｕＺｎ系合金
製のタブ部の少なくとも裏面部分をＰｄ非被覆領域とす
ることによって、従来タブ部のリードフレーム表面と封
止樹脂との界面で見られたポップコーン現象の発生が抑
えられる。As is clear from the above results, the first to
In the lead frame according to the third embodiment, at least the back surface portion of the tab portion made of CuZn-based alloy is set as the Pd non-covered area, so that the popcorn phenomenon conventionally observed at the interface between the lead frame surface of the tab portion and the sealing resin. Can be suppressed.
【００６０】[0060]
【発明の効果】以上説明した通り、本発明のリードフレ
ームによれば、Ｃｕ系合金のなかで最も安価で抜き打ち
破断性が良好なＣｕＺｎ系合金のもつ封止樹脂との高い
密着性をタブ部で発揮することができ、従来のＰｄ被覆
リードフレームに見られたポップコーン欠陥の発生が抑
えられ、信頼性の優れた電子機器を経済的に製造するこ
とができるという効果がある。As described above, according to the lead frame of the present invention, the tab portion has a high adhesiveness with the sealing resin of the CuZn-based alloy, which is the cheapest of the Cu-based alloys and has the excellent punching breakability. The effect of suppressing popcorn defects found in conventional Pd-coated lead frames can be achieved, and an electronic device with excellent reliability can be economically manufactured.
【図１】本発明の第１の実施例によるリードフレームを
用いた半導体実装形態を示す概略断面図である。FIG. 1 is a schematic sectional view showing a semiconductor mounting form using a lead frame according to a first embodiment of the present invention.
【図２】本発明の第２の実施例によるリードフレームを
用いた半導体実装形態を示す概略断面図である。FIG. 2 is a schematic sectional view showing a semiconductor mounting form using a lead frame according to a second embodiment of the present invention.
【図３】本発明の第３の実施例によるリードフレームを
用いた半導体実装形態を示す概略断面図である。FIG. 3 is a schematic sectional view showing a semiconductor mounting form using a lead frame according to a third embodiment of the present invention.
【図４】各種合金における封止樹脂に対する密着力を示
す線図（横軸：酸化処理時間（分），縦軸：剪断強度
（Ｎ／ｍｍ2））である。FIG. 4 is a diagram showing the adhesion of various alloys to a sealing resin (horizontal axis: oxidation treatment time (minutes), vertical axis: shear strength (N / mm 2 )).
【図５】ＣｎＺｎ合金の封止樹脂に対する密着力へのＺ
ｎ含有量の影響を示す線図（横軸：Ｚｎ含有率（ｗｔ
％），縦軸：剪断強度（Ｎ／ｍｍ2））である。FIG. 5 is a graph showing the Z to the adhesion of the CnZn alloy to the sealing resin.
Diagram showing influence of n content (horizontal axis: Zn content (wt
%), Vertical axis: shear strength (N / mm 2 )).
１，２１：半導体装置 ２１：ＭＰＵ装置 ２，１２，２２：タブ部 ３，１３，２３：インナーリード ４，１４，２４：アウターリード ５，１５，２５：Ａｕワイヤ ６，１６，２６：Ｐｄメッキ層 ７，１７，２７：（封止用）エポキシ樹脂 ８，１８，２８：封止体 1,21: semiconductor device 21: MPU device 2,12,22: Tab part 3,13,23: Inner lead 4,14,24: Outer leads 5,15,25: Au wire 6, 16, 26: Pd plating layer 7, 17, 27: (sealing) epoxy resin 8, 18, 28: sealed body
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平９−199655（ＪＰ，Ａ) 特開 平４−162556（ＪＰ，Ａ) 特開 昭62−141747（ＪＰ，Ａ) 特開 昭63−304654（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/50 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-9-199655 (JP, A) JP-A-4-162556 (JP, A) JP-A 62-141747 (JP, A) JP-A 63- 304654 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/50
Claims (2)
その周囲に配置され、タブ部上の半導体装置に一端側で
電気結線されるリード部とを備え、Ｐｄ又はＰｄ合金で
被覆されているリードフレームにおいて、 前記タブ部が、Ｚｎを３ｗｔ％以上４０ｗｔ％以下の範
囲内で含有するＣｕ−Ｚｎ系合金からなり、 少なくとも前記タブ部の裏面の一部にＰｄ又はＰｄ合金
の非被覆領域が設けられて前記Ｃｕ−Ｚｎ系合金面が露
出していることを特徴とするリードフレーム。1. A tab portion for mounting a semiconductor device,
The semiconductor device on the tab portion is provided with a lead portion electrically connected on one end side to the semiconductor device on the tab portion, and is made of Pd or Pd alloy.
In the covered lead frame, the tab portion is made of a Cu—Zn alloy containing Zn in a range of 3 wt% to 40 wt%, and at least a part of the back surface of the tab portion is made of Pd or Pd alloy.
Of the Cu--Zn based alloy surface is exposed.
Lead frame, characterized in that it has issued.
成の金属材からなることを特徴とするリードフレーム。2. The lead frame, wherein the lead portion is made of a metal material having a composition different from that of the tab portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03241498A JP3481448B2 (en) | 1998-01-30 | 1998-01-30 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03241498A JP3481448B2 (en) | 1998-01-30 | 1998-01-30 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11220084A JPH11220084A (en) | 1999-08-10 |
| JP3481448B2 true JP3481448B2 (en) | 2003-12-22 |
Family
ID=12358302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03241498A Expired - Fee Related JP3481448B2 (en) | 1998-01-30 | 1998-01-30 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3481448B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001230360A (en) * | 2000-02-18 | 2001-08-24 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
| JP2014146827A (en) * | 2014-03-27 | 2014-08-14 | Dainippon Printing Co Ltd | Surface lamination structure of circuit member |
-
1998
- 1998-01-30 JP JP03241498A patent/JP3481448B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11220084A (en) | 1999-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6518508B2 (en) | Ag-pre-plated lead frame for semiconductor package | |
| KR101924407B1 (en) | Lead frame and semiconductor device | |
| US6593643B1 (en) | Semiconductor device lead frame | |
| US6713852B2 (en) | Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin | |
| JP3537417B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6583500B1 (en) | Thin tin preplated semiconductor leadframes | |
| JP3760075B2 (en) | Lead frame for semiconductor packages | |
| US20020070434A1 (en) | Palladium-spot leadframes for high adhesion semiconductor devices and method of fabrication | |
| US20030116837A1 (en) | Semiconductor device and manufacturing method thereof | |
| JP3481448B2 (en) | Lead frame | |
| JPS6349382B2 (en) | ||
| JPH07326701A (en) | Conductive material for electric-electronic part, lead frame and semiconductor integrated circuit using the same | |
| KR100378489B1 (en) | Ag or Ag-alloy plated Lead frame for semiconductor package and the method of manufacturing the same | |
| KR100702956B1 (en) | Lead frame for semiconductor package and manufacturing method thereof | |
| JP2570911B2 (en) | Semiconductor package and lead frame used therefor | |
| JP3590603B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH11251503A (en) | Electronic part and manufacture therefor | |
| JPS63304654A (en) | Lead frame | |
| JPH08204081A (en) | Lead frame for semiconductor device, semiconductor device, and manufacturing method thereof | |
| JPH10284666A (en) | Electronic component device | |
| JP3454667B2 (en) | LOC type lead frame | |
| JPH08153843A (en) | Lead frame for semiconductor chip mounting | |
| KR100691338B1 (en) | Leadframe for Semiconductor Device Manufacturing | |
| JPH08241947A (en) | Lead frame for resin sealed semiconductor device and semiconductor device using it as well as manufacture of lead frame for resin sealed semiconductor device | |
| JPH04174546A (en) | Manufacture of semiconductor lead frame |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081010 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091010 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091010 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101010 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111010 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121010 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131010 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |