JP3474776B2 - Insulated gate field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor used as a high voltage, high current power switching element for a motor driving inverter, a power source, an igniter and the like.

[0002]

2. Description of the Related Art Insulated gate field effect transistors are
Since it has a MOS structure and is of a voltage drive type, it has a smaller drive power than a bipolar transistor and is less prone to thermal runaway. There are, for example, a power MOSFET (DMOS) which is a unipolar device and an IGBT which is a bipolar device. The IGBT has a structure similar to that of the power MOSFET, but by providing a pn junction in the drain region, conductivity modulation is caused in the high resistance drain layer during operation to achieve both a high breakdown voltage and a low on-resistance that cannot be achieved with the power MOSFET. it can.

An IGBT will be described below as an example. Figure
13 is arranged in the cell region of the IGBT and outside thereof.
It is sectional drawing of the guard ring part as a high breakdown voltage means.
This will be described according to the manufacturing process. First, on the semiconductor substrate
Yes p⁺Layer 1 (first semiconductor layer) is prepared, and a gas phase is formed on the layer 1.
N of high resistance by the growth method^-Form layer 2 (second semiconductor layer)
To do. Next, at a depth of 3 to 6 μm, the p-layer 3 (third semiconductor
Layer), p-layer 4 (fifth semiconductor layer) and p-layer 5 (Gardrin)
Section) is simultaneously formed by the selective diffusion method. And select
P layer 9, n by diffusion method ⁺Form layer 6 (fourth semiconductor layer)
To do. In the above manufacturing process, n^-Layer 2 surface
Oxidation as a gate insulating film formed by oxidizing
Using the gate electrode 8 formed on the film 7 as a mask,
The p-layer 9 and n are made by the known DSA technology.⁺Layer (source area)
6 are formed in a self-aligned manner, thereby forming a channel
To be done. After that, the interlayer insulating film 10 is formed, and then p
Layers 3 and n⁺Form ohmic contacts in layers 6 and p-layer 4
In order to open the contact hole in the upper oxide film,
Minium is vapor-deposited by several μm, and selective etching
Pole 11, gate electrode routing line 15, source electrode routing
The ridge line 11a is formed. Also, p⁺Metal film on the back of layer 1
Is vapor-deposited to form the drain electrode 12.

FIG. 14 shows a plane pattern of an element having the above cross-sectional structure. In FIG. 14, the source electrode 11 of FIG. 13 has a stripe-shaped opening pattern 22 formed in a plane and is repeatedly arranged at a predetermined interval together with a p well region formed of the p regions 3 and 9 to form a cell region A. is doing. A source electrode 11 is formed on the front surface of the cell region A. Further, the p region 4 is arranged so as to surround the terminal portion of the cell region A, and the source electrode routing line 11a, the gate electrode routing line 15, the source electrode pad 30, and the gate electrode pad 31 are formed on the p region 4. Reference numerals 21 and 25 in FIG. 13 denote insulating openings of the source electrode leading line 11a and the gate electrode leading line 15. The source electrode lead-out line 11a is provided to fix the potential of the entire element and eliminate the non-uniformity of the potential during operation.

The p-region 4 has a predetermined distance on the outer periphery thereof and has a length of 1
One or a plurality of guard ring parts 5 are arranged. Further, a channel stopper region 13 is arranged on the outer periphery of the guard ring region (region where the guard ring portion 5 is formed). The channel stopper region 13 is provided to suppress the expansion of the depletion layer due to the high voltage applied to the end portion of the substrate and to eliminate the influence thereof. Reference numeral 16 is an equipotential ring for applying a potential to the channel stopper region 13.

[0006]

In the above structure, a current path is formed between the drain electrode 12 and the source electrode 11 by forming a channel by applying a voltage to the gate electrode 8. With respect to such a normal operation, a surge voltage higher than the normal working voltage may be applied between the drain electrode 12 and the source electrode 11. In such a case, the pn junction formed of the p well region and the n ⁻ layer 2 is reverse biased, and the depletion layer spreads in the high resistance n ⁻ layer 2. Here, in the A region, depletion layers extend in the p well regions adjacent to each other and the n ⁻ layer 2 located between the p well regions, and the depletion layers overlap with each other, whereby the relaxation of the electric field is achieved. And pn at the bottom of the p-well region
The maximum electric field value EA is taken at the junction.

On the other hand, a p-layer 4 is formed outside the end of the p-well region, and in the region (B-region) extending from the end of the p-layer 4 to the end of the n ⁻ layer 2, the electric field relaxation effect is obtained. And the maximum electric field value EB is taken at the outer peripheral portion of the p layer 4, especially at the corner portion or the surface of the n ⁻ layer 2 in the vicinity thereof. Here, generally, EA <EB. That is, the breakdown voltage of the element depends on the breakdown at the corner of the p layer 4. Therefore, in order to reduce the EB value and bring it closer to the EA value to improve the breakdown voltage of the B region, the guard ring portions 5 that are repeatedly arranged are provided to reduce the maximum electric field value EB of the B region to improve the breakdown voltage of the element. I have to.

The electric field value EG in this guard ring region is
When a surge voltage is applied to the drain electrode 12, the voltage rises, and a large number of electron-hole pairs due to impact ionization are generated outside the guard ring portion located at the outermost periphery in the guard ring region. At this time, the electric field value E in the guard ring area
G also becomes larger in the planar pattern of the guard ring portion 5 in the corner pattern portion curved at a certain radius of curvature than in the linear pattern portion. Of the generated carriers, holes flow out to the nearby source electrode 11 or source electrode routing line 11a, and electrons flow to the p ⁺ layer substrate 1 to inject new holes. At this time, the current generates the flow indicated by the arrow in FIG. Among these, the current a is the p layer 4
Thin source electrode routing wire 11a routed along
Since it reaches the source electrode pad 30 via the wiring, the resistance is large due to the wiring, and the amount is smaller than the current b flowing directly to the source electrode 11. As a result, even if the guard ring portion is provided, a larger amount of current is concentrated in the cell region near the curved pattern portion.

As a result, a large current a flows into the p layer 9 in the cell region near the curved pattern portion of the guard ring portion, and a pn junction between the n ⁺ layer 6 and the p layer 9 is forward biased due to the occurrence of a voltage drop, It easily induces the operation of the parasitic transistor and is easily destroyed by current concentration. The breakdown voltage of the guard ring portion may be increased in order to improve the breakdown withstand voltage, but the breakdown voltage of the guard ring region may be increased by increasing the depth of the diffusion layer formed in the guard ring region or by increasing the diffusion layer. Need to increase the number of. However, increasing the depth of the diffusion layer also increases the lateral diffusion distance, which increases the area of the guard ring region. Furthermore, since the diffusion layer in the guard ring region is generally formed at the same time as the diffusion layer in the cell region in order to save the number of photomasks, the width of the diffusion layer in the cell region also increases, which further increases the chip area. Occurs. Further, increasing the number of diffusion layers formed in the guard ring region also increases the guard ring region, leading to an increase in the chip area.

Also in the MOSFET, since the semiconductor substrate 1 is an n-type, minority carriers (holes in this case) are not injected from the semiconductor substrate 1, but they collide when a high electric field is generated in the guard ring region. A large current flows through the p layer 9 in the cell region near the guard ring curve pattern portion due to the flow of ionized carriers, and a pn junction between the n ⁺ layer 6 and the p layer 9 is forward biased due to the occurrence of a voltage drop, and the operation of the parasitic transistor is performed. And it is easy to destroy due to current concentration, and there is a similar problem.

The present invention has been made in view of the above problems, and when the surge voltage is applied without increasing the chip area of the insulated gate field effect transistor,
The purpose is to improve the breakdown resistance of the device.

[0012]

Since SUMMARY OF THE INVENTION The present invention to achieve the above object, in the insulated gate field effect transistor according to the invention described in any one of claims 1 to 8, the
A section that has straight and corner portions in the planar contour.
And an outer peripheral portion on the outer peripheral side of the cell area,
The cell region is on the semiconductor substrate and on one side of the semiconductor substrate.
A second conductivity type high-resistance layer formed on the first conductivity type well region formed in plurality on one side of the high resistance layer, the formed U El region Te individual smell the well region 2 Conductivity type source region, in the individual well region
A serial source region and adjacent gate electrode formed through a gate insulating film a table surface on at least the channel region as a channel region of said well region, a source in contact common to the source region of the respective well regions the electrode
Wherein the outer peripheral portion, said extended to said gate electrode
Set for the channel region in each well region
Is provided with a gate electrode lead line connected to a common said gate electrode, further comprising a drain electrode on the other surface of the semiconductor substrate, wherein the high resistance layer in the outer peripheral portion one
On the surface side, the straight portion and the corner portion of the cell region
Along a first semiconductor region of a first conductivity type formed, Oite a position corresponding to the corner portion of the cell region, before
Set the first contact portion to the serial first semiconductor region, with contacting said direct the source electrode and the source electrode extended to the first contact portion upwardly into the first semiconductor region in said first contact portion The first contact portion extends along the corner portion at a position corresponding to the corner portion.

[0013]

According to the invention described in claims 1 to 8 , when a surge voltage is applied and current concentration occurs around the corners of the cell region, the current is supplied to the first semiconductor region. Since the current is directly bypassed to the source electrode in the wide cell region via the wide first contact portion of the cell region, the current flows into the well region in the cell region and forward bias is applied between the well region and the source region. Can be suppressed.
Therefore, it is possible to improve the breakdown resistance of the element when a surge voltage is applied.

[0014]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) FIGS. 1 to 3 show a first embodiment of the present invention. This first embodiment is applied to an n-channel IGBT, the entire plane pattern is the same as that shown in FIG. 14, and the area C (guard ring area corner portion) in FIG. Therefore, one of them is taken as an example to be a region C), and is characterized in that it is configured as shown in the enlarged view of FIG. 2 and 3 are cross-sectional views taken along line aa 'and bb' of FIG. 1, respectively. However,
Each sectional view shows up to the guard ring region.
Hereinafter, the same applies to all the embodiments. The same parts as those of the structure shown in FIG. 13 of the prior art are designated by the same reference numerals.

That is, as shown in the pattern plan view of FIG. 1 and the sectional view of FIG. 2, the cell region and p region 4 in the vicinity of the guard ring region corner are different from the prior art of FIGS. An insulating film opening 23 is provided in which a region 11b in which the source electrode 11 of the cell region extends to the outer periphery is provided, and the region 11b is widely opened in the p region 4 along a corner.
The point is that they are in contact with each other.

In such a structure, the source electrode 11
On the other hand, when a surge voltage that makes the drain electrode 12 have a positive potential is applied, a high electric field is generated in the vicinity of the corner portion of the guard ring region, and carriers are generated by impact ionization. When the current due to the generated carriers flows to the source electrode 11 in the cell region, the current is extracted from the region 11b in which the source electrode 11 in the cell region extends to the outer periphery and is in contact with the p region 4, reducing the current flowing into the cell region. Let That is, the region 11b forms a current bypass portion that bypasses the current directly to the source electrode 11 in the cell region, and this action suppresses forward bias between the p-well region and the source region 6 due to the current. Latch-up can be prevented, and as a result, the breakdown resistance can be improved up to a high current.

In this embodiment, the region shown in FIG. 2, that is, the current bypass portion by the corner region 11b is formed. However, in the region shown in FIG. 3, that is, the straight portion, the gate electrode routing line by the region 15 is formed. A connection portion with the gate electrode 8 is formed. Further, in both regions, the source electrode routing line 11a is formed on the outermost periphery and is configured to contact the p region 4 via the insulating film opening 21.

(Second Embodiment) FIGS. 4 to 6 show a second embodiment of the present invention. FIG. 4 is an enlarged view of the C region similarly to FIG. 1, and FIGS. 5 and 6 are aa ′ and bb ′ of FIG. 4, respectively.
FIG. In this embodiment, as in the first embodiment, the source electrode 11 in the cell region extends to the outer peripheral corner portion and contacts the p region 4 at the extended portion 11b, and the source electrode 11 is at least the element. The plane pattern of the guard ring portion 5 in the vicinity of the corner portion extends over the p region 4 located inside the region having the linear pattern, and contacts the p region 4 via the insulating film opening 26. There is. A region 2 in which the source electrode 11 in this cell region extends over the p region 4 and contacts the p region 4
6 and a region 27 in which the gate electrode 8 in the cell region extends over the p region 4 and contacts the gate routing line 15 are alternately arranged along the p region 4 located inside the linear pattern portion of the guard ring portion 5. It is arranged to be arranged.

As a result, the area of the current extraction region is increased in the plane, and the current flowing into the cell region is further reduced,
It is possible to suppress the occurrence of latch-up and further improve the breakdown resistance. Further, if the pattern of the present embodiment is applied to the entire end portion of the cell portion, the carrier extraction electrode 11b becomes
Since it comes into contact with the P region 4 through the contact hole 26, it also plays a role of fixing the outer peripheral potential, so that the source routing line 11a becomes unnecessary and the area of the region 4 can be reduced. Further, in the operation at the time of forming the channel part inversion layer, it has the effect of extracting the holes injected from the p ⁺ layer 1 with respect to the flow of the electron current through the channel. There is also an effect of improving.

(Third Embodiment) FIGS. 7 to 9 show a third embodiment of the present invention. FIG. 7 is an enlarged view of the area C as in FIG. 1, and FIGS. 8 and 9 are aa ′ and bb ′ of FIG. 7, respectively.
FIG. In this embodiment, in the D region indicated by the chain double-dashed line in FIG. 7, as shown in FIG. 8, the n ⁺ source region 6 is not formed in the cell region near the corner portion of the guard ring region, that is, in the region D. The p well region 3 is used as a dummy layer in which the n ⁺ source region 6 is not formed. The other structure is the gate electrode 8 in the cell region.
On the p-layer 4 is the gate routing line 15 and the insulating film opening 25.
The configuration is the same as that of the second embodiment except that the connection is made via.

In this structure, when a high electric field is generated in the vicinity of the guard ring region corner portion due to the surge voltage as described above, and a current generated by carriers generated by impact ionization flows through the source electrode 11 in the cell region, the n ⁺ source region is generated. Since 6 is not formed, the parasitic transistor structure does not exist, and therefore, the parasitic transistor operation does not occur, so that the breakdown resistance is improved.

That is, according to the present embodiment, since the channel region at the outer peripheral corner portion is eliminated, there is no inflow of electron current in the corner portion, and accordingly, there is an effect of reducing the hole injection amount in the corner portion. Since the extraction area is increased, the synergistic effect can achieve the effect of improving the latch-up resistance of the corner portion. Further, since the shape pitch of the p region 3 of the D region is the same as that of the cell region, the way the depletion layer spreads when the drain voltage is applied, that is, the electric field distribution can be the same as that of the cell region even in the D region.
The potential distribution on the chip surface can be made uniform. This makes dv / d
A uniform junction current flows even for surges with large t,
Current concentration is unlikely to occur. The p region 3 of the D region and the p region of the cell region may be separated.

(Fourth Embodiment) FIGS. 10 to 12 show a fourth embodiment of the present invention. FIG. 10 is an enlarged view of the area C as in FIG. 1, and FIGS. 11 and 12 are a- of FIG.
It is a ', bb' sectional drawing. In this embodiment, the p region 24 is provided between the cell region and the p region 4 at the corner of the cell region, and the insulating film opening 29 is formed in the p region 24.
It is configured to contact the source electrode 11 via. Other configurations are the same as those in the second embodiment.

In this structure, as described above, when a high electric field is generated in the vicinity of the corner portion of the guard ring region due to the surge voltage and a current caused by carriers generated by impact ionization flows through the source electrode 11 in the cell region, the p region 24 becomes The region becomes a carrier extraction region through the insulating film opening 29, and as a result, the concentration of current in the corner cell region is suppressed, so that the operation of the parasitic transistor structure in the cell part is suppressed,
This improves the breakage resistance.

That is, according to the present embodiment, by making the contact area of the p region large, even in the operation at the time of forming the channel inversion layer, the electron current is injected from the p ⁺ layer 1 with respect to the flow of the electron current through the channel. Since the effect of extracting the positive holes works effectively, it is possible to prevent the concentration of hole current in the cell portion around the cell region. Further, by forming the extraction region in a fan-shaped pattern, it is possible to efficiently extract the hole current when the holes in the corner guard ring region flow toward the cell part. Incidentally, the p region 24 and the insulating film opening 29
May be arbitrarily expanded in the X and Y directions. Further, the p region 24 and the P region 4 may be integrated, or the insulating film opening 26 may be integrated with 29 at that time.

In the first to fourth embodiments described above in detail, the stripe pattern is shown as an example of the cell pattern. However, the same effect can be obtained in a cell pattern element such as a quadrangle, a hexagon or an octagon. Can be achieved. Also,
It is possible to further improve the breakage resistance by designing by combining the above embodiments appropriately. For example, the third or fourth embodiment described above is a combination of the second embodiment and can be regarded as an application of the second embodiment.

Further, the corner portion of the guard ring area can have the same effect even if the corner portion is not a curved pattern but is angular. Further, although the n-channel type IGBT is shown as an example, the same effect can be achieved also in the p-channel type IGBT which has the opposite conductivity type. Further, the first semiconductor layer is n ⁺
The same effect can be achieved for the layered MOSFET.

[Brief description of drawings]

FIG. 1 is a partially enlarged plan view pattern diagram of an IGBT showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line aa ′ in FIG.

FIG. 3 is a sectional view taken along line b-b ′ in FIG.

FIG. 4 is a partially enlarged plan view showing a second embodiment of the present invention.

5 is a cross-sectional view taken along the line aa 'in FIG.

6 is a sectional view taken along the line b-b 'in FIG.

FIG. 7 is a partially enlarged plan view showing a third embodiment of the present invention.

8 is a cross-sectional view taken along the line aa 'in FIG.

9 is a sectional view taken along the line b-b ′ in FIG. 7.

FIG. 10 is a partially enlarged plan view showing a fourth embodiment of the present invention.

11 is a cross-sectional view taken along the line aa 'in FIG.

12 is a sectional view taken along the line b-b 'in FIG.

FIG. 13 is a sectional view showing a conventional IGBT.

FIG. 14 is a plan pattern diagram of a conventional IGBT.

[Explanation of symbols]

1 P ⁺ layer 2 n ^- layer 3 p layer 4 p layer 5 guard ring portion 6 n ⁺ layer 8 gate electrode 9 p layer 11 source electrode 12 drain electrode 15 gate electrode routing line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-3-12970 (JP, A) JP-A-58-25264 (JP, A) JP-A-4-229661 (JP, A) JP-A-5- 198816 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (8)

(57) [Claims] 1. A straight line portion and a straight line in the contour of the plane shape.
Cell area having a corner portion and the outer periphery of the cell area
The outer peripheral portion of the semiconductor substrate, and the cell region is on the one side of the semiconductor substrate.
A second conductivity type high-resistance layer formed on the first conductivity type well region formed in plurality on one side of the high resistance layer, the formed U El region Te individual smell the well region 2 Conductivity type source region, in the individual well region
A serial source region and adjacent gate electrode formed through a gate insulating film a table surface on at least the channel region as a channel region of said well region, a source in contact common to the source region of the respective well regions the electrode
And the outer peripheral portion extends the gate electrode to form the individual electrodes .
Before set to the channel region in the well region
Comprising <br/> gate electrode lead wire for connecting the serial gate electrodes in common, further wherein the <br/> insulated gate field effect transistor having a drain electrode on the other surface of the semiconductor substrate, wherein in the outer peripheral portion On the one surface side of the high resistance layer, the
Along the straight line portion and the corner portion of the cell region, the first semiconductor region of a first conductivity type formed, at a position corresponding to the corner portion of the cell region
Te, wherein in said the first semiconductor region to set the first contact portion, the source <br/> over scan electrodes are extended to the first contact portion above the source electrode of the first contact portion a 1 direct contact with the semiconductor region, and at the position corresponding to the corner portion, the first contact
Insulated gate field effect transistor, characterized in that extended along the corner of the section. 2. The gate electrode routing line is the first
The insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor is disposed on the semiconductor region . Wherein said gate electrode lead wire, the first
The insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor is arranged on the outer peripheral side of the contact portion. 4. A position corresponding to the straight line portion of the cell region.
In the above configuration, the first semiconductor region has a linear portion, and a gate electrode extension portion that connects the gate electrode and the gate electrode routing line in the cell region in a portion that is the linear portion. The insulated gate field effect transistor according to claim 1, wherein the source electrode and the second contact portion that directly contact the first semiconductor region are alternately arranged. 5. Corresponding to the corner portion in the cell area
A second semiconductor region of the first conductivity type is provided between the well region and the first semiconductor region at a position where the second semiconductor region is connected to the source electrode in the cell region . The insulated gate field effect transistor according to any one of 1 to 4. 6. Corresponding to the corner portion in the cell area
The insulated gate field effect transistor according to any one of claims 1 to 4, wherein the source region is not arranged in the well region at a position . 7. The source in the cell region on the first semiconductor region on the outer peripheral side of the gate electrode routing line.
The source electrode lead line connected to the electrodes are arranged, the gate
The insulated gate field effect transistor according to claim 1 , wherein the source electrode routing line is in contact with the first semiconductor region on the outer peripheral side of the gate electrode routing line. 8. The insulated gate field effect transistor according to claim 1, wherein a region of the semiconductor substrate in contact with the drain electrode is of a first conductivity type.