JP3473689B2 - Digital signal processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DSP (digital signal processor) used for various digital signal processing, and more particularly to a microprogram capable of efficiently using an arithmetic unit and to be executed. The present invention relates to a digital signal processing device capable of improving the easiness of writing.

[0002]

2. Description of the Related Art Conventionally, a DSP (Digital Signal Processor) for performing various digital signal processing at high speed has been known. The DSP has an arithmetic unit for performing multiplication and addition. Since the processing speed of the arithmetic unit (especially the multiplication circuit) is slower than that of other units, there are quite a few that are operated by a so-called pipeline method.

Since the operation is performed in the pipeline system, the conventional DSP is restricted by the microprogram.
That is, since the multiplier of the arithmetic unit is slower than the execution speed of one step of the microprogram (it takes one step or more to output the result of multiplication), the multiplication result can be used immediately in the next step of the multiplication instruction. However, there is a problem in that processing cannot be performed continuously in this sense.

For example, let us consider a case in which the calculation a × b × c is performed. Also assume that the multiplier takes two steps to produce the result. At this time, if the multiplication of a × b is performed in the first step, the result cannot be obtained in the second step, and is obtained in the third step. Therefore, the result of the previous a × b (held in the register) after the third step
And the coefficient c must be multiplied. of course,
The second step is not completely wasted and another instruction can be executed. Since the arithmetic unit including the multiplier performs pipeline processing, it is possible to write a multiplication instruction in the second step, for example.

[0005]

In the conventional DSP, the program could not be written continuously in this way. It suffices to use a multiplier that can complete the multiplication in one step, but it is very expensive. Also, it is possible to reduce the number of steps of the microprogram executed per sampling period, but the performance is improved by increasing the number of steps rather than by doing so.

Further, in the conventional DSP, it is necessary to write the microprogram in consideration of the timing of the calculation result. Further, there is a drawback that the program cannot be easily read because operations that are unrelated to each other appear alternately, and that debugging also takes time.

The present invention aims to improve the DSP.
It is another object of the present invention to provide a digital signal processing device which facilitates the development of a microprogram and makes the developed microprogram easy to read.

[0008]

To achieve the above object, according to an aspect of the digital signal processing apparatus according to claim 1, micro which stores a plurality of micro-program of the microinstruction of a plurality steps to be performed for each sampling period
A program storage means, a plurality of data storage means and a plurality of data storage means.
Number coefficient storage means, read means for sequentially reading the microinstructions of the plurality of microprograms from the microprogram storage means at each sampling cycle, and a matrix for each sampling cycle by the read means.
The read microphone is synchronized with the reading of the black instruction.
(B) Data storage means and coefficient storage means corresponding to the instruction
Data and coefficients from the
Switching means for switching and switching according to the read microinstruction and in synchronization with the reading of the microinstruction.
Read from the replaced data storage means and coefficient storage means
The output data and coefficient are used to perform digital signal processing in a pipeline manner and
And a signal processing means for storing the result of the digital signal processing in a predetermined data storage means , wherein the reading means is configured to execute a microinstruction in the signal processing means for performing an operation in the pipeline system. Each of the plurality of microprograms is read for one step in each of the plurality of step periods until the corresponding calculation result is obtained, and by repeating this, the plurality of microprograms are time-divisionally parallel in each sampling cycle. And the processing result of the microinstruction in any one step of the microprogram is made available to the microinstruction in the next step of the microprogram. It is characterized by being

For example, the storage means is a first storage means for storing a first microprogram, a second storage means for storing a second microprogram, ..., And an nth storage means.
In the case where it is configured by the n-th (n is an integer of 2 or more) storage means for storing the micro program, the first micro instruction of the first micro program and the first micro instruction of the second micro program. , ..., and the first microinstruction of the nth microprogram, in that order, and then the second microinstruction of the first microprogram, the second microinstruction of the second microprogram ,. The second microinstruction of the nth microprogram is read in this order, and then the third microinstruction of the first microprogram, the third microinstruction of the second microprogram, ..., And the nth microprogram. Read the third micro-instruction in this order, ...
In this way, each micro instruction is read and executed.

The signal processing means is, for example, a data register, a coefficient register, and an arithmetic unit (multiplier, adder, etc.) for inputting and arithmetically operating the data of the data register and the coefficient register and storing the arithmetic result in the data register. And performs digital signal processing according to the read microinstruction. It is assumed that the portions other than the arithmetic unit, such as the data register and the coefficient register, have sufficient areas to execute a microprogram of a plurality of steps. For example, for data registers and coefficient registers, prepare an area for the number of steps of the microprogram (that is, the number of microinstructions), and use the areas of the corresponding data registers and coefficient registers in synchronization with the microinstructions to be read. You may

[0011] The invention according to claim 2, in claim 1, each microprogram stored in the microprogram storage unit, which each, provided with effect adding program and connection program, each effect
The result-adding program individually responds to the input music signal.
Performs processing to add and output one independent effect
Is a program, and the connection program is each effect described above.
A program that defines the input / output relationship of music signals between additional programs.
It is a program .

According to a third aspect of the present invention, the invention according to the second aspect further comprises means for changing only the connection program without changing the effect addition program of each of the plurality of micro programs in the micro program storage means. Is characterized by.

According to a fourth aspect of the present invention, there is provided a digital signal processing device comprising a program supply means for sequentially outputting microinstructions of respective steps of a plurality of types of programs each composed of a plurality of steps of microinstructions, and a plurality of data storages.
Means and a plurality of coefficient storage means, and the program supply
The means is one of the programs of the plurality of types.
The micro-instruction is output in synchronization with whether the micro-instruction is output.
Data storage means and coefficients corresponding to stored microinstructions
Data and coefficient are read from the storage means
Switching means for switching as described above, and the program supply
According to the micro instruction output from the means, and
Data description switched in synchronization with microinstruction output
Data read from storage means and coefficient storage means
And a coefficient are used to perform a digital operation in a pipeline method according to the plurality of types of programs , and
Store the result of digital operation in a predetermined data storage means
That includes a single operating means, said program supplying means, one step of each of the plurality of microprograms over several step period until the corresponding operation result from the execution of the microinstruction is obtained in said calculating means It is characterized in that it outputs the micro instruction of.

[0014] The invention according to claim 5, in claim 4, each microprogram output from said program supplying means, which respectively, with the effect additional programs and forming <br/> line program, Each effect addition professional
Gram is independent for each input music signal
A program that adds and outputs one effect
The connection program is
A program that defines the input / output relationship of music signals between rams
Characterized in that there.

According to a sixth aspect of the invention, in the fifth aspect, the invention further comprises means for changing only the connection program without changing the effect addition program of each of the plurality of microprograms in the program supply means. Characterize.

[0016]

The operation part of the digital signal processing means is one which requires a plurality of steps from the input of data to the output of the operation result (pipeline system).
According to the above configuration, the microinstructions of different microprograms (one microprogram means a set of a series of microinstructions for performing one function) are sequentially executed. Therefore, focusing on a certain microprogram, after the first microinstruction is read and executed, the next second microinstruction is executed after the elapse of a predetermined number of steps, and then the predetermined second microinstruction is executed. After the time corresponding to the number of steps has elapsed, the next third microinstruction is executed, and the process proceeds as follows.

As a result, the arithmetic unit does not have to play, and on the other hand, the microprogram does not need to be written in consideration of the timing of the arithmetic result.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block configuration of a digital signal processor (DSP) according to a first embodiment of the present invention. Figure 2 shows various effects (distortion and reverberation) of this DSP on digital musical tone signals of electronic musical instruments.
The block configuration of the electronic musical instrument used as the effect addition device for adding (.

An electronic musical instrument using the DSP of this embodiment will be described with reference to FIG. This electronic musical instrument includes a panel switch (SW) 201, a panel SW interface (I / F) 202, a keyboard 203, a keyboard I / F 204,
Central processing unit (CPU) 205, random access
Memory (RAM) 206, read only memory (R
OM) 207, sound source 208, DSP 209, digital-to-analog converter (DAC) 210, sound system 211, and data address bus 212.

The panel switch (SW) 201 is a switch group for making various settings such as tone color and effect. The panel SW interface (I / F) 202 is an interface for notifying the CPU 205 of operation information and setting information of the panel switch (SW) 201 via the bus 212. The keyboard 203 is a keyboard provided with a plurality of keys for the performer to play. Performance information from the keyboard 203 is input to the CPU 205 via the keyboard I / F 204 and the bus 212.

The sound source 208 generates a digital musical tone signal according to an instruction from the CPU 205. DSP209 is C
In accordance with an instruction from the PU 205, various effects are added to the digital tone signal from the sound source 208. The digital musical tone signal after the effect is added is converted into an analog signal by the DAC 210 and is emitted by the sound system 211.

The sound source 208 operates on the basis of a clock signal having a predetermined sampling period and outputs a digital musical tone signal. In this embodiment, for convenience of explanation, the sound source 20
8 outputs one waveform amplitude value data for each sampling period. Note that the present invention is not limited to this, and it is obvious that the present invention can be applied to the case of performing processing of a plurality of channels or left and right stereo processing in one sampling cycle by time division multiplexing processing.

The CPU 205 controls the operation of the entire electronic musical instrument. In particular, the CPU 205 gives a tone generation instruction to the sound source 208 according to the performance information sent from the keyboard 203. When the effect to be added to the musical sound is set on the panel SW201, the CPU 205 reads out an effect program (microprogram) for adding the instructed effect to the musical sound signal from the ROM 207 and then DSP.
Send to 209.

For example, when it is desired to add distortion and reverberation to a musical sound, the distortion addition program and the reverberation addition program are sent to the DSP 209. DSP2
09 executes these microprograms to add an effect to the tone signal from the sound source 208.

The RAM 206 is used for various working areas. The ROM 207 stores a program executed by the CPU 205, a microprogram for adding various effects, and the like.

Next, referring to FIG. 1, the DSP 20 of FIG.
9 will be described in detail.

The DSP 209 has an input register 101, data registers 102 and 103, and coefficient registers 104 and 1.
05, selectors 106 to 112, multiplier 113, delay circuit 114, adder 115, microprogram registers 116 and 117, latch 118, external delay RAM 11
9, address control (address control circuit) 12
0, address registers 121 and 122, and a clock generator 125. Adder 115, external delay R
The AM 119 and the latch 118 are connected to each other by the DSP data bus 124.

Reference numeral 212 is a CPU bus (data address bus in FIG. 1) to which the DSP 209 is connected.
The DSP 209 is configured by one chip except the external delay RAM 119. The external delay RAM 119 is externally provided because of its large capacity.

The input register 101 is a sound source 208 of FIG.
It is a register for taking in the digital tone signal from. While the input data is being supplied from the sound source 208, the microprogram register 116 or 117
The write signal from is input to the input register 101, whereby the data is stored (acquired) in the input register 101.

The data registers 102 and 103 temporarily store the calculation result from the adder 115 and the external delay RA.
The data from M119 is temporarily stored. The data registers 102 and 103 are provided with a plurality of areas for storing these data, and the microprogram registers 116 and 117 are used for writing, reading and addressing.
Is performed by the microprogram stored in the memory (specifically, the microinstruction read from the microprogram registers 116 and 117).

The coefficient registers 104 and 105 are registers having a plurality of areas for storing coefficient data sent from the CPU 205 of FIG. 2 via the CPU bus 212. The read data from the coefficient register 104 is input to the A terminal of the selector 112, and the read data from the coefficient register 105 is input to the B terminal of the selector 112. The selector 112 selects any of these input data according to the clock φ1 and outputs it to the multiplier 113. Specifically, in the selector 112, when the clock φ1 is H
When (High), the input data of the A terminal is selected and output,
When the clock φ1 is L (Low), the input data of the B terminal is selectively output.

The coefficients stored in the coefficient registers 104 and 105 are stored in the CPU of FIG.
It can be rewritten from 205 in real time. As a result, coefficients such as filter calculation can be changed according to the user's operation of the external controller, and timbre can also be controlled in real time.

The selector 108 includes the data register 102.
Data from, constant "1", or input register 101
It is a selector that selects and outputs any of the data from. The selector 109 is a selector that selects and outputs either the data from the data register 103, the constant “1”, or the data from the input register 101. The reason that there is a constant "1" is that it is necessary when only the adder is used by allowing the multiplier 113 to pass through.

The selector 106 includes the data register 102.
From the DSP data bus 124 (adder 115
Alternatively, it is a selector for selecting and outputting either the data from the external delay RAM 119) or the constant "0".
The selector 107 is a selector that selects and outputs either data from the data register 103, data from the DSP data bus 124 (adder 115 or external delay RAM 119), or a constant “0”. Selector 1
The selection output of the constant "0" in 06 and 107 is because there is a case where it is desired to give the constant "0" to the adder 115 and to let the multiplication result of the multiplier 113 pass through.

Each of these selectors 108, 109, 10
The selection processing in 6 and 107 is performed in accordance with the micro instruction read from the micro program registers 116 and 117.

The selector 110 includes the data from the selector 106 input to the A terminal and the selector 1 input to the B terminal.
Any of the data from 07 is selected and output. Selector 1
The output of 10 is input to the adder 115 after being delayed for a predetermined time by the delay circuit 114. Selector 111
Is the data from the selector 108 input to the A terminal and B
Any of the data from the selector 109 input to the terminal is selected and output.

These selectors 110 and 111 select and output the input data of the A terminal when the clock φ1 is H,
When the clock φ1 is L, the input data of the B terminal is selected and output.

The output of the selector 111 is input to the multiplier 113. The multiplier 113 multiplies the output data from the selector 111 and the output data from the selector 112, and outputs the multiplication result to the adder 115.

The adder 115 adds the output of the delay circuit 114 and the output of the multiplier 113 and outputs the addition result to the DSP data bus 124. Multiplier 113, delay circuit 11
4 and the adder 115 constitute an arithmetic unit. This computing unit is assumed to be capable of computing 256 times (that is, 256 steps) per sampling period.

Further, the multiplier 113 and the adder 115 are assumed to operate in a pipeline system, and the multiplication by the multiplier 113 is performed halfway in the first step, and the multiplication and the multiplication result from the middle are performed in the next second step. It is assumed that the adder 115 is used to perform addition (at that time, the multiplier 113 is performing another multiplication). The delay circuit 114 is
This is for adjusting the timing of input to the adder 115.

Micro program registers 116 and 11
7 is executed in one sampling period 12
It stores a microprogram consisting of 8-step microinstructions. That is, the micro program registers 116 and 117 are 128-stage shift registers (one stage stores one microinstruction step) that makes one revolution in one sampling cycle. The micro program register 116 is read (one micro instruction) in the section where the clock φ1 is H, and the micro program register 11
In the case of 7, the clock φ1 bar (inversion of φ1) is read in the H section (1 microinstruction).

When changing the type of effect, this microprogram is rewritten. The microprogram to be rewritten is the CPU bus 212.
2 are stored in the ROM 207 of FIG. The CPU 205 of FIG. 2 designates a panel SW201 or a tone color designation, or a program change or the like, and a microprogram corresponding to the designation is stored in the ROM.
Read from 207 to microprogram register 11
Write in 6, 117.

The latch 118 is for latching and outputting the digital musical tone signal after the effect is added. This latch output is connected to the external DAC 210 and converted into an analog signal.

The external delay RAM 119 is used to generate a delayed signal. The writing / reading is performed by a microprogram (microprogram registers 116, 1
It is instructed by the microinstruction read from 17. The address for writing / reading is output from the address control 120. The address control 120 is a control circuit that adds an address offset in order to convert a relative address output from the address registers 121 and 122 into an absolute address. The address offset is the output of the address counter, and is composed of a subtraction counter that subtracts the address range corresponding to the storage area of the delay RAM 119 by 1 for each sampling period.

The address registers 121 and 122 are relative addresses in which the leading address of the external delay RAM 119 is regarded as 0, and access timings corresponding to microprograms (specifically, microinstructions read from the microprogram registers 116 and 117). Is stored so that the desired address is output.

The clock generator 125 supplies the clock φ1 and the clock φ1 bar to each part of the DSP. The clock φ1 is a clock signal that alternately repeats L level and H level at predetermined time intervals. The clock φ1 is included for 128 cycles per sampling cycle. That is, L is 128 sections and H is 1 in one sampling period.
It will be included in 28 sections (FIG. 5). Clock φ1
The bar is a signal obtained by inverting L and H of the clock φ1. It should be noted that one time period in which H (or L) is maintained in the clocks φ1 and φ1 bar is simply referred to as a period.

As described above, the microprogram registers 116 and 117 store microprograms each consisting of a series of 128-step microinstructions executed in one sampling cycle, and are alternately stored based on the clocks φ1 and φ1 bar. It is read one microinstruction at a time. That is, the micro instruction is read from the micro program register 116 and executed in the section where the clock φ1 is H, and the micro instruction is read from the micro program register 117 in the section where the clock φ1 bar is H (that is, the section where the clock φ1 is L). It is issued and executed. Therefore, in terms of the DSP as a whole, 256-step micro-instructions are read and executed in one sampling cycle.

Now, paying attention to the microprogram of the microprogram register 116 that is read and executed in the section where the clock φ1 is H, the calculation performed by the calculation unit according to this microprogram is 1 per sampling cycle.
Since there are 28 steps, the data register 102 and the coefficient register 104, which are also read in the section where the clock φ1 is H, must supply different data and coefficients (if necessary) at each step of the operation. Therefore, each of the data register 102 and the coefficient register 104 is composed of a shift register of 128 stages and makes one rotation in one sampling cycle.
Similarly, the address register 121 is also a 128-stage shift register that makes one rotation in one sampling cycle.

Similarly, the coefficient register 105 for storing the coefficients and addresses used in the microprogram 117 and the address register 122 are also 128-stage shift registers that rotate once in one sampling cycle.

Although omitted in the DSP of FIG. 1,
An interpolator that interpolates the coefficients of the coefficient register and outputs them to the arithmetic unit, and an LFO (low frequency oscillator) that outputs a modulation waveform (triangular wave, sawtooth wave, sine wave, etc.) for performing amplitude modulation, delay time modulation, etc. May be provided.

FIG. 3 shows the microprogram register 11
6, 117, coefficient registers 104 and 105, and address registers 121 and 122 are shown as an example. FIG. 4A is a block diagram showing how the DSP of FIG. 1 that operates by storing the data of FIG. 3 functions as an effect addition device.

Referring to FIG. 3, microprogram P1 is stored in microprogram register 116.
The micro program P1 consists of 128 steps of micro instructions. Coefficient data 314 of the coefficient register 104
Is coefficient data corresponding to the micro instruction of each step of the 128 step micro program P1. Also, the address data 315 of the address register 121
Is address data corresponding to the microinstruction of each step of the 128-step microprogram P1.
The microprogram P1 is roughly divided into three parts 31
1, 312, 313.

Reference numeral 311 in FIG. 3 is a connection program for storing the input signal (waveform amplitude value data from the sound source 208) in the input register 101, reading it, and supplying it to the multiplier 113 of the arithmetic unit. Specifically, it is a program that performs the following processes.

The input signal is stored in the input register 101. The selector 108 is switched to supply the data of the input register 101 to the A terminal of the selector 111. (The micro program P1 is read when the clock φ1 is H, and the selector 111 selectively outputs the A terminal at this time.) Therefore, the input data of the A terminal is supplied to the multiplier 113 via the selector 111.

Reference numeral 312 in FIG. 3 is a distortion adding program for adding distortion to the input signal. Specifically, this is a program that performs the following processes.

The multiplier 113 multiplies the data supplied from the selector 111 and the selector 112. The coefficient data to be multiplied is the coefficient register 10
4 according to a micro instruction, and the selector 112
The one input to the multiplier 113 via (the clock φ1 is H and the A terminal is selectively output) is used.

The adder adds the data of the delay circuit 114 and the multiplication result of the multiplier 113. As the data of the delay circuit 114, the data from the data register 102 or the data from the adder 115 or the external delay RAM 119 obtained via the DSP data bus 124 is selected by the selector 106 according to the micro instruction, and further the selector 110 is selected. It is input to and held in the delay circuit 114 via (the clock φ1 is H and the A terminal is selectively output).

The addition result of the adder 115 is written to the delay circuit 114 via the DSP data bus 124 and the selectors 106 and 110, or the DSP data bus 12 is used.
External delay RAM 119 and data register 10 via
Write to 2. Where to write is instructed by the read microinstruction. In particular, the external delay RAM 11
When writing to 9, an address obtained by converting the relative address read from the address register 121 into an absolute address by the address control 120 is used.

If necessary, the data in the external delay RAM 119 is written in the data register 102 or the delay circuit 114. This is a case where data delayed for a predetermined time is used.

The data is read from the data register 102 and supplied to the multiplier 113 via the selectors 108 and 111. Also, coefficient data is read from the coefficient register 104, and the coefficient data is supplied to the multiplier 113 via the selector 112. Data register 1
The designation of the read address 02 and the selection by the selector 108 are designated by the read micro instruction.

By repeating the above-mentioned processes (1) to (3), the calculation is repeated to obtain the final calculation result. The calculation result is a musical tone signal with distortion added.

Reference numeral 313 in FIG. 3 is a connection program for storing the calculation result in a predetermined area A1 of the data register 103. This performs a process of setting the calculation result output from the adder 115 in a predetermined area A1 of the data register 103 via the DSP data bus 124.

Next, the microprogram P2 will be described. The micro program register 117 stores the micro program P2. Micro program P
2 is composed of 128-step microinstructions, like the microprogram P1. The coefficient data 324 of the coefficient register 105 is the 128-step microprogram P.
2 is coefficient data corresponding to the micro instruction of each step of 2. The address data 325 of the address register 122 is the address data corresponding to the micro instruction of each step of the 128-step micro program P2. The microprogram P2 is roughly composed of three parts 321, 322, 323.

Reference numeral 321 in FIG. 3 is a connection program for reading data from a predetermined area A1 of the data register 103 and supplying it to the multiplier 113 of the arithmetic unit. In particular,
It is a program that performs the following processes.

The selector 109 is switched to switch the data in the predetermined area A1 of the data register 103 to the selector 11
Supply to the B terminal of 1. A predetermined area A1 of the data register 103 stores a calculation result (that is, a tone signal to which distortion is added) calculated by the microprogram P1 in the previous one sampling period.

(The micro program P2 is read out when the clock φ1 bar is H, and the selector 111 selects and outputs the B terminal at this time.) Selector 1
The data of the B terminal is supplied to the multiplier 113 via 11.

Reference numeral 322 in FIG. 3 is a reverberation adding program for adding a reverberation effect to the input data. The processing procedure of the reverberation adding program 322 is the same as that of the distortion adding program 312 described above. However, since the micro program P2 is read out when the clock φ1 bar is H, the selectors 110, 111, 112 are
Selects and outputs the input of the B terminal, whereby the data register 103 and the coefficient register 105 are used. Further, the address register 122 is used. Furthermore, as a matter of course, the calculation to be performed is a calculation for adding reverberation.

Reference numeral 323 in FIG. 3 is a connection program for storing the calculation result (musical tone signal with reverberation) stored in a predetermined area A2 of the data register 103, and for further effect balance calculation. This is specifically the following ~
It is a process like.

The output data from the reverberation adding program 322 output from the adder 115 is stored in a predetermined area A2 of the data register 103 via the DSP data bus 124.

The effect balance calculation of the input signal stored in the input register 101 and the effect-added data stored in the predetermined area A2 is performed. That is, first, the data of the input register 101 is set to the selector 10
It is supplied to the multiplier 113 via 9, 111 and is multiplied by a predetermined coefficient k1 (k1 is read from the coefficient register 105 via the selector 112), and the multiplication result and 0 are added in the adder 115. ,) The multiplication result is stored in a predetermined area A3 of the data register 103. Next, similarly, the data in the predetermined area A2 is multiplied by a predetermined coefficient k2,
The multiplication result and the data in the predetermined area A3 of the data register 103 are added. As a result, the effect balance calculation is completed, and the final output signal is obtained.

The output signal finally obtained is latched 11
8 and output to the outside.

As described above, by operating based on the microprogram as shown in FIG. 3, D of FIG.
SP is equivalent to the effect adding device as shown in FIG.

In FIG. 4A, 401 is a distortion adding section for adding distortion to the input signal,
Reference numeral 402 is a reverberation adding unit that adds reverberation to the signal to which distortion is added, 403 is a multiplication unit that multiplies the input signal by a coefficient k1, 404 is a multiplication unit that multiplies a signal to which distortion and reverberation are added by a coefficient k2, and 405 is Multiplication unit 4
It is an addition unit that adds the multiplication result of 03 and the multiplication result of the multiplication unit 404.

The correspondence with the microprogram of FIG. 3 is as follows.

First, the connection of the input signal input to the distortion adding section 401 of FIG. 4A corresponds to the connection program 311 of the microprogram P1 of FIG. The distortion addition unit 401 of FIG. 4A corresponds to the distortion addition program 312 of FIG. Figure 4
The connection from the distortion adding unit 401 to the reverberation adding unit 402 in (a) corresponds to the connection program 313 of the micro program P1 and the connection program 321 of the micro program P2 in FIG.

The reverberation adding unit 402 in FIG. 4A corresponds to the reverberation adding program 322 in FIG. The input signal of FIG. 4A is input to the multiplication unit 403 and is multiplied by the coefficient k1, and the output of the reverberation addition unit 402 is input to the multiplication unit 404 and the coefficient k is input.
The part that multiplies by 2 and adds the multiplication results by the addition unit 405 and outputs the result corresponds to the connection program 323 in FIG. 3.

The data registers 102 and 10 shown in FIG.
3 has a plurality of areas (addresses) and is composed of a dual port RAM which can be accessed by either of the programs P1 and P2. This allows the programs P1 and P2 to use common data, and by passing the data, it is possible to freely connect different effects as shown in FIG.

FIG. 5 is a time chart showing the input / output timings of the clocks φ1 and φ1 bars and the selector and the arithmetic unit. The operation of alternately executing the microprogram programs P1 and P2 will be described in more detail with reference to this figure.

In FIG. 5, for clocks φ1 and φ1 bar, clock signals for 128 cycles are included in one sampling period. Also, one sampling period is 2
It is equal to 56 sections (one section is one time section in which H (or L) is maintained).

In the section where the clock φ1 is H, the micro instructions of the micro program P1 in FIG. 3 are sequentially read from the micro program register 116, and in this section, the selectors 110, 111 and 112 select and output the input of the A terminal, respectively. To do. Further, the address data of the address register 121 is used as the address data. Therefore, in this section, the data register 10
2, coefficient register 104, and address register 12
The data of 1 is used (if necessary), and the 128-step microinstruction of the microprogram P1 is executed.

In the section where the clock φ1 is L (that is,
3 is sequentially read from the micro program register 117 during the period in which the clock φ1 bar is H), and in this period, the selectors 110, 111 and 112 select and output the input of the B terminal, respectively. Further, the address data of the address register 122 is used as the address data. Therefore, in this section, the data in the data register 103, the coefficient register 105, and the address register 122 are used (as needed), and the microprogram 117 is used.
The 128-step microinstruction of the microprogram P2 of FIG.

In FIG. 5, "selectors 110, 111, 11
2 "indicates that the terminals selected by these selectors are switched alternately between the A terminal and the B terminal in accordance with the clocks φ1 and φ1 bars. The "arithmetic unit input" and the "arithmetic unit output" indicate that the arithmetic operations are alternately performed by the micro instructions of the micro programs P1 and P2 according to the clocks φ1 and φ1 bar. Since the multiplier 113 and the adder 115 that form the arithmetic unit perform processing in a pipeline system, for example, the arithmetic result is output to the data input to the arithmetic unit in the section 501 by the microinstruction of the microprogram P1. Next, not the section 503 but the next next section 502. In the section 503, the calculation by the micro instruction of the micro program P2 is performed.

As described above, the calculation unit does not output the calculation result in one section but outputs the calculation result in the next section after one section. In accordance with this, the micro program is output according to the clocks φ1 and φ1 bars. Since P1 and P2 are executed alternately, the arithmetic unit does not play. In other words, even if you write a microprogram that inputs data to the operation unit at a certain step (called step) to instruct the operation and uses the operation result at the next step (called step), After the executed section, 1
Since the step is executed in the next section after the section, and the calculation result of the step has already been output at that time, the processing can proceed without any problem.

In the above embodiment, an example in which two effect adding portions are connected in series as shown in FIG. 4A has been described.
Other ways of connection are possible. For example, an effect adding device as shown in FIG. 4B can be realized. In this case, it is not necessary to change the programs 312 and 322 of the microprogram of FIG. Also,
Connection programs 311 and 31 of the micro program P1
There is no need to change 3.

The connection program 321 of the microprogram P2 is changed to "read an input signal from the input register 101 and supply it to the arithmetic section", and the connection program 3
23, “Calculation result is the predetermined area A of the data register 103
2 and then the input register 101, the predetermined area A1 of the data register 103, and the data register 103.
“Calculate the effect balance using the data of the predetermined area A2”. Further, coefficient data and address data may be changed as necessary.

In the first embodiment, the distortion and reverberation effect are processed as one output signal by serial or parallel processing with respect to one input. However, the present invention is not limited to this. It is also possible to give completely independent effects and output as two output signals.

Next, a second embodiment of the present invention will be described.

FIG. 6 shows the block configuration of the DSP of the second embodiment. In this figure, the same numbering as in FIG. 1 indicates the same number. Like the DSP of the first embodiment, this DSP also functions as an effect imparting device for an electronic musical instrument as shown in FIG.

FIG. 7 shows a block configuration of an effect addition device realized by the DSP of FIG. This effect adding device is roughly divided into an equalizer section 701 and an effect section 702. Here, it is assumed that four input signals are input and finally an L side (left side) output and an R side (right side) output are obtained.

The equalizer section 701 is composed of 12 equalizers EQ1 to EQ12. Input 1 which is the first input signal has equalizers EQ1, EQ1 connected in series.
It is input to the effect unit 702 via EQ2 and EQ3. Input 2, which is the second input signal, is input to the effect unit 702 via the equalizers EQ4, EQ5, EQ6 connected in series. Input 3, which is the third input signal, is
It is input to the effect unit 702 via the equalizers EQ7, EQ8, EQ9 connected in series. The fourth input signal, input 4, is equalizer EQ1 connected in series.
It is input to the effect unit 702 via 0, EQ11, EQ12.

The effect section 702 performs processing for adding a predetermined effect, such as the distortion adding section 401 and the reverberation adding section 402 shown in FIG.

FIG. 8 shows the structure of one equalizer realized by this DSP. This equalizer is an adder 80
1, 804, delay circuits 802, 803, and multiplier 8
11 to 815.

The input data is input to the adder 801.
The adder 801 adds the input data, the multiplication result of the multiplier 811, and the multiplication result of the multiplier 812. The addition result is input to the multiplier 813 and the delay circuit 802. The delay circuit 802 delays the input data by one sampling period and outputs the delayed data to the multipliers 811 and 814 and the delay circuit 803. The multiplier 811 multiplies the input data by the multiplier c1 and outputs the multiplication result to the adder 801. Delay circuit 8
03 delays the input data by one sampling period and outputs the delayed data to the multipliers 812 and 815.

The multiplier 812 multiplies the input data by the multiplier c.
Multiply by 2 and output the multiplication result to the adder 801. The multiplier 813 multiplies the input data by the multiplier c3 and outputs the multiplication result to the adder 804. The multiplier 814 multiplies the input data by the multiplier c4 and outputs the multiplication result to the adder 80.
Output to 4. The multiplier 815 multiplies the input data by the multiplier c5 and outputs the multiplication result to the adder 804. The adder 804 adds the multiplication results from the multipliers 813, 814, 815 and outputs it.

Referring again to FIG. 6, D of the second embodiment
The SP will be described in detail. Of the parts shown in FIG. 6, the parts having the same functions as those in FIG. 1 are given the same numbering, and therefore the parts different from the first embodiment will be described in detail below.

The DSP shown in FIG. 6 has a timing signal generator 616 based on the microprogram memory 116 of the DSP shown in FIG.
, Which realizes an equalizer. Of course, the equalizer can be realized by using a microprogram, but since the equalizer is a simple circuit as described in FIGS. 7 and 8, it can be easily realized by the hardware timing signal generator 616 or the like. It is less time-consuming and more efficient than using a microprogram. Since the timing signal generator 616 is realized by hardware so as to independently generate a predetermined timing signal, it is not connected to the CPU bus 212.

In the DSP of FIG. 1, the microprograms P1 and P2 of the microprogram registers 116 and 117 are alternately read and executed according to the clocks φ1 and φ1 bars, but the DSP of FIG. Are the same. That is, in the DSP of FIG. 6, when the clock φ1 is H, the timing signal generator 616 generates a timing signal (which serves as a microinstruction) to implement the equalizer unit 701 of FIG.
When the clock φ1 bar is H (φ1 is L), the micro instruction is read from the micro program register 117 and the processing for realizing the effect unit 702 of FIG. 7 is performed.

Therefore, the selectors 110, 111 and 11 for switching the input terminals A and B according to the clock φ1.
The provision of 2 is also the same as in FIG. Clock φ1
Focusing on the side of the micro program register 117 executed when the bar is H, a process of adding a predetermined effect is performed using the data of the input register 101, the data register 103, and the coefficient register 105, which is also shown in FIG.
Is the same as.

The output of the coefficient register 105 is as shown in FIG.
Instead of directly inputting to the B terminal of the selector 112 as described above, it is connected via the selector 635. Data from an LFO (low frequency oscillator) 633 is input to the other input terminal of the selector 635. This is one in which the output data of the LFO 633 is used as a multiplier of the multiplier 113 so that the tone signal can be amplitude-modulated. In addition, LFO633
The output of is input to the address control 120. This is so that the delay time modulation can be performed by changing the access address of the external delay RAM 119 according to the LFO output.

Next, the part that realizes the equalizer section 701 of FIG. 7 which is a feature of this embodiment will be described.

The EQ coefficient register 604 is used for the CPU bus 2
2 is a register having a plurality of areas for storing EQ coefficient data sent from the CPU 205 of FIG. The EQ coefficient data corresponds to the multiplier of each multiplier of the equalizer in FIG. The read data from the EQ coefficient register 604 is input to one input terminal of the selector 634. The constant "1" is input to the other input terminal of the selector 634. The output of the selector 634 is input to the A terminal of the selector 112.

The selector 634 performs selective output based on the 1-bit selection control signal generated from the timing signal generator 616. That is, the selection control signal is "0".
When, the EQ coefficient data from the EQ coefficient register 604 is selected and output, and when the selection control signal is "1", it is a constant value.
1 "is selectively output.

The latch 631 is used for the DSP data bus 124.
Latch data from. The output of the latch 631 is input to the selectors 606 and 107, the EQSR 602-1, the selector 608, and the data register 103. EQ
SRs 602-1 and 602-2 are shift registers (12 words each) for realizing the delay circuits 802 and 803 in the equalizer circuit of FIG. EQSR60
The output of 2-1 is the selector 608 and the EQSR 60.
Enter in 2-2. The output of the EQSR602-2 is input to the selector 608. The EQOR 632 is a temporary storage register that stores the output data of one equalizer (FIG. 8). The output of EQOR 632 is the selector 608,
And to the data register 103.

The selector 608 is for selecting the data to be supplied to the multiplier 113. Selector 608
Has five input terminals. These input terminals are called a 0th input terminal, a 1st input terminal, ..., And a 4th input terminal. The selector 608 performs selective output based on the 3-bit selection control signal generated from the timing signal generator 616. This 3-bit selection control signal takes values of 0, 1, 2, 3, 4 when considered as a decimal integer. When the value of the selection control signal is n, the selector 608 selectively outputs the input data of the nth input terminal.

EQ is connected to the 0th input terminal of the selector 608.
Input the data of OR632. E to the first input terminal
The data at the final stage of the QSR 602-1 is input. The data of the final stage of EQSR602-2 is input to the second input terminal. The data of the latch 631 is input to the third input terminal. The data of the input register 101 is input to the fourth input terminal.

The selector 606 is for selecting the data to be supplied to the adder 115. Selector 606
Has three input terminals. Connect those input terminals to the 0th
They are called an input terminal, a first input terminal, and a second input terminal.
The selector 606 performs selective output based on the 2-bit selection control signal generated from the timing signal generator 616. This 2-bit selection control signal takes values of 0, 1 and 2 when considered as a decimal integer. When the value of the selection control signal is n, the selector 606 selectively outputs the input data of the nth input terminal.

The data of the latch 631 is input to the 0th input terminal of the selector 606. The constant "0" is input to the first input terminal. The data of the data register 103 is input to the second input terminal.

Clock generator 125 outputs clocks φ1 and φ1 bar similar to those of FIG. further,
The clock generator 125 outputs the clock φ2. The clock φ2 will be described later.

FIG. 9 shows the timing signal generator 61 of FIG.
6 is a detailed circuit diagram of FIG. Timing signal generator 616
Is a counter 901, an AND circuit (hereinafter, AND) 902, a knot circuit (hereinafter, NOT) 903.
~ 906, AND910-915, OR circuit (hereinafter O
R) 921, 922, 924, and AND92
Equipped with 3.

The counter 901 is a 4-bit counter which receives the clock φ1 and counts up at the timing when the clock φ1 rises from L to H. Of the 4-bit counter output, the 0th power bit and the 2nd power bit of 2 are input to the AND 902, and the output of the AND 902 is input to the reset terminal R of the counter 901, so the counter output becomes 6 (decimal). Will be reset when
As a result, the counter 901 causes the 0, 1, 2, 3, 4,
It is a hexadecimal counter that repeatedly outputs 5.

NOTs 903 to 906 are connected to the respective 4 bits of the output of the counter 901. AND9
The six ANDs 10 to 915 are ANDs that output 1 corresponding to the counter values 0 to 5, respectively.
The correspondence is as follows.

When the counter value is 0 ... AND910 is 1; otherwise 0 When the counter value is 1 ... AND911 is 1; otherwise 0 When the counter value is 2 ... AND912 is 1; otherwise 0 counter value Is 3, AND 913 is 1, otherwise 0 is when the counter value is 4 AND 914 is 1, otherwise 0 is when the counter value is 5 AND 915 is 1, otherwise 0

OR 921, 922 and AND 923
Is for creating a selection control signal (3 bits) to the selector 608 of FIG. OR921 is AN
The outputs of D911, 913, and 914 are input, and the result of the OR operation is output as 2 0 bits of the selection control signal.
The OR 922 inputs the outputs of the ANDs 912, 913, 915, and outputs the result of the OR operation as the 1st power of 2 bits of the selection control signal. AND923 sets clock φ2 and A
The output of the ND 910 is input, and the result of the AND operation is output as 2 square bits of the selection control signal.

A numerical value enclosed in [] is shown below each bit output of the selection control signal to the selector 608. This means that the corresponding bit becomes 1 when the counter value is the numerical value. Shows. That is, it is as follows.

The 2nd power of 0 bit of the selection control signal is 1 when the counter values are 1, 3, and 4, and is 0 otherwise. The 2nd power bit of the selection control signal has a counter value of 2,
It becomes 1 when it is 3, 5 and 0 otherwise. The counter value of the 2nd power bit of the selection control signal is 0.
It becomes 1 when (and the clock φ2 is 1), and becomes 0 otherwise.

The output of AND913 is EQSR602-.
It is output as a write instruction signal to 1. Since the write instruction is represented by 1, the write instruction is issued when the counter value is 3. However, in more detail, using an unillustrated latch, the output from the latch 631 is temporarily latched at the timing when the counter value is 3, and the EQOR
EQSR6 at the same timing as the write signal to 632
02-1 is written in the first stage.

The output of AND 910 is output as a selection control signal to selector 634. This selection control signal takes 1 when the counter value is 0, and takes 0 otherwise.

The OR 924 is for creating a selection control signal (2 bits) to the selector 606. OR
924 inputs the outputs of AND 913 and 910, and ORs
The result of the operation is output as 2 0 bits of the selection control signal. As a result, the 2 0th bit of the selection control signal is
It becomes 1 when the counter value is 0 and 3, and becomes 0 otherwise. 0 is always output as the 2nd power bit of the selection control signal.

FIG. 10 is a time chart showing the signal states of the respective parts when the equalizer 701 of FIG. 7 is realized by the DSP of FIG. Referring to FIG. 10, the DSP of FIG.
Will be described in detail.

In FIG. 10, 0 to 127 are separated by vertical bars as "steps", but this means that 128 sampling intervals operating in response to the timing signal from the timing signal generator 616 in one sampling period. Shows. Each section separated by a vertical bar can be regarded as a section in which the clock φ1 is H. Actually, there is a section where the clock φ1 is L at the position of this vertical bar, and the microprogram of the microprogram register 117 is executed in that section. Here, in order to explain the operation for realizing the equalizer unit, the drawing is focused on only the section where the clock φ1 is H. Therefore, the selector 110 of FIG.
111 and 112 selectively output the A terminal.

FIG. 10 shows values taken by various timing signals from the timing signal generator 616 described in FIG. 9 at each step. The EQ coefficient register 60
The EQ coefficient data output from No. 4, the clock φ2, and the write instruction signal to the EQOR632 are also shown. The clock φ2 is a clock signal output from the clock generator 625 of FIG. 6, and becomes H every 18 steps.
That is, H at step 0, H at step 18, H at step 36, ... Although not shown in the timing signal generator 616 of FIG. 9, the write instruction signal to the EQOR 632 is a signal that becomes H every 6 steps. Specifically, the output of AND910 is extracted and EQOR6
It may be a write instruction signal to 32.

The steps will be sequentially described below. The counter 901 of the timing signal generator 616 described with reference to FIG. 9 starts counting from step 0. That is, the counter value is 0 in step 0, the counter value is 1 in step 1, the counter value is 2 in step 2,
The counter value is 5 in step 5, the counter value is 0 in step 6, and so on.
repeat.

At step 0, data is fetched from the input register 101. The input register 101 may be a shift register or a simple register. Here, it is assumed that the input 1 which is the first input signal is output from the input register 101 during steps 0 to 5.

At step 0, since the counter value of the timing signal generator 616 of FIG. 9 is 0, the value of the selection control signal input to the selector 608 is 4 as shown in FIG. Therefore, the selector 608 receives the data (input 1) from the input register 101 input to the fourth input terminal.
Is output selectively. This data is supplied to the multiplier 113 via the selector 111.

On the other hand, since the value of the selection control signal input to the selector 634 is 1, the selector 634 selectively outputs the constant "1". This constant “1” is supplied to the multiplier 113 via the selector 112. Also, the selector 606
Since the value of the selection control signal input to the selector 1 is 1, the selector 60
6 selects and outputs the constant "0". This constant “0” is added to the adder 115 via the selector 110 and the delay circuit 114.
To enter.

The arithmetic unit performs the following arithmetic operation and stores the result in the latch 631. (Input 1) × 1 + 0 → (Latch 631) (Equation 0)

Next, in step 1, since the counter value in FIG. 9 is 1, the value of the selection control signal input to the selector 608 is 1, as shown in FIG. Therefore, the selector 608 receives the EQSR 60 input to the first input terminal.
The data from 2-1 is selectively output. EQSR602-
Data Z ^-1 is stored in the last stage of 1. This data Z ⁻¹ is supplied to the multiplier 113 via the selector 111.

On the other hand, since the value of the selection control signal input to the selector 634 is 0, the selector 634 selectively outputs the data from the EQ coefficient register 604. Here, the coefficient c
1 is supplied to the multiplier 113 via the selector 112. Since the value of the selection control signal input to the selector 606 is 0, the selector 606 selectively outputs the data in the latch 631. The data of the latch 631 is the selector 11
It is input to the adder 115 via 0 and the delay circuit 114.

The arithmetic unit performs the following arithmetic operation and stores the result in the latch 631. Z ⁻¹ × c1 + (latch 631) → (latch 631) (Equation 1)

Next, in step 2, since the counter value in FIG. 9 is 2, the value of the selection control signal input to the selector 608 is 2, as shown in FIG. Therefore, the selector 608 receives the EQSR 60 input to the second input terminal.
The data from 2-2 is selectively output. EQSR602-
Data Z ^-2 is stored in the last stage of ² . This data Z ^-2 is supplied to the multiplier 113 via the selector 111.

On the other hand, since the value of the selection control signal input to the selector 634 is 0, the selector 634 selectively outputs the data from the EQ coefficient register 604. Here, the coefficient c
2 is supplied to the multiplier 113 via the selector 112. Since the value of the selection control signal input to the selector 606 is 0, the selector 606 selectively outputs the data in the latch 631. The data of the latch 631 is the selector 11
It is input to the adder 115 via 0 and the delay circuit 114.

The arithmetic unit performs the following arithmetic operation and stores the result in the latch 631. Z ⁻² × c2 + (latch 631) → (latch 631) (Equation 2)

Next, in step 3, since the counter value in FIG. 9 is 3, the value of the selection control signal input to the selector 608 is 3, as shown in FIG. Therefore, the selector 608 has the latch 631 input to the third input terminal.
Selectively output the data from. This data is supplied to the multiplier 113 via the selector 111.

On the other hand, since the value of the selection control signal input to the selector 634 is 0, the selector 634 selectively outputs the data from the EQ coefficient register 604. Here, the coefficient c
3 is supplied to the multiplier 113 via the selector 112. Further, since the value of the selection control signal input to the selector 606 is 1, the selector 606 selectively outputs the constant “0”. This constant “0” is used for the selector 110 and the delay circuit 11
4 to the adder 115.

The arithmetic unit performs the following arithmetic operation and stores the result in the latch 631. (Latch 631) × c3 + 0 → (Latch 631) (Equation 3)

In step 3, the write instruction signal to the EQSR 602 is also output. However, in reality, the process of writing the data of the latch 631 into the latch (not shown) is performed. The latched data is read at the same timing (steps 0, 6, 1) as the write signal to the EQOR 632.
2, rising edge timing) EQSR601-
It is written in the first stage of 1. EQSR601-1 and E
Since the QSR 601-2 is a shift register, the QSR 601-2 sequentially shifts at a predetermined clock, for example, the equalizer E.
While Q1 is being calculated (steps 0-5), EQ
The SR 602-1 continues to output Z ⁻¹ delayed by one sampling period, and the EQSR 602-2 continues to output Z ⁻² delayed by 2 sampling periods. The same applies hereinafter.

Next, in step 4, since the counter value in FIG. 9 is 4, the value of the selection control signal input to the selector 608 is 1, as shown in FIG. Therefore, the selector 608 receives the EQSR 60 input to the first input terminal.
The data Z ^-1 at the final stage of 1-1 is selectively output. This data Z ⁻¹ is supplied to the multiplier 113 via the selector 111.

On the other hand, since the value of the selection control signal input to the selector 634 is 0, the selector 634 selectively outputs the data from the EQ coefficient register 604. Here, the coefficient c
4 is supplied to the multiplier 113 via the selector 112. Since the value of the selection control signal input to the selector 606 is 0, the selector 606 selectively outputs the data in the latch 631. The data of the latch 631 is the selector 11
It is input to the adder 115 via 0 and the delay circuit 114.

The arithmetic unit performs the following arithmetic operation and stores the result in the latch 631. Z ⁻¹ × c4 + (latch 631) → (latch 631) (Equation 4)

Next, in step 5, since the counter value in FIG. 9 is 5, the value of the selection control signal input to the selector 608 is 2, as shown in FIG. Therefore, the selector 608 receives the EQSR 60 input to the second input terminal.
The data Z ^-2 at the final stage of 2-2 is selectively output. This data Z ^-2 is supplied to the multiplier 113 via the selector 111.

On the other hand, since the value of the selection control signal input to the selector 634 is 0, the selector 634 selectively outputs the data from the EQ coefficient register 604. Here, the coefficient c
5 is supplied to the multiplier 113 via the selector 112. Since the value of the selection control signal input to the selector 606 is 0, the selector 606 selectively outputs the data in the latch 631. The data of the latch 631 is the selector 11
It is input to the adder 115 via 0 and the delay circuit 114.

The arithmetic unit performs the following arithmetic operation and stores the result in the latch 631. Z ⁻² × c5 + (latch 631) → (latch 631) (Equation 5)

Next, in step 6, a write instruction signal to the EQOR 632 is output as shown in FIG.
As a result, the calculation result obtained in the above step 5 becomes EQ.
It is stored in OR632.

With the above, the processing of EQ1 (configuration of FIG. 8) in the equalizer section 701 of FIG. 7 is completed. Subsequently, the processing from step 6 to EQ2 is performed.
This is similar to the processing from step 0 above. However, since the clock φ2 is 0 in step 6, the selector 608 output from the timing signal generator 616 is output.
The value of the selection control signal to is 0. Therefore, since the selector 608 selectively outputs the 0th input terminal, the following (Expression 6) is executed instead of the above (Expression 0). (EQOR632) × 1 + 0 → (latch 631) (Equation 6)

As a result, the input from EQ1 to EQ2 in FIG. 7 is supplied.

In this way, the EQ is executed in steps 6 to 12.
2 is performed, and EQ3 is performed in steps 12-18. The output of EQ3 is stored in a predetermined area of the data register 103. As shown in FIG. 10, step 18
Then, the clock φ2 becomes 1. This is step 18 ~
This is because, in step 35, the processing of steps 0 to 17 is performed on the input 2 which is the second input signal. Similarly, input 3 is processed in steps 36 to 53, and steps 54 to 54 are executed.
At 72, input 4 is processed. The result of each process is input to the next effect unit 702 via the data register 103.

According to the second embodiment, since the equalizer processing and the effect addition processing are alternately performed according to the clocks φ1 and φ1 bars, the timing of the calculation result is taken into consideration in the microprogram for performing the effect addition processing. No need.

In the above first and second embodiments,
Although the series of processing is two, for example, three or more microprograms may be sequentially switched and executed in the first embodiment.

[0150]

As described above, according to the present invention, a plurality of microprograms can be sequentially executed according to the speed of the arithmetic unit, so that the microprograms can be described separately, and Since it is not necessary to consider the delay until the arithmetic unit outputs the arithmetic result, the microprogram can be easily developed. In addition, the microprogram can be easily read, mistakes can be prevented, and the arithmetic unit can be used efficiently. Since each microprogram can use the operation result corresponding to the microinstruction in one step in the next step, the microprogram can be easily read and the debugging time can be shortened.

Furthermore, since the microprograms can be separated, it is easy to exchange the programs and switch the connections, and it is not necessary to prepare many microprograms in the ROM, which has the advantage of saving the storage capacity.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a digital signal processing device (DSP) according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of an electronic musical instrument using the DSP of FIG.

FIG. 3 is a diagram showing a configuration example of a microprogram or the like.

FIG. 4 is a block configuration diagram of an effect adding device realized by the DSP of FIG.

FIG. 5 is a time chart diagram showing input / output timings of a clock and a selector.

FIG. 6 is a block diagram of the DSP of the second embodiment of the present invention.

7 is a block configuration diagram of an effect addition device realized by the DSP of FIG.

8 is a block diagram of one equalizer realized by the DSP of FIG.

FIG. 9 is a detailed circuit diagram of a timing signal generator.

FIG. 10 is a time chart diagram showing the states of signals of various parts in the second embodiment.

[Explanation of symbols]

101 ... Input register, 102, 103 ... Data register, 104, 105 ... Coefficient register, 106-112 ...
Selector, 113 ... Multiplier, 114 ... Delay circuit, 115
... Adder, 116, 117 ... Micro program register, 118 ... Latch, 119 ... External delay RAM, 120
... address control, 121, 122 ... address register, 125 ... clock generator.

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G10H 1/02 G06F 9/22-9/28 G10K 15/12

Claims (6)

(57) [Claims] 1. A microprogram storage means for storing a plurality of microprograms each including a plurality of steps of microinstructions to be executed at each sampling cycle, a plurality of data storage means and a plurality of coefficient storage means, and the microprogram storage means. To read means for sequentially reading the microinstructions of each of the plurality of microprograms at each sampling cycle, and a microphone for each sampling cycle by the reading means.
(B) In synchronization with the reading of the instruction, the read micro instruction
Data storage means and coefficient storage means
Data and coefficient to be read respectively
Switching means , and according to the read micro instruction ,
Data storage hands switched in synchronization with the reading of instructions
Data read from the stage and coefficient storage means
The number is used to perform digital signal processing in a pipeline manner and to obtain the result of the digital signal processing.
A signal processing unit for storing the data in a predetermined data storage unit, and the reading unit includes a plurality of units from the execution of the microinstruction to the corresponding operation result obtained in the signal processing unit that performs the operation by the pipeline method. Each of the plurality of microprograms is read for one step in each of the step periods, and by repeating this, the plurality of microprograms are read in parallel in a time-division manner at each sampling cycle, and In each of the plurality of microprograms, the processing result of the microinstruction in any one step of the microprogram is available in the microinstruction in the next step of the microprogram, the digital signal processing device. . 2. The digital signal processing device according to claim 1, wherein each of the micro programs stored in the micro program storage means is an effect addition program or an effect addition program .
And are those having a connection program, the urging each effect
The additional programs are independent for each input music signal.
A professional who performs the process of adding and outputting one standing effect.
Gram, the connection program, the addition of each effect
Program that defines the input / output relationship of music signals between programs
A digital signal processing device characterized by being a ram . 3. The digital signal processing apparatus according to claim 2, further comprising means for changing only the connection program without changing the effect addition program of each of the plurality of micro programs in the micro program storage means. A digital signal processing device characterized by the above. 4. A program supply means for sequentially outputting the microinstructions of each step of a plurality of types of programs each composed of a plurality of steps of microinstructions, a plurality of data storage means and a plurality of coefficient storage means, and the program supply. Means of the above-mentioned plural kinds of programs
Same as which program of which micro instruction is output.
Data corresponding to the read micro-instruction
Data and coefficients are stored in the storage means and coefficient storage means.
Switching means for switching so that each is read, and the microinstruction output from the program supply means
Therefore, and in synchronization with the output of the microinstruction,
Read from the replaced data storage means and coefficient storage means
Using the output data and the coefficient , the digital operation is performed by the pipeline method according to the programs of the plurality of types , and the result of the digital operation is stored in a predetermined data.
And a single calculating means to be stored in the data storage unit, said program supplying means, said plurality of microprogram across step period until the corresponding operation result from the execution of the microinstruction is obtained in said calculating means digital signal processor which is characterized in that outputs a microinstruction of each of the one step. 5. The digital signal processing apparatus according to claim 4, each microprogram output from said program supplying means, which respectively, with the effect additional programs and connection flop <br/> Rogura arm , Each effect addition program
One is independent for each input music signal.
This is a program that adds the effect of
The connection program is the effect addition program
A digital signal processing device, which is a program for defining an input / output relationship of music signals between the digital signals. 6. The digital signal processing device according to claim 5, further comprising means for changing only the wiring program without changing the effect addition program of each of the plurality of microprograms in the program supply means. A digital signal processing device characterized by: