JP3470561B2 - Asynchronous signal input device and sampling frequency conversion device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous signal input device for reliably receiving input signals of various rates and a sampling frequency conversion device for converting an input signal into a predetermined sampling frequency.

[0002]

2. Description of the Related Art Conventionally, as a sampling frequency conversion device for receiving an asynchronous input signal and converting it into a signal of a predetermined sampling frequency, a data write command PU
A FIFO that sequentially writes data each time SH is supplied, and reads from the previously stored data each time a POP that is a data read command is supplied.
Those using O are known. FIG. 5 shows a conventional FI.
It is a block diagram which shows the structure of the sampling frequency converter which uses FO.

In FIG. 5, when storing data, first, data is supplied to the input In of the FIFO 1 and PUSH is supplied. In W counter 2, FI
A write address for FO1 is generated, and the write address is supplied to the write address input of FIFO1. On the other hand, the PUSH is supplied to the FIFO1 as the write enable signal WE. As a result, F
In the IFO1, the input data is stored in the write address. PUSH at this time is, for example, 44.1k.
Performed at a sampling frequency of Hz.

On the other hand, when reading data, the POP
To supply. The R counter 3 generates a read address for the FIFO 1, and the read address is F
It is supplied to the read address input of IFO1. on the other hand,
The POP is a FIFO as a read enable RE.
1 is supplied. As a result, the FIFO1 outputs the data stored at the read address. The POP at this time is performed at a sampling frequency of 48 kHz, for example.

The state monitoring unit 4 also includes a W counter 2 and an R counter.
The counter value (address) of the counter 3 is monitored to prevent the read address from overtaking the write address.
AND circuit 5 holds the read address.
A control signal is sent to the POP to control whether the POP is valid or invalid. When the POP is ineffective, the read enable RE is given to the FIFO1 while the value of the R counter is held, so that the same data as the previous time is repeatedly read. Although the configuration of FIG. 5 is configured to hold the read address and repeatedly read the same data in order to increase the sampling frequency,
Conversely, when lowering the sampling frequency, FIFO1
It is necessary to make a configuration in which the data stored in is skipped and read.

FIG. 6 is a block diagram showing the configuration of the sampling frequency conversion circuit described in Japanese Utility Model Laid-Open No. 6-54323. The circuit shown in the figure shows data Dou having a sampling frequency different from that of the input data Din.
It is a sampling frequency conversion circuit for converting to t. In the sampling frequency conversion circuit, the linear interpolation unit 8
Externally input master clock CKM and clock CKout
Based on the above, the data Din is linearly interpolated using the time difference information between the sampling point of the data Din and the sampling point of the data Dout. Note that this example is shown as a reference as a method of converting the sampling frequency without using the FIFO.

[0007]

By the way, in the above-described conventional sampling frequency conversion apparatus using the FIFO, the sampling frequency is slightly different between the input and output, so that the FIFO 1 becomes empty during a long-time operation. It becomes full or full. Therefore, in the state monitoring unit 4, by controlling the read address, the same data is continuously output (hold), or one data is skipped. Here, FIG. 7 is a conceptual diagram showing a waveform of an input / output signal (data) by the conventional sampling frequency conversion device. As shown in the figure, the conventional sampling frequency conversion device using the FIFO has a problem that the output signal (dotted line) is distorted (noise is generated) with respect to the input signal (solid line) due to the influence of data hold or data skipping. .

The present invention has been made in view of the above-mentioned circumstances, and it is possible to prevent an occurrence of noise and an asynchronous signal input device which automatically operates according to a sampling frequency of input data and can reliably receive an asynchronous input signal. An object is to provide a sampling frequency conversion device.

[0009]

In order to solve the above-mentioned problems, according to the invention of claim 1, the data inputted at a predetermined cycle is written by a predetermined write signal and at the same time by a predetermined read signal. Storage means for reading data, data amount measuring means for measuring the data amount of the storage means, and read signal generating means for generating the read signal at a cycle corresponding to the data amount measured by the data amount measuring means. It is characterized by including.

According to a second aspect of the present invention, in the asynchronous signal input device according to the first aspect, there is provided conversion means for giving a non-linear gain to the data amount measured by the data amount measuring means, and the read signal generation The means is characterized in that the read signal is generated at a cycle corresponding to the amount of data given the non-linear gain by the converting means.

[0011] According to a third aspect of the invention, the asynchronous signal input device according to claim 1 or 2, wherein the data amount measuring means, and the counting up at a predetermined write signal to the storage means, of the predetermined It is characterized in that the amount of data in the storage means is measured by counting down with a read signal.

Further, in order to solve the above-mentioned problems,
According to a fourth aspect of the present invention, a storage unit, a write control unit that writes input data having a first sampling frequency to the storage unit by a write signal having the first sampling frequency, and a data amount of the storage unit is measured. The same as the data amount measuring means and the clock of the second sampling frequency.
A means for generating a read signal synchronized on the basis of the data amount measured by the data amount measuring means, and the read signal generating means for controlling the generation of said read <br/> heading signal,
Each time the clock of the second sampling frequency is generated
Is a means for changing the interpolation information, and
The amount of data measured by the data amount measuring means
An interpolation information generating means for controlling, based on the read
By the read signal generated by the signal generating means
Read control means for reading data from the storage means,
Generation timing of the clock of the second sampling frequency
Data corresponding to the
Generated by the read data and the interpolation information generating means.
And an interpolating unit for performing an interpolating operation using the generated interpolating information .

According to a fifth aspect of the present invention, in the sampling frequency changing device according to the fourth aspect, the reading is performed.
And a signal generating means for generating a clock of the second sampling frequency.
Each time a lock occurs, the data amount measuring means
Cumulative addition of values corresponding to the measured data amount
Sum is characterized and this <br/> for generating a read signal for each reaches a predetermined value.

According to the present invention, when the data is written into the storage means at a predetermined write cycle and the data is read at the predetermined read cycle, the data amount measuring means measures the data amount of the storage means, Since the read signal generation means generates the predetermined read signal for the storage means at a cycle according to the data amount, it automatically operates according to the sampling frequency of the input data to prevent noise generation. Is possible.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a sampling frequency conversion device for receiving an asynchronous input signal and converting it to a predetermined sampling frequency according to an embodiment of the present invention. In the figure, a FIFO 20 is composed of a dual port RAM (random access memory), stores input data Din according to a write address and a write enable signal supplied from a write control unit 21 described later, and reads it described later. The stored data is output to the interpolation unit 30 according to the read address and the read enable signal supplied from the control unit 22.

The write controller 21 generates a write address and a write enable signal according to the write timing CKin (44.1 kHz) to the FIFO 20, and supplies the write address and the write enable signal to the FIFO 20. The read control unit 22 also generates a read address and a read enable signal according to the read timing CO supplied from the full adder 28 described later, and supplies the read address and the read enable signal to the FIFO 20.

The counter 23 monitors the storage state of the FIFO, and increases the counter value at the write timing CKin and decreases the counter value at the read timing CO so that the current data amount ΔS in the FIFO 20 is reached. Indicates. The conversion unit 24 includes a counter 23.
The current data amount ΔS, which is the counter value of, is subjected to non-linear conversion to output data Gain (ΔS), and the converted data Gain (ΔS) is supplied to the full adder 26. Here, FIG. 3 is a table showing the conversion characteristics of the conversion unit 24. The full adder 26 uses the data Gain
(ΔS) is added to the output of the selection circuit 25, which will be described later. When the value supplied from the selection circuit 25 is y (n), y (n + 1) = y (n) + Gain (ΔS) Is added and y (n + 1) is output

In the selection circuit 25, the full adder 26 is provided with the above y.
(N) is given, and the initial value y is set at the start of the operation.
(0) and thereafter, the output y (n) of the latch circuit 27 is selected. Here, the initial value y (0) is 44.1 kHz is 4
Convert to 8 kHz, in this embodiment y (0) = 4
It is set to 096 × (44.1 / 48). In addition,
This initial value is given to shorten the time until the operation stabilizes, and is not essential. The full adder 26 is
Y (n + 1) is given to the latch circuit 27 according to the above-mentioned formula. The latch circuit 27 latches the addition result of the full adder 26 in synchronization with the externally input clock CKout (48 kHz), supplies it to the selection circuit 25 (feedback), and supplies it to the full adder 28.

The full adder 28 adds the value supplied from the latch circuit 27 and the value supplied (feedback) from the latch circuit 29, which will be described later, and supplies the addition result to the latch circuit 29 as well as the carrier. The read timing CO is supplied to the read control unit 22 and the counter 23 described above. The latch circuit 29 latches the addition result in synchronization with the externally input clock CKout (48 kHz), supplies it to the full adder 28, and supplies it as an interpolation ratio to an interpolation unit 30 described later.

The FIFO 20 to the latch circuit 29 described above constitute the asynchronous signal input device of the present invention. The sampling frequency conversion device of the present invention including the interpolation unit 30 will be described later.

The operation of the embodiment as the asynchronous signal input device will now be described. FIG. 2 is a timing chart for explaining the operation. Overall, this asynchronous signal input device has a clock C of 44.1 kHz.
Data Din input to the FIFO 20 based on Kin
In contrast, the clock CKout of 48 kHz is used for synchronization. That is, the read control unit 2
As the read-out timing CO given to 2, the pulse which is obtained by skipping the pulse of the clock CKout of 48 kHz is created as shown in FIG. By creating the read timing CO synchronized with such input data and supplying it to the FIFO 20, the input data can be reliably captured.

A full adder 28 and a latch circuit 29 which generate this read-out timing CO as a carry-out.
The accumulating section consisting of 12 bits is composed of 12 bits. For example, if a value of 2 ^ 12 (← 2 to the 12th power) = 4096 is given, a carry-out CO is generated at every 48 kHz timing. To do. That is, when the value 4096 is given from the latch circuit 27 at the previous stage, the clock CKout of 48 kHz is supplied to the read control unit 22 as it is. On the other hand, a value smaller than 4096, for example, the initial value 4096 × (44.
If 1/48) is given, carry-out CO does not occur at every 48 kHz timing. That is, CO is generated as shown in FIG. 2 with a pulse skipped at a 48 kHz clock CKout.

The counter 23 to create a numerical value for determining the carry-out occurrence timing of the full adder 28.
This is a portion configured by the latch circuit 27. Converter 24
Is based on the data amount ΔS of the FIFO 20 indicated by the counter 23, and the data Gain (ΔS) is such that the data amount ΔS always maintains an appropriate amount (two in this embodiment).
To occur. That is, when ΔS is small, the conversion unit 2
Since a small value (negative value) is output by 4, the operation is performed so as to reduce the occurrence of the read timing CO, and conversely, when ΔS is large, a large value (positive value) is generated by the conversion unit 24. ) Is output, the operation is performed so that the read timing CO is frequently generated. Also, ΔS
Is a proper amount (two), the value output from the conversion unit 24 is “0”. As described above, the relationship between ΔS and Gain (ΔS) follows the table of FIG. 3, but the non-linear relationship is that the larger the deviation from the target value, the larger the correction amount and the target value. This is because the correction amount is reduced and the stable operation is performed if the target value is locked. The output H of the conversion unit 24 is added to the output of the selection circuit 25 in the full adder 26. That is, the output of the full adder 26 is the initial value 4096 × (44.1 /) output from the selection circuit 25.
48) as a start, the FIFO indicated by the counter 23
It will increase or decrease according to the data amount ΔS of 20.
The output of the full adder 26 is the clock CKout (48k
It is latched by the latch circuit 27 based on (Hz).

As a result of the above operation, as described above, as a whole, the asynchronous signal input device uses the clock CKout of 48 kHz for the data Din input to the FIFO 20 based on the clock CKin of 44.1 kHz. And synchronize to work.

Next, the FIFO 20 to the latch circuit 29
A sampling frequency conversion device in which the asynchronous signal input device configured by and the interpolation unit 30 are combined will be described. As described above, the data supplied from the FIFO 20 is output according to a pulse obtained by skipping the pulse of the clock CKout (48 kHz) in some places, but the output is converted into a signal having an accurate sampling frequency of 48 kHz and output as Dout. It is the interpolation unit 30 that does this.

Before describing the details of the interpolation section 30, the principle of interpolation will be described with reference to FIG. In calculating the value of the interpolation point indicated by the mark x from the input sample place indicated by the mark o, it can be calculated in either linear interpolation or higher-order interpolation if Δt, T and the input sample value D are known. For example, in linear interpolation, {D (t + 1) -D
It is obtained by calculating (t)} × (Δt / T) + D (t).

Returning to FIG. 1, the input sample value D is supplied from the FIFO 20, and the information corresponding to Δt is supplied from the latch circuit 29. 4 for T
It is a fixed value of 096, and the interpolation unit 30 uses the above information to perform D according to the above linear interpolation formula or higher-order interpolation formula.
Calculate out.

By the way, as described above, the read timing CO generated from the full adder 28 is the clock CKou.
Since the pulse is extracted in some places with respect to t (48 kHz), the data output from the FIFO 20 is not generated at all timings of 48 kHz. On the other hand, the information Δt regarding interpolation is CKout (48
It is updated at all timings (kHz). This has an important effect on good interpolation. This will be described with reference to FIG.

In the figure, D (A1), D (A2), ... Is 4
FIFO20 according to the clock CKin of 4.1 kHz
The input data written in the addresses A1, A2, ... The data stored in the FIFO 20 is read according to the value (indicated by the R address pointer in FIG. 2) obtained by counting the read timing CO by the read control unit 22. Also, information about interpolation Δt
Is output from the latch 29 at the timing of the clock CKout (48 kHz) (indicated by L2 output in FIG. 2). That is, at the timing when CO occurs, the updated data D and the updated interpolation information Δt
Is calculated based on the previous data D and the updated interpolation information Δt at the timing of generation of the clock CKout at which CO is not generated. A proper interpolation process is performed.

The address control of the FIFO 20 and the creation of the interpolation information Δt necessary for performing such interpolation are not specially required only for the interpolation processing, and are composed of the FIFO 20 and the latch circuit 29. This is a necessary structure as an asynchronous signal input device. Therefore, it can be said that the asynchronous signal input device of the present invention is particularly suitable for application to the sampling frequency conversion device.

[0032]

As described above, according to the present invention, when the data is written into the storage means at a predetermined write cycle and the data is read at a predetermined read cycle, the data amount measuring means allows The data amount of the storage means is measured, and the read signal generation means generates the predetermined read signal for the storage means in a cycle according to the data amount. Therefore, the read signal generation means automatically responds to the sampling frequency of the input data. The advantage is that it can be operated and noise generation can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of this embodiment.

[FIG. 3] FIFO data amount ΔS and gain Gain (Δ
It is a conceptual diagram which shows the correspondence with S).

FIG. 4 is a conceptual diagram for explaining an operation in an interpolation unit.

FIG. 5 is a block diagram showing a configuration of a sampling frequency conversion device using a conventional FIFO.

FIG. 6 is a block diagram showing a configuration of a conventional sampling frequency conversion device that does not use a FIFO.

FIG. 7 is a conceptual diagram showing waveforms of input / output signals (data) of a sampling frequency conversion device using a conventional FIFO.

[Explanation of symbols]

20 FIFO (storage means) 21 Write control section 22 Read control section 23 Counter (data amount measuring means) 24 Converting section (converting means) 25 Selection circuit 26 Full adder (reading signal generating means) 27 Latch circuit (reading signal generating means) ) 28 full adder (readout signal generation means, interpolation ratio generation means) 29 latch circuit (interpolation ratio generation means) 30 interpolation unit (interpolation means)

Continuation of the front page (56) Reference JP-A-5-235698 (JP, A) JP-A-5-259812 (JP, A) JP-A-6-268477 (JP, A) JP-A-7-212190 (JP , A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03H 17/00-17/08 H04B 14/00-14/08

Claims (5)

(57) [Claims] 1. A storage unit for writing data input at a predetermined cycle with a predetermined write signal and reading the data with a predetermined read signal; and a data amount measuring unit for measuring the data amount of the storage unit. An asynchronous signal input device, comprising: a read signal generating unit that generates the read signal at a cycle corresponding to the data amount measured by the data amount measuring unit. 2. A conversion unit for applying a non-linear gain to the data amount measured by the data amount measuring unit, wherein the read signal generation unit has a cycle corresponding to the data amount given the non-linear gain by the conversion unit. 2. The asynchronous signal input device according to claim 1, wherein the read signal is generated by. Wherein the data amount measuring means, and the counting up at a predetermined write signal to the storage means,
3. The asynchronous signal input device according to claim 1, wherein the amount of data in the storage unit is measured by counting down with the predetermined read signal. 4. Storage means for storing input data of a first sampling frequency in the first sample
Write to the storage means by a pulling frequency write signal.
Write-in control means, data amount measuring means for measuring the data amount of the storage means, and reading in synchronization with the clock of the second sampling frequency
A means for generating and signal on the basis of the data amount measured by the data amount measuring means, and the read signal generating means for controlling the <br/> generation of the read signal, a clock of said second sampling frequency Every time it occurs
Is a means for changing the interpolation information, and
The amount of data measured by the data amount measuring means
An interpolation information generating means for controlling on the basis of the read generated by the reading signal generating means
Read out to read data from the storage means by a signal
Control means and timing for generating a clock of the second sampling frequency
Data corresponding to the
Generated by the read data and the interpolation information generating means.
A sampling frequency conversion device, comprising: an interpolating unit that obtains by an interpolation calculation using the generated interpolation information . 5. The read signal generating means comprises the second
Each time a clock with a sampling frequency of
Corresponding to the amount of data measured by the data amount measuring means
Value is cumulatively added, and each time the cumulative addition value reaches a predetermined value,
The sampling frequency conversion device according to claim 4, wherein a read signal is generated .