JP3465362B2 - Data processing device having cache memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for software prefetching a computer having a cache memory, and more particularly to a data processing device which efficiently uses two types of cache memories.

[0002]

2. Description of the Related Art A computer having a cache memory stores frequently used data in a small-capacity, high-speed cache memory among data stored in a large-capacity, low-speed main memory, and an instruction unit such as a CPU. Generally performs high-speed data access with the cache memory and accesses the main memory only when there is no data in the cache memory.

However, since the machine cycle of the CPU is drastically shortened as compared with the memory, the penalty at the time of a cache miss (the time until the requested data is acquired from the main memory) is increasing.

A method called software prefetch for solving this problem is described in "Softw" of David Callahan et al.
are Prefetching ”Fourth International Conference o
nArchitectual Support for Programming Languages an
d Operating Systems, 1991, p.40-52. According to the first conventional technique, the prefetch instruction performs address calculation before the instruction unit needs the data, detects whether or not the data indicated by the address exists in the cache memory, and if the data does not exist in the cache memory, the main operation is performed. Transfer from memory to cache memory. By doing so, when the data is needed, the data is stored in the cache memory in advance by the prefetch instruction, so that the hit rate of the cache memory can be improved and the penalty can be minimized.

Further, the cache memory has two different uses.
Japanese Patent Application Laid-Open No. 4-303248 discloses a buffer which is composed of three buffers and which is selectively used depending on the hardware.

According to the second conventional technique, the cache memory stores the data which is frequently accessed in time and the data which is referred to in the future by the program in the vicinity of the address currently referred to by the program. , And a P buffer for storing the P buffer, and the P buffer and the S buffer are selectively used depending on the addressing method and the register used for the address calculation.

[0007]

According to the first prior art, in order to process a transfer from a main memory to a cache memory and a memory reference instruction from an instruction unit at the same time,
The first problem is that an expensive 2-port cache memory must be used. Of course, if the simultaneous processing is not performed, a commonly used 1-port cache memory may be used, but this requires a long processing time and the characteristics of software prefetch cannot be utilized.

Further, if the data that is read out from the cache memory only once and is immediately evicted from the cache is held in the cache memory, the pollution of the cache memory becomes large and the hit rate decreases. There is a problem.

These problems are remarkable in a program that handles large-scale data that cannot fit in the cache memory.

According to the second conventional technique, which of the two cache memories is to receive data is determined by the addressing method and the register used for the address calculation.
There is a third problem that the two cache memories cannot be used properly in consideration of data characteristics such as data size.

An object of the present invention is to solve the above-mentioned problems and to process small data stored in a cache memory and frequently accessed and large-scale data that cannot be stored in the cache memory efficiently at high speed. An object of the present invention is to provide a data processing device that reduces the pollution of the cache memory and improves the hit rate.

[0012]

A feature of the present invention for achieving the above object is that a large-capacity 1-port first cache memory and a small-capacity 2-port are provided between a main memory and an instruction processing unit. A second cache memory, and stores frequently accessed data in the first cache memory;
The data having a low access frequency is a control unit controlled by a prefetch instruction stored in the second cache memory, and is a control for controlling the first cache memory or the second cache memory to store the data. And a part.

[0013]

Since the frequently accessed data is stored in the first cache memory, the hit rate is improved. Also,
Since the data with low access frequency is not stored, the pollution of the first cache memory can be reduced.

Since data having a low access frequency is stored in the second cache memory, it can be deleted from the second cache memory after the data is processed. That is, although the capacity of the second cache memory is small, since the data to be accessed at all times is stored, the hit rate can be increased.

Since the second cache memory has two ports, by simultaneously processing the data transfer from the main memory and the memory reference instruction from the instruction unit for large-scale data with low access frequency, Highly efficient processing is possible.

Furthermore, the function of simultaneous processing of data transfer from the main memory and memory reference instruction from the instruction unit is:
Since only the small capacity second cache memory needs to be provided, the amount of hardware can be small and the cost can be reduced.

[0017]

FIG. 34 is a schematic diagram of the present invention.

The computer of the present invention comprises an instruction unit 201,
It is composed of a memory unit 202 and a main memory 203.

The instruction unit 201 is, for example, a CPU or the like that performs calculation and control.

The memory unit 202 comprises a first cache memory 101, a second cache memory 100 and a control unit 1600.

The main memory 203 is a storage device for storing instructions and data.

The instruction unit 201 is a unit for processing instructions, requests the memory unit 202 to read and write data, and exchanges addresses and data via the bus 3402. Further, when the prefetch instruction is processed, the control signal line 3404 receives information indicating whether the data transferred from the main memory 203 to the memory unit 202 is written in the first cache memory 101 or the second cache memory 100. To the control unit 1600 via.

The control unit 1600 is the command unit 2
When the data of the address that 01 has requested to read or write exists in either the first cache memory 101 or the second cache memory 100, the corresponding cache memory is read or written.
When the data at the address requested by the instruction unit 201 does not exist in either the first cache memory 101 or the second cache memory 100, the main memory 203 is requested to read or write the data via the bus 3406. , Exchange addresses and data. When the prefetch instruction request is received from the instruction unit 201, the main memory 203 is requested to read the data, and the data transferred from the main memory 203 is transferred to the first cache according to the information received through the control signal line 3404. Write to either the memory 101 or the second cache memory 100.

The main memory 203 is a memory unit 202.
The data is read or written according to the request.

FIG. 1 is a block diagram of the present invention.

The memory unit 202 includes a first cache memory 101, a second cache memory 100, and selectors 104, 16 for inputting / outputting data to / from these.
It is composed of a control unit consisting of 05 and control unit 1600.

The instruction unit 201 is, for example, a CPU or the like that performs calculation and control.

The memory unit 202 includes a first cache memory 101, a second cache memory 100, and selectors 104 and 16 for inputting / outputting data to / from these.
It is composed of a control unit consisting of 05 and control unit 1600.

The main memory 203 is a storage device for storing instructions and data.

The first cache memory 101 is a one-port cache memory having a larger capacity than the second cache memory 100.

The second cache memory 100 is a cache memory having a smaller capacity and two ports than the first cache memory.

The instruction unit 201 is a unit for processing instructions, and is a first unit through the buses 210, 211 and 212.
Data is exchanged with the cache memory 101 and the second cache memory 100. That is, the address bus 210 and the write data bus 21 having a 4-byte width
1, to send address, data and control signals to the memory unit 202 and the main memory 203 via the control signal line 213.

The memory unit 202 has a 4-byte width read data bus 212 and a wait signal line 214,
The data and the wait signal are sent to the instruction unit 201, and the request signal is sent to the main memory 203 via the request signal line 218.

The main memory 203 transfers data to the first cache memory 101 and the second cache memory 100 via the buses 215 and 216. That is, the main memory 2
03 is a transfer data bus 215, a transfer address bus 21
6. Send data, address and response signal to the memory unit 202 via the response signal line 217.

FIG. 12 is a diagram for explaining an example of the format of the operation code of the instruction processed by the instruction unit 201 of FIG. OP is an opcode, A and B are fields for instructing a source register, C is a field for instructing a target register, and d is a field for indicating immediate data.

FIG. 13 is a diagram showing the types of instructions processed by the instruction unit 201 of FIG. For simplicity, the number of instructions is limited to 10 in this embodiment, but this does not limit the application of the present invention. The present invention can be applied to a computer having a few tens to a hundred or more instructions like a normal processor.

The AND, OR, ADD, and SUB instructions carry out operations corresponding to the source registers A and B and store them in the target register C.

The NOT instruction stores the bit inversion of source register A in target register C.

The branch instruction BRA is a program counter P.
Immediate d is added to C and stored in the program counter PC.

The load instruction LD is the contents of register A and B.
The read data is stored in the register C by adding the contents of the above to the address.

The store instruction ST changes the contents of the register B to
The contents of register A are written as an address.

Next, the prefetch instruction will be described.

The prefetch instruction PF1 checks whether or not there is corresponding data in the first cache memory 101 and the second cache memory 100 by using an address obtained by adding the contents of the register A and the contents of B, When there is not, the first cache memory 1 from the main memory 203
The data is transferred to 01.

The prefetch instruction PF2 has almost the same function as that of PF1 except that the transferred data is written in the second cache memory 100.

As will be described later in detail, the first cache memory 101 is a direct map type cache memory having a capacity of 1 Mbytes and a block size of 16 bytes.

The direct map system is a system in which a memory location is uniquely determined by a memory address.

The second cache memory 100 is a full-associative cache memory having a block size of 4 bytes and 64 entries.

The full associative method is a method of storing data at an arbitrary address in the memory in an arbitrary storage location on the cache.

The PF1 instruction is used when prefetching data that may be reused, and the PF2 instruction is used when prefetching data that has no or little reuse possibility.

The determination of reusability is made by the compiler when the object code is generated. For example, when accessing a large amount of data that cannot fit in the cache, it is judged that there is no possibility of reuse even if it is stored in the cache, and the PF
Two instructions are used.

The first cache memory 101 has a capacity of 1M.
Although it has a byte and a larger capacity than the second cache memory 100, since it is one port, it is not so large as a whole and operates at high speed.

The second cache memory 100 is of the fully associative type, and since the memory reference instruction from the instruction unit 1 and the data transfer from the main memory 203 are processed in parallel, the cell structure is complicated. Since the number of entries is as small as 64, the overall size is small and the speed can be increased.

The second cache memory 100 is transferred from the main memory 203 by the PF2 instruction but is not used by the LD instruction because it is used by the PF2 instruction to store data that is not reused. Since the data is only temporarily stored, the hit rate is high and the performance can be improved even if the capacity is small.

When the load instruction is executed, the instruction unit 20
1 indicates the address of the data to be loaded on the address bus 2
Then, the control signal 213 indicates that the instruction is a load instruction. If there is corresponding data in the cache memory in the memory unit 202, the memory unit 202 loads the data on the read data bus 212. If it does not exist, the wait signal 214 is sent to the instruction unit 201, and the request signal 218 for requesting the transfer of the data to the main memory 203 is set to "1". Main memory 2 when receiving it
03 reads the data and transfers it to the transfer data bus 215.
Then, the response signal 217 is returned to the memory unit 202. The memory unit 202 sends the data to the instruction unit 201 through the read data bus 212 while writing the data in the internal cache, and sets the wait signal 214 to "0".

When executing a store instruction, the instruction unit 20
1, the write address is placed on the address bus 210 and the data to be written is placed on the write data bus 211.
Send to 4. For simplicity, in this embodiment, writing is
Both the cache 100 or 101 and the main memory 203 are performed (write-through method). Further, at the time of writing, even if the cache misses, data transfer from the main memory 203 to the cache is not performed. When writing to the data space, the memory unit 202 writes the data sent from the write data 211 to the cache if the cache hits, and the main memory 203 also writes the same data to the main memory.

Reference numeral 301 is an instruction cache, 320 is an arithmetic unit, and 302 is a memory interface. The instruction cache 301 sends the instruction as a signal 307 to the arithmetic unit 320 and the memory interface 302. The memory interface 302 includes instructions LD, ST, PF1,
When the PF2 is executed, the control signal 213 is transmitted and the signal 21
Receive 4 When the wait signal 214 becomes "1", the signal 308 is sent to the arithmetic unit 320, and the pipeline is stopped until the wait signal 214 becomes "0".
Reference numeral 1600 is a control unit, and 1605 and 104 are selectors. The control unit 1600 includes a memory interface 302, a main memory 203 and control signals 213, 214,
217 and 218 are exchanged, and the selector 1605 and the second
Cache memory 100, first cache memory 1
01 is controlled by signals 111, 113, 122-125. The selector 104 includes the second cache memory 10
The correct data is selected from the data bus 110 of 0 and the data bus 112 of the first cache memory 101 and sent to the instruction unit 201 as a signal 212. Since the first cache memory 101 has one port, access from the main memory 203 and instruction unit 2
The access from 01 can be processed only sequentially. The control unit 1600 uses the selector 1605 to determine which accesses the first cache memory 101.

FIG. 3 is a structural example of the instruction unit 201 of FIG. 301 is an instruction cache, 303 is a decoder, 302 is a memory interface, 305 is a register, 306 is an ALU, and 304 is an address adder. The instruction cache stores the instructions on the bus 30 via the decoder 30.
3 and the memory interface 302. The decoder 303 decodes the received instruction and controls the register 305, the ALU 306, and the address adder 304 with the signal 330. ALU306 uses register 3
Receive the data through 12,313, perform the calculation,
The result is written to register 305 via bus 314.
Address adder 304 uses bus 31 from register 305.
Data is read through 0, 311 and added to load or store the result, or the bus 210 is used as an address to be stored.
Send to. At the time of storing, the data to be stored is read from the register 305 and sent to the bus 211. At the time of loading, the read data is received through the bus 212 and written in the register 305.

The memory interface 302 uses the instruction L.
When executing D, ST, PF1, and PF2, the control signal 213
To receive signal 214. When the wait signal 214 becomes “1”, the signal 308 is sent to the decoder 303.
And the pipeline is stopped until the wait signal 214 becomes "0".

FIG. 4 is a diagram for explaining the pipeline processing. IF is an instruction read stage, D is a decode stage, E is an operation and address addition stage, A
Is a cache access stage, and W is a register write stage. When the load instruction is executed, the cache is accessed at the A stage and the data read at the W stage is written in the register 305. When the store instruction is executed, the cache is checked at the A stage, and if there is a hit, the cache is written at the A stage. Figure 2
Is an example of the configuration of the memory unit 202 in FIG. 1. 10
1 is a first direct-mapped cache memory having a capacity of 1 Mbyte and a block size of 16 bytes, 100
Is a second cache memory of block size 4 bytes, capacity 256 bytes, full associative method, 102
Is a 4-entry prefetch queue, 103 is a control circuit, and 104 and 105 are selectors.

The first cache memory 101 has an address 130, a transfer data bus 215, and a selector control signal 1
23, write signal 122, write data 211 as input, read data 112, hit signal 11
3 is output. The second cache memory 100 has an address 210, a transfer address 216, transfer data 215, and
Receives registration signal 124, write signal 125, write data 211, read data 110, hit signal 1
11 is sent out. The prefetch queue 102 receives the cache selection signal 213-1, the transfer address 216, the address 210, the set signal 120, and the reset signal 121, and outputs a full signal 114, a hit signal 115, and a cache selection signal 116.

The control circuit 103 outputs a control signal 213-2 from the instruction unit 201, a full signal 114, a hit signal 115 and a cache selection signal 116 from the prefetch queue 102, and a response signal 217 from the main memory 203.
The hit signal 111 from the second cache memory 100,
The hit signal 113 is received from the first cache memory 101, and the wait signal 214 is sent to the instruction unit 201.
, A set signal 120 and a reset signal 121 to the prefetch queue 102, and a transfer request signal 2 to the main memory 203.
18 to the second cache memory 100 with a registration signal 12
4, write signal 125, first cache memory 101
The write signal 122 and the selector control signal 123 are sent to the selector 105, and the selector control signal 123 is sent to the selector 105.

The selector 104 is the second cache memory 1
00, data 110, hit signal 111, first cache memory 101 data 112, hit signal 113
When the hit signal 111 is asserted, the data 110 is read, and when the hit signal 113 is asserted, the data 112 is read as an output and is output to the data bus 212. Further, the selector 105 outputs the selector control signal 123.
Either the address 210 or the transfer address 216 is selected under the control of 1 and is sent to the first cache memory 101 as the output 130.

When the write signal 122 indicates a read operation, the first cache memory 101 reads the cache memory with the contents of the address 130 and sends the read data 112 and the hit signal 113. or,
When the write signal 122 is instructing to write,
When the selector control signal 123 is 1, the transfer data 21
When 5 is 0, the content of the write data 211 is written.

The second cache memory 100 checks the contents of the cache at the address 210 when the write signal 125 is negated and the reading is instructed.
The read data 110 and the hit signal 111 are transmitted. When the write signal 125 is asserted and a write is instructed, the cache is checked, and if there is a hit, the contents of the write data bus 211 are written.
In parallel with the above operation, when the registration signal 124 is asserted, the pair of the transfer address 216 and the transfer data 215 is registered.

The prefetch queue 102 is the main memory 2
This is a queue that can hold the address of the data being transferred from 03 up to 4 entries. When the set signal 120 is asserted, the address 210 and the set selection signal 2
The contents of 13-1 are registered in the queue, and the reset signal 12
When 1 is asserted, the cache selection signal 116 corresponding to the transfer address 216 is output and the entry is invalidated. Further, the address 210 is compared with the address held internally, and if the entry is being transferred from the main memory 203, the hit signal 115 is asserted. Further, while the valid address is held in all the entries, the full signal 114 indicating it is asserted. Finally, the operation of the control circuit 103 will be described. FIG. 14 shows a configuration example of the control circuit 103. The control circuit 103 decodes the control signal 213-2 to output LD, ST, PF1, PF.
The activation of each instruction of 2 is accepted. During execution of the LD instruction, when both the hit signal 111 from the second cache memory 100 and the hit signal 113 from the first cache memory 101 are negated, both caches have missed. In order to make the instruction unit 201 wait while transferring data, the wait signal 214 is asserted. Further, both the hit signal 111 from the second cache memory 100 and the hit signal 113 from the first cache memory 101 are negated during execution of the LD, PF1, and PF2 instructions, and the hit signal 115 from the prefetch queue 102 is also executed. Is also negated but the full signal 114 from the prefetch queue 102 is asserted, the prefetch queue 102 is full and the instruction cannot be queued.
The wait signal 214 is asserted in order to make 1 wait.

While the LD, PF1 or PF2 instruction is being executed, the full signal 114 from the prefetch queue 102 is negated, and the second cache memory 10
0 hit signal 111, first cache memory 10
When the hit signal 113 from 1 is also negated, the transfer request signal 218 to the main memory 203 is asserted, and at the same time, the set signal 120 to the prefetch queue 102 is asserted and registered in the prefetch queue 102.

On the other hand, the response signal 21 from the main memory 203
When 7 is asserted, the reset signal 121 to the prefetch queue 102 is asserted to reset the entry from the prefetch queue 102, and the cache select signal 116 is seen to register the transfer data in the cache. When instructing to write to the first cache memory 101, the write signal 122 to the first cache memory 101 is asserted, and when instructing to write to the second cache memory 100, to the second cache memory 100. Registration signal 124
Assert.

When the hit signal 113 from the first cache memory 101 is asserted during execution of the ST instruction, the write signal 122 to the first cache memory 101 is asserted to write the data to the first cache memory 101. To do. Similarly, when the ST instruction is executed, the hit signal 111 from the second cache memory 100 is sent.
Is written to write the data to the second cache memory 100, the second cache memory 1
The write signal 125 to 00 is asserted.

FIG. 5 shows an example of the structure of the prefetch queue 102 shown in FIG. Reference numeral 500 is a priority circuit, 501 is a determination circuit, and 502 to 505 are cells. Cell 502-
505 is a read address 212, a cache selection signal 213-1, a transfer address 216, and a reset signal 121.
In response, the valid signals 506, 509, 512, 515, the hit signals 507, 510, 513, 516, the selection signal 1
16 is sent out. Also, set signals 508, 511, 51
Receive 4,517.

The priority circuit 500 includes a cell 502.
From ~ 505, valid signals 506, 509, 512, 51
5 is received from the control circuit 103 and the set signals 508, 511, 514 and 517 are transmitted to the cell 502.
To 505.

The determination circuit 501 is provided with valid signals 506 and 50.
9,512,515 and hit signals 507,510,51
3,516 received from cells 502-505, full signal 11
4 and the hit signal 115 are sent to the control circuit 103.

Since each cell 502-505 has the same function,
The operation will be described only for the cell 502. The cell 502 internally has an address, a register holding a cache selection bit, and its valid bit. When the set signal 508 is asserted, the valid bit is asserted, and the contents of the transfer address 216 and the cache selection signal 213-
The contents of 1 are taken inside. The read address 212 is compared with the valid address held inside, and if they match, the corresponding cache selection bit held is sent to the signal 116. When the transfer address 216 matches the internally held address and the reset signal 121 is asserted, the valid bit is invalidated. When the set signal 120 is asserted, the priority circuit 500 looks at the valid signals 506, 509, 512, 515, selects one of the valid cells and asserts the corresponding set signal 508, 511, 514, 517. The order of priority is cells 502-505, and cells 502 are set in order.

The determination circuit 501 asserts the hit signal 115 if there is at least one cell in which both the valid signal and the hit signal are asserted. Also, valid signals 506, 50
When 9, 512 and 515 are all asserted, full signal 114 is asserted.

FIG. 6 is a structural example of the cell 502 of FIG. Reference numeral 601 is a register holding an invalid bit, 602 is a register holding an address, 603 is a register holding a cache selection bit, 604, 605 are comparators, 630 is a tri-state buffer, 631, 63.
2 is an AND gate. Valid bit 601 is set when set signal 508 is asserted and signal 6
It is reset when 08 is asserted. The set signal 508 is a valid bit 601, an address register 60.
2, the cache select bit 603 is connected, and when the set signal 508 is asserted, the valid bit 6
01 is set, the address register 602 fetches the read address 212, and the cache selection register 6
03 takes in the cache selection signal 213-1. The valid bit sends its output as a valid signal 506. The comparator 604 compares the read address 212 with the output 606 of the address register 602, and they match,
If the valid bit 601 is asserted, the hit signal 507 is asserted. The comparator 605 outputs the output 606 of the address register 602 and the transfer address 216.
Are compared, and if they match, the tri-state buffer 63
0 is opened and the contents of the cache selection bit register 603 are sent to the signal 116. Furthermore, when the reset signal 121 is asserted, the signal 608 is asserted and the valid bit 601 is reset. FIG. 7 shows FIG.
3 is a configuration example of the priority circuit 500 of FIG. 705-
Reference numeral 707 is an inverter, and 701 to 704 are AND gates. FIG. 8 is a configuration example of the determination circuit 501 of FIG. Reference numerals 801 to 804 and 806 are AND gates, and 805 is an OR gate. FIG. 9 is a configuration example of the second cache memory 100 of FIG. 900 is a determination circuit, 901
Numerals 903 are cells for holding a pair of valid bit, address and data. The cells 901 to 903 are read addresses 210, registration requests 124, write data 211,
It receives a write request 125 as an input and outputs data 110. Also, the cells 901 to 903 send hit signals 910 to 912 to the determination circuit 900, respectively. Cell 90
1 receives the transfer address 216 and the transfer data 215, and sends the address 913 and the data 914 to the cell 902. Similarly, cell 902 sends addresses 915 and 916 to the next cell. The last cell 912 has an address 917, a data 9
Receive 18.

The determination circuit 900 determines if any one of the hit signals 910 to 912 from the cells 901 to 903 is asserted, the control circuit 103 and the selector 104.
The hit signal 111 to is asserted. Cell 901 is
The read address 210 is compared with the address held internally, and if they match and are valid, the hit signal 91
0 is transmitted and the corresponding data to be held internally is stored in the bus 11
Output to 0. When the write request 125 is asserted, the address held internally and the write address 2
If 10 is compared and they match and the valid bit is asserted, the content of the write data 211 is fetched.
In parallel with the above operation, when the registration request 124 is asserted, the valid bit is asserted and the transfer address 21
6, The transfer data 215 is taken in inside. Cell 9 at this time
02 receives the address and data held in the cell 901 through signals 913 and 914, respectively. That is, the cells 901 to 903 are FIFO. Figure 10
It is a configuration example of the cell 901 of FIG. 1,000, 100
Reference numerals 1 and 1002 denote registers that hold valid bits, addresses, and data, respectively. 1004 is a comparator,
AND gates 1005 and 1006, and a tri-state buffer 1003. The registration request 124 is connected to a register 1000 that holds a valid bit, a register 1001 that holds an address, and a register 1002 that holds data. When the registration request 124 is asserted, the valid bit 1000 is set, the register 1001 holding the address fetches the transfer address 216, and the register 1002 holding the data fetches the data 215. The comparator 1004 compares the address 210 with the output 913 of the register holding the address. A
The ND gate 1006 asserts the hit signal 910 when the output of the comparator 1004 is asserted and the valid bit is asserted, opens the tri-state buffer 1003, and transfers the contents of the register holding the data to the data bus 110. Send out. Also, hit signal 9
When AND gate 1005 detects that 10 is asserted and the write request is asserted, signal 1008 to register 1002 holding data is asserted,
Register 1 for holding the write data 211
002.

As described above, the second cache memory 10
0 is a fully associative method and instruction unit 2
Since the memory reference instruction from 01 and the data transfer from the main memory 203 are processed in parallel, the cell structure is complicated, but since the number of entries is as small as 64, the overall size is small, and Speeding up is also possible.

The second cache memory 100 has a PF
2 instructions are used to store data that will not be reused, so the PF2 instruction causes the main memory 203
Since only the data that has been transferred from, but is not yet used by the LD instruction is temporarily held, the hit rate is high and the performance can be improved even if the capacity is small.

Since the block size of the cache memory in FIG. 9 is as small as 4 bytes, the block size is set to the first block.
It is possible to increase the number of entries with the same capacity as compared with the case where the cache memory has the same 16 bytes. Therefore, even when a large number of array data are processed at one time, it is possible to store each array in a separate entry, and it is possible to prevent performance degradation due to insufficient number of entries. Further, since the data transfer from the main memory is performed in units of 4 bytes, even when processing data of discontinuous addresses, it is possible to perform high-speed processing without transferring unnecessary data. .

FIG. 11 is a configuration example of the first cache memory of FIG. 1100 is an address array, 1101
Is a valid bit, 1102 is a data array, 1104 is a comparator, 1105 is an AND gate, 1103 is a selector. The selector 1103 is controlled by the control signal 123, selects the transfer data 215 or the write data 211, and sends the output to the data array 1102.

Address array 1100, valid bit 11
01 is accessed by the lower bit 130-1 of the address 130. The comparator 1104 compares the address array output 1106 with the higher order 130-2 of the address 130. When 1105 detects that the output of the comparator is asserted and the valid bit 1107 is asserted, it outputs a hit signal 112. Also, write signal 1
When 22 is asserted, it takes the address 130-2 and raises the corresponding valid bit. The data array is accessed by the lower bits 130-1 of the address 130, and the read data is sent to the bus 113. When the write signal 122 is asserted, the selector 1103
Write the output of.

The first cache memory 101 has a capacity of 1M.
The number of bytes is larger than that of the second cache memory 100, but since it is one port, it is not so large as a whole and high-speed operation can be expected.

FIG. 14 shows an example of the configuration of the control circuit 103 shown in FIG. 1400, 1406, 1410 are OR gates, 14
01 to 1405, 1407 to 1409, 1411 are ANs
It is a D gate. A decoder 1412 has a function of decoding the control signal 213-2 by the instruction unit 201 and determining whether or not the instruction being executed is each instruction of LD, ST, PF1, and PF2.

FIG. 15 shows a second configuration example of the memory unit 202 of FIG. The configuration example of FIG. 15 is almost the same as the configuration example of FIG. 2, except that an interface 130 is provided between the first cache memory 101 and the second cache memory 100.

The first problem of the configuration example of FIG. 2 is that when a small-to-medium-sized program is executed using the PF1 instruction, the second problem is
The cache memory is wasted. The second problem is that since the first cache memory is a direct map, the hit rate is lower than that of a set associative cache memory having the same capacity.
The embodiment of FIG. 15 solves this problem.

In the embodiment shown in FIG. 15, when the first cache memory 101 misses, first, the second cache memory 100 is searched, and if there is a hit, the interface 1
Corresponding data is transferred from the second cache memory 100 to the first cache memory 101 through the numeral 30. Also, when registering in the first cache memory,
The overflowed data is transferred to the second
Registered in the cache memory 100. Such a cache is called a victim cache, and it is possible to improve the hit rate compared to the cache memory of the direct map method. Normann P. Jouppi, “Improving Direct-Map
ped Cache Performance by theAddition of a small Fu
lly-Associative Cache and Prefetch Buffers, ”Proc.
17th Symp. On Comp. Arch., Sattle, WA, pp364−373,
Written in may, 1990.

According to the second embodiment of FIG. 15, it is possible to improve the performance by effectively utilizing both the first cache memory 101 and the second cache memory 100 for a small-to-medium-sized program. There is.

FIG. 23 shows a second configuration example of the first cache memory 101 of FIG. The cache memory in FIG. 23 has a capacity of 1 Mbytes, a block size of 16 bytes, and 2
This is a wayset associative cache memory. 2301 and 2303 are address arrays, 230
2, 2304 are valid bits, 2305, 2306 are data arrays, 2307, 2308 are comparators, 230
9 is an array selection memory, 2310, 2312, 231
3,2314,2315 are AND gates, 2311,23
16 is an OR gate, and 2320 and 2322 are selectors. In the following description, the address array 2301, the valid bit 2302 and the data array 2305 are collectively referred to as the array 1, the address array 2303, the valid bit 2304 and the data array 2306 are collectively referred to as the array 2.

The selector 2320 is controlled by the control signal 123, and transfers data 215 or write data 21.
1 is selected and the output 2330 is output to the data arrays 2305 and 23.
Send to 06. The first address array 2301 and valid bit 2302 are the lower bits 130- of the address 130.
Accessed with 1. The comparator 2307 outputs the address array output 2331 and the high-order bit 13 of the address 130.
Compare 0-2. The output of the comparator 2307 is asserted in the AND gate 2314, and the valid bit 2332
When it detects that is asserted, it outputs the array 1 hit signal 2335. Also, the first address array 2
When the write signal 2337 of array 1 is asserted, 301 and valid bit 2302 fetch the address 130-2 and set the corresponding valid bit. Similarly, the second
Address array 2303 and valid bit 2304 are accessed by the lower bits 130-1 of address 130. The comparator 2308 outputs the address array output 233.
3 and the upper bits 130-2 of the address 130 are compared. When the AND gate 2315 detects that the output of the comparator 2308 is asserted and the valid bit 2334 is asserted, the hit signal 233 of the array 2 is detected.
6 is sent out. Also, the second address array 2303 and valid bit 2304 take in the address 130-2 and raise the corresponding valid bit when the write signal 2338 of the array 2 is asserted. The OR gate 2316 outputs the hit signal 2335 of the array 1 and the hit signal 2 of the array 2.
Hit signal 11 when any of 336 is asserted.
3 is sent out. The first data array 2305 is accessed by the lower bits 130-1 of the address 130 and sends the read data to the bus 2339. When the write signal 2337 of array 1 is asserted, the output 2330 of the selector 2320 is written. Similarly, the second data array 2306 has the lower bit 1 of the address 130.
The data read and accessed by 30-1 is transferred to the bus 2
340. When the write signal 2338 of the array 2 is asserted, the output 23 of the selector 2320
Write 30. The selector 2322 selects the output 2339 of the first data array when the hit signal 2335 of the array 1 is asserted, and selects the output 2340 of the second data array otherwise, and outputs the result to the data bus 112. Send out. The array selection memory 2309 holds information on which of the array 1 and the array 2 is written when the write signal 122 is asserted.
When the transfer data 215 transferred from the main memory is written, the array 2 was written last time, the array 2 is written, and the last written data is the array 2, array 1 is written. Write. On the other hand, when the write data 211 of the store instruction transferred from the instruction unit is written, the array that hits one of the array 1 and the array 2 is written, and the information held in the array selection memory 2309 is ignored. Hereinafter, a method of generating the write signal 2337 of the array 1 and the write signal 2338 of the array 2 will be described. The array selection memory 2309 is accessed by the lower bit 130-1 of the address 130, and the read data is
It is sent to the ND gate 2310. When the write signal 122 is asserted, the value of the array selection signal 2341 is written. The AND gate 2310 outputs the hit signal 11
When 3 is not asserted and the output of the array selection memory 2309 is not asserted, the control signal 2342 is transmitted. The OR gate 2311 sends out the array selection signal 2341 when either the hit signal 2335 of the array 1 or the control signal 2342 is asserted. Array 1 when array select signal 2341 is asserted
Array select signal 2341
Indicates that the array 2 is to be written when is not asserted. The AND gate 2312 outputs the write signal 2337 of the array 1 when the write signal 122 is asserted and the array select signal 2341 is asserted.
Is sent. Similarly, in the AND gate 2313, the write signal 122 is asserted, and the array selection signal 2341 is output.
Array 2 is asserted, array 2 write signal 2338 is sent. The cache memory in FIG.
Since the method is the way set associative method, the physical quantity is larger than that of the cache memory of FIG. 11, but since block conflict can be prevented from occurring, the hit rate is improved as compared with the cache memory of FIG.

FIG. 24 shows a second configuration example of the second cache memory 100 of FIG. The cache memory in FIG. 24 has a capacity of 2 Kbytes, a block size of 32 bytes, 2
This is a wayset associative cache memory. 2401 and 2403 are address arrays and 240
2, 2404 are valid bits, 2405, 2406 are data arrays, 2407, 2408 are comparators, 240
9 is an array selection memory, 2410, 2411, 241
2, 2413, 2414, 2415 are AND gates, 2
Reference numeral 416 is an OR gate, 2417 is an inverting circuit, and 2422 is a selector. In the following description, the address array 24
01, valid bit 2402 and data array 2405 are collectively referred to as array 1, address array 2403, valid bit 2404 and data array 2406 are collectively referred to as array 2.

The first address array 2401 and valid bit 2402 are the lower bits 2 of the read address 210.
The value of the address specified in 10-1 is output. The comparator 2407 compares the address array output 2431 with the high-order bits 210-2 of the address 210. When AND gate 2414 detects that the output of comparator 2407 is asserted and valid bit 2432 is asserted, it outputs hit signal 2435 of array 1.
Also, the first address array 2401, valid bit 240
2 is the lower bit 21 of the read address 210 when the first write signal 2437 of array 1 is asserted.
The read address 21 is added to the address specified by 0-1.
The upper bit 210-2 of 0 is taken in and the corresponding valid bit is set. Also, the second write signal 24 of the array 1
When 39 is asserted, the upper bit 216-2 of the transfer address 216 is fetched into the address specified by the lower bit 216-1 of the transfer address 216, and the corresponding valid bit is set. Similarly, the second address array 24
03, valid bit 2404, read address 210
The value of the address designated by the lower bit 210-1 of the is output. Comparator 2408 outputs address array output 2
433 and the upper bits 210-2 of the address 210 are compared. When the AND gate 2415 detects that the output of the comparator 2408 is asserted and the valid bit 2434 is asserted, the hit signal 243 of the array 2 is detected.
6 is sent out. Also, the second address array 2403 and the valid bit 2404 are the same as the first write signal 2 of the array 2.
When 438 is asserted, the upper bit 210-2 of the read address 210 is fetched into the address specified by the lower bit 210-1 of the read address 210,
Set the corresponding valid bit. Further, when the second write signal 2440 of the array 2 is asserted, the upper bit 216-2 of the transfer address 216 is fetched into the address designated by the lower bit 216-1 of the transfer address 216, and the corresponding valid bit is fetched. Stand up. OR gate 241
6 outputs the hit signal 111 when either the hit signal 2435 of the array 1 or the hit signal 2436 of the array 2 is asserted. First data array 2405
Sends the data of the address specified by the lower bit 210-1 of the read address 210 to the bus 2441. When the first write signal 2437 of the array 1 is asserted, the write data 211 is written to the address specified by the lower bit 210-1 of the read address 210.
Write. When the second write signal 2439 of the array 1 is asserted, the transfer data 21 is transferred to the address specified by the lower bit 216-1 of the transfer address 216.
Write 5. Similarly, the first data array 2406 outputs the data of the address specified by the lower bit 210-1 of the read address 210 to the bus 2442.
When the first write signal 2438 of array 2 is asserted, the lower bit 21 of read address 210 is
The write data 211 is written to the address designated by 0-1. When the second write signal 2440 of the array 1 is asserted, the transfer data 215 is written to the address designated by the lower bit 216-1 of the transfer address 216. The selector 2422 selects the output 2441 of the first data array when the hit signal 2435 of the array 1 is asserted, and selects the output 2442 of the second data array otherwise, and outputs the result to the data bus 110.
Send to. Array selection memory 2409 has a registration request 1
24, or when write request 125 is asserted,
Information on which of array 1 and array 2 has been written is held. When the transfer data 215 transferred from the main memory is written, the array 2 was written last time, the array 2 is written, and the last written data is the array 2, array 1 is written. Write. On the other hand, transferred from the instruction unit,
When writing the write data 211 of the store instruction,
Data is written to the one of the arrays 1 and 2 which hits, and the information held in the array selection memory 2409 is ignored. Below, write signal 2 of array 1
437 and 2439 and the write signal 243 of the array 2
A method of generating 8,2440 will be described. The array selection memory 2409 stores the lower bits 216-of the transfer address 216.
The data of the address designated by 1 is converted into the inversion circuit 2417.
Send to. When the write request 125 is asserted, the value of the hit signal 2435 of the array 1 is written to the address designated by the lower bit 210-1 of the read address 210. When the registration request 124 is asserted, the value of the array selection signal 2443 is written to the address designated by the lower bit 216-1 of the transfer address 216. The inverting circuit 2417 outputs the array selection signal 24 when the output of the array selection memory 2409 is not asserted.
43 is sent out. The AND gate 2410 outputs the hit signal 2435 of the array 1 when the write request 125 is asserted.
Asserts the first write signal 2437 for array 1 when is asserted. The AND gate 2411 outputs the hit signal of the array 1 when the write request 125 is asserted.
When 2435 is not asserted, it sends array 2 first write signal 2438. Similarly, the AND gate 2412 outputs the second write signal 2439 of the array 1 when the registration request 124 is asserted and the array selection signal 2443 is asserted. The AND gate 2413 operates when the registration request 124 is asserted and the array selection signal 2443 is not asserted.
The second write signal 2440 is transmitted. Since the cache memory in FIG. 24 is a 2-way set associative method, it is a full set associative method.
The capacity can be increased with a small amount of material compared to the cache memory of. Moreover, since the block size is as large as 32 bytes, the amount of data transferred from the main memory at one time is large. Therefore, when processing data of consecutive addresses, it is necessary to process a certain amount of data from the main memory to the second cache memory as compared with the cache memory of FIG. 9 having a small block size. Performance is improved due to the small number of prefetch instructions.

FIG. 16 is a schematic diagram of the second embodiment of the present invention. Of the constituent elements of the embodiment shown in FIG. 16, those which are the same as those of the embodiment shown in FIG. 1 are designated by the same reference numerals.
The feature of this embodiment is that two address buses 1710 and 17 are provided.
13 and four data buses 1711, 1712, 1
714, 1715. by this,
It is possible to perform parallel processing of two memory reference instructions.

In the embodiment shown in FIG. 16, the instruction unit 170 is used.
1, a memory unit 1702 and a main memory 1703.

The instruction unit 1701 is a unit for processing instructions and is composed of an instruction cache 1801, a memory interface 1802, and an arithmetic unit 1820. The instruction unit 1701 includes buses 1710 to 17
12, and exchanges data with the first cache memory 101 and the second cache memory 1690 via the buses 1713 to 1715. In other words, via the address buses 1710 and 1713, 4-byte width write data buses 1711 and 1714, and the control signal line 1716,
The memory unit 170 stores address, data and control signals.
2. Send to main memory 1703.

The memory unit 1702 includes a first cache memory 101, a second cache memory 1690, and a selector 10 for inputting / outputting data to / from these.
4, 1695 and a control unit 1692. The first cache memory 101 has the same configuration as the first cache memory of the embodiment shown in FIG. 1, and is a large-capacity one-port cache memory. The second cache memory 1690 is a cache memory having a small capacity and three ports. The memory unit 1702 sends data and a wait signal to the instruction unit 1701 via the 4-byte width read data buses 1712 and 1715 and the wait signal line 1717, and the request signal lines 1723 and 172.
4, the request signal is sent to the main memory 1703.

The main memory 1703 is a storage device for storing instructions and data, and transfers data to the first cache memory 101 and the second cache memory 1690 via the buses 1720 and 1721. That is, the main memory 17
03 is a transfer data bus 1720 and a transfer address bus 1
Data, an address and a response signal are sent to the memory unit 1702 via the 721 and the response signal line 1722.

The format of the operation code of the instruction processed by the instruction unit 1701 of FIG. 16 is the same as that shown in FIG. The types of instructions to be processed are shown in FIG.
Is the same as that shown in.

FIG. 18 shows the instruction unit 1701 of FIG.
It is a configuration example of. 1801 is an instruction cache, 1803
Is a decoder, 1802 is a memory interface, 180
5 is a register, 1806 is an ALU, 1841, 1842
Is an address adder. The instruction cache sends the instruction to the decoder 1803 and the memory interface 1802 via the bus 1807. The decoder 1803 decodes the received instruction, registers 1805, ALU1
806, the address adders 1841 and 1842 to the signal 183
Control by 0. The ALU1806 receives data from the register 1805 through the buses 1812 and 1813,
The operation is performed and the result is sent to the register 1 through the bus 1814.
Write to 805. The first address adder 1841 is
The data is received from the register 1805 through the buses 1810 and 1811, added, and the result is loaded or sent to the bus 1713 as an address to be stored. At the time of storing, the data to be stored is read from the register 1805 and sent to the bus 1714. When loading,
The read data is received through the bus 1715 and written in the register 1805. Similarly, the second address adder 1842 receives the bus 1814, 1 from the register 1805.
The data is read through 815, added, and the result is loaded or sent to the bus 1710 as an address to be stored. At the time of storing, the data to be stored is read from the register 1805 and sent to the bus 1711. At the time of loading, the read data is received through the bus 1712 and written in the register 1805.

The memory interface 1802 uses the instruction L.
When executing D, ST, PF1, and PF2, control signal 171
6 is sent, and the wait signal 1717 is received. Waiting signal 17
When 17 becomes "1", the signal 1808 is sent to the decoder 1803, and the pipeline is stopped until the wait signal 1717 becomes "0".

FIG. 19 is a diagram for explaining the pipeline processing. IF is an instruction read stage, D is a decode stage, E is an operation and address addition stage, A
Is a cache access stage, W is a register write stage, R is a stage for reattempting cache access, and X is a wait stage. When two load instructions, instruction 1 and instruction 2, are processed in parallel, instruction 1 simultaneously accesses the first cache memory and the second cache memory at the A stage, and instruction 2 only accesses the second cache memory at the A stage. To access. Since the instruction 1 hits the second cache memory, the data read from the second cache memory is written to the register at the W stage. Since the instruction 2 hits the second cache memory, the data read from the second cache memory is
Write to register at W stage. When the instructions 3 and 4 are processed in parallel, the instruction 3 simultaneously accesses the first cache memory and the second cache memory in the A stage, and the instruction 4 accesses only the second cache memory in the A stage. Since the instruction 3 hits the second cache memory, the data read from the second cache memory is written to the register at the W stage. Instruction 4 is
Since the second cache memory misses, the first cache memory is accessed at the R stage and the read data is written to the register at the W stage. When the instruction 5 and the instruction 6 are processed in parallel, the instruction 5 simultaneously accesses the first cache memory and the second cache memory in the A stage, and the instruction 6 accesses only the second cache memory in the A stage. Since the instruction 5 hits the first cache memory, the data read from the first cache memory is written to the register at the W stage. Since the instruction 6 hits the second cache memory,
The data read from the cache memory is written in the register in the W stage. When the instructions 7 and 8 are processed in parallel, the instruction 7 simultaneously accesses the first cache memory and the second cache memory in the A stage, and the instruction 8 accesses only the second cache memory in the A stage. Since the instruction 7 hits the first cache memory, the data read from the first cache memory is written to the register at the W stage. Since the instruction 8 misses the second cache memory, the first cache memory is accessed at the R stage, and the read data is written as W
Write to register on stage.

The pipeline processing at the time of executing the store instruction is the same as that at the time of executing the load instruction. The cache is checked at the A stage or the R stage, and if it is hit, writing to the cache is performed at the A stage or the R stage.

As described above, when the second instruction hits the second cache memory, two memory reference instructions are processed in parallel. Therefore, by transferring the data to the second cache memory using the PF2 instruction, it becomes possible to always perform parallel processing of the two memory reference instructions and improve the performance.

FIG. 17 shows the memory unit 170 of FIG.
2 is a configuration example of No. 2. 101 is the first cache memory,
1690 is a second cache memory, 102 is a 4-entry prefetch queue, 1603 is a control circuit, 10
4, 1740, 1742, 1731 and 1734 are selectors.

The first cache memory 101 has an address 1630, transfer data 1720, selector control signal 1
623, write signal 1622, write data 174
4 is input, and read data 1612 and hit signal 1613 are output. Second cache memory 16
90 is address 1710, 1713, transfer address 1
721, transfer data 1720, registration signal 1624, write signals 1625 and 1626, write data 171
1,1714 are received and read data 1610,171
2. Hit signals 1611 and 1681 are transmitted. The prefetch queue 102 has a cache selection signal 1733, a transfer address 1721, an address 1730, and a set signal 1
20, the reset signal 121 is received, and the full signal 114, the hit signal 115, and the cache selection signal 116 are output.

The control circuit 1603 outputs control signals 1716-3 and 1716-4 from the instruction unit, a full signal 114, a hit signal 115 and a cache selection signal 116 from the prefetch queue 102 and a response signal 17 from the main memory.
22 from the second cache memory 1690 and hit signals 1611 and 1681 from the second cache memory 1690.
1, the hit signal 1613 is received, the wait signal 1717 is sent to the instruction unit, the set signal 120, the reset signal 121, and the selection signal 173 are sent to the prefetch queue 102.
2 to the main memory, transfer request signals 1723 and 1724,
A registration signal 1624 to the second cache memory 1690,
Write signals 1625, 1626, write signal 1622 to the first cache memory 101, selector control signal
1623 is sent to selectors 1740 and 1742 as selector control signals 1623 and 1627, respectively.

The selector 104 receives the data 1610 and the hit signal 1611 from the second cache memory 1690 and the data 1612 and the hit signal 1613 from the first cache memory 101. If the hit signal 1611 is asserted, the data 1610 and the hit signal 1611 are received. If 1613 is asserted, the data 1612 is read as output,
Output to the data bus 1715. Also selector 1740
Are address 1713, address 1710, transfer address 1 under the control of selector control signals 1623 and 1627.
721 is selected and sent to the first cache memory 101 as the output 1630. Also selector 17
42 selects either the write data 1714 or the write data 1711 under the control of the selector control signal 1627, and sends it to the first cache memory 101 as an output 1744. Further, the selector 1731 controls the address 1713 and the address 1710 under the control of the selection signal 1732.
Is output to the prefetch queue 102 as the output 1730. Further, the selector 1734 controls the selection signal 1732 to set the selection signals 1716-1,
Either one of the set selection signals 1716-2 is selected and sent as the output 1733 to the prefetch queue 102.

The first cache memory 101 reads the cache memory with the contents of the address 1630 when the write signal 1622 instructs the read,
The read data 1612 and the hit signal 1613 are transmitted. Further, when the write signal 1622 is instructing to write, the transfer data 1720 is set when the selector control signal 1623 is 1, and the write data 1744 is set when it is 0.
Write the contents of.

When the write signal 1625 is negated and read is instructed, the second cache memory 1690 checks the contents of the cache at the address 1713 and reads the read data 1610 and the hit signal 1611.
Is sent. When the write signal 1625 is asserted and a write is instructed, the cache is checked, and if there is a hit, the contents of the write data bus 1714 are written. Similarly, when the write signal 1626 is negated and a read instruction is issued, the address 1
The data read out by checking the cache contents in 710 1
712 and a hit signal 1681 are transmitted. When the write signal 1626 is asserted and the writing is instructed, the cache is checked, and if there is a hit, the contents of the write data bus 1711 are written. When the registration signal 1624 is asserted in parallel with the above operation,
A pair of transfer address 1721 and transfer data 1720 is registered.

The prefetch queue 102 is a queue capable of holding an address of data being transferred from the main memory up to 4 entries. When the set signal 120 is asserted, the address 1730 and the cache selection signal 1 are stored.
The contents of 733 are registered in the queue. Also, reset signal 1
When 21 is asserted, the cache selection signal 116 corresponding to the transfer address 1721 is output to invalidate the entry. Further, the address 1730 is compared with the address held internally, and if the entry is being transferred from the main memory, the hit signal 115 is asserted. Further, while the valid address is held in all the entries, the full signal 114 indicating it is asserted.

FIG. 22 shows a configuration example of the control circuit 1603 shown in FIG. The control circuit 1603 controls the control signal 1716-3 relating to the first instruction and the control signal relating to the second instruction.
Decode 1716-4 to LD, ST, PF1, PF2
Accepts the activation of each instruction. The first instruction is the LD instruction, and the hit signal 1613 from the first cache memory
And the first hit signal 16 from the second cache memory
When both 11 are negated, both caches miss and therefore the first instruction wait signal 2201 is asserted to make the instruction unit wait while transferring data from the main memory. Also, the first instruction is LD,
Both the hit signal 1613 from the first cache memory and the first hit signal 1611 from the second cache memory are negated by the PF1 and PF2 instructions, and the hit signal 115 from the prefetch queue is also negated. Full signal from prefetch queue 1
When 14 is asserted, the instruction fetch unit 2201 is asserted in order to make the instruction unit wait until the prefetch queue becomes available because the prefetch queue is full and instructions cannot be queued. Further, the first instruction is the LD, PF1, PF2 instruction, both the hit signal 1613 from the first cache memory and the first hit signal 1611 from the second cache memory are negated, and the prefetch queue When both the hit signal 115 and the full signal 114 are negated, the transfer request signal 1723 to the main memory is asserted. At the same time, the selection signal 1732 for the prefetch queue and the set signal 120 are asserted to register the first instruction in the prefetch queue. The first instruction is the ST instruction, and the hit signal 1 from the first cache memory
When 613 is asserted, the write signal 1622 to the first cache memory is asserted to write the data to the first cache memory. Similarly, when the first instruction is the ST instruction and the first hit signal 1611 from the second cache memory is asserted, the data is written to the second cache memory in order to write the data to the second cache memory. Write signal 1
Assert 625.

On the other hand, the second instruction is LD, ST, PF1,
When the second hit signal 1681 from the second cache memory is negated in the PF2 instruction, the wait signal 2202 of the second instruction is asserted because it is necessary to access the cache 1 in the next cycle. The access of the second instruction to the cache 1 is performed when the wait signal 2201 of the first instruction is negated and the access of the first instruction to the cache is completed. AND gate 221
1, the wait signal 2201 of the first instruction is negated,
When the wait signal 2202 of the second instruction is asserted,
Assert the control signal 2203. When the control signal 2203 is asserted, the register 2212 asserts the select signal 1627 to the cache 1 after one cycle. When the selection signal 1627 is 1, the second instruction cache 1
Is accessed, but the cache of the first instruction is not accessed. When the second instruction is the LD instruction, the select signal 1627 to the cache 1 is asserted, and the hit signal 1613 from the first cache memory is negated, both caches miss, The second instruction wait signal 2202 is asserted to make the instruction unit wait while the data is transferred from the memory. The second instruction is an LD, PF1, or PF2 instruction, the select signal 1627 to the cache 1 is asserted, and the hit signal 16 from the first cache memory 16
When 13 is negated and the hit signal 115 from the prefetch queue is also negated but the full signal 114 from the prefetch queue is asserted, the prefetch queue is full and the instruction cannot be queued. Therefore, in order to make the instruction unit wait until the prefetch queue becomes available, the wait signal 2202 of the instruction 2 is asserted. The second instruction is L
In the D, PF1, and PF2 instructions, the select signal 1627 to the cache 1 is asserted, the hit signal 1613 from the first cache memory is negated, and the hit signal 115 from the prefetch queue is also the full signal 114. Also, when it is negated, the transfer request signal 1724 to the main memory is asserted. At the same time, the set signal 120 to the prefetch queue is asserted, and the second instruction is registered in the prefetch queue. The second instruction is the ST instruction, and the selection signal 1627 to the cache 1
Is asserted and the hit signal 1613 from the first cache memory is asserted, the write signal 1622 to the first cache memory is asserted to write the data to the first cache memory. When the second instruction is the ST instruction and the second hit signal 1681 from the second cache memory is asserted, the second data is written to the second cache memory in order to write the data to the second cache memory. Write signal 1626 is asserted.

The OR gate 2213 waits for the instruction unit when either the wait signal 2201 for the first instruction or the wait signal 2202 for the second instruction is asserted.
Assert 1717.

When the response signal 1722 from the main memory is asserted, the reset signal 121 to the prefetch queue is asserted to reset the entry from the prefetch queue 102. At the same time, in order to register the transfer data in the cache, the cache selection signal 116 is viewed, and when it is instructed to write to the first cache memory, the write signal 1622 to the first cache memory and the selection signal 1623. Is asserted to instruct to write to the second cache memory, the registration signal 162 to the second cache memory is
Assert 4.

FIG. 20 shows an example of the configuration of the second cache memory 1690 shown in FIG. The cache memory in FIG. 20 is a full-associative cache memory having a block size of 4 bytes and a capacity of 256 bytes. 2000
Is a decision circuit, 2001 to 2003 are valid bits, addresses,
A cell that holds a pair of data. Cell 2001-
2003 receives read addresses 1713 and 1710, registration request 1624, write data 1714 and 1711, and write requests 1625 and 1626 as inputs, and outputs data 1610 and 1712. Also, cells 2001 to
2003 are hit signals 2010 to 2012 and 2 respectively.
020-2022 are sent to the determination circuit 2000. The cell 2001 has a transfer address 1721 and transfer data 1720.
Address 2013 and data 2014 in cell 20
Send to 02. Similarly, cell 2002 has addresses 2015, 2
Send 016 to the next cell. The last cell 2003 receives the address 2017 and the data 2018.

The determination circuit 2000 is composed of cells 2001 to 200.
If any one of the hit signals 2010 to 2012 from 3 is asserted, the hit signal 1611 is asserted. Similarly, if any one of the hit signals 2020 to 2022 from the cells 2001 to 2003 is asserted, the hit signal 1681 is asserted. Cell 2001
Compares the read address 1713 with the address held inside, and if they match and is valid, sends a hit signal 2010 and outputs the corresponding data held inside to the bus 1610. When the write request 1625 is asserted, the internally held address is compared with the address 1713. If they match and the valid bit is asserted, the content of the write data 1714 is fetched. Similarly, the read address 1710 is compared with the address held internally, and if they match and are valid, the hit signal 2020 is sent and the corresponding data held internally is output to the bus 1712. Write request 1
When 626 is asserted, the address held internally is compared with the address 1710. If they match and the valid bit is asserted, the write data 171 is written.
Take in the contents of 1. In parallel with the above operation, when the registration request 1624 is asserted, the valid bit is asserted and the transfer address 1721 and the transfer data 1720 are fetched inside. At this time, the cell 2002 outputs the address and data held by the cell 2001 to the signal 201.
Take in through 3,2014. That is, cells 2001 to
2003 is a FIFO.

FIG. 21 shows a structural example of the cell 2001 of FIG. Reference numerals 2100, 2101 and 2102 are registers that hold valid bits, addresses and data, respectively. 21
04 and 2114 are comparators, and 2105 and 2106.
2115 and 2116 are AND gates, 2103 and 211
3 is a tri-state buffer. The registration request 1624 includes a register 2100 holding a valid bit, a register 2101 holding an address, and a register 21 holding data.
02 is connected. When the registration request 1624 is asserted, the valid bit 2100 is set, and the register 2101 holding the address has the transfer address 1721.
And the register 2102 for holding the data fetches the transfer data 1720. The comparator 2104 compares the output 2013 of the register holding the address with the address 1713. The AND gate 2106 asserts the hit signal 2010 when the output of the comparator 2104 is asserted and the valid bit is asserted, opens the tri-state buffer 2103, and outputs the contents of the register holding the data to the data bus 1610. Send out. Further, the AND signal 21 indicates that the hit signal 2010 is asserted and the write request 1625 is asserted.
05 detects, the register 2102 for holding the data
Signal 2108 to write data 171
4 is loaded into the register 2102 which holds the data.
Similarly, the comparator 2114 compares the address 1710 with the output 2013 of the register holding the address. The AND gate 2116 asserts the hit signal 2020 when the output of the comparator 2114 is asserted and the valid bit is asserted, opens the tri-state buffer 2113, and outputs the contents of the register holding the data to the data bus 1712. Send out. When the AND signal 2115 detects that the hit signal 2020 is asserted and the write request 1626 is asserted,
A signal 2118 to the register 2102 holding the data is asserted, and the write data 1711 is fetched in the register 2102 holding the data.

As described above, the cache memory of FIG. 20 is of the fully associative type, and since the access of two memory reference instructions and the writing of the transfer data from the main memory are processed in parallel, the configuration is complicated. Capacity is 2
Since it is as small as 56 bytes, the overall size is small, and the speed can be increased.

FIG. 25 is a schematic diagram of the third embodiment of the present invention. Of the constituent elements of the embodiment shown in FIG. 25, the same constituent elements as those of the embodiment shown in FIG. 1 are designated by the same reference numerals.
The feature of this embodiment resides in that the memory unit 2602 is provided with a register 2580 for holding the information of the ST instruction. As a result, the cache hit determination of the ST instruction and the data writing can be performed in different machine cycles, so that the time required for one machine cycle when processing the ST instruction is reduced and the operating frequency is improved. .

In the embodiment of FIG. 25, the instruction unit 201,
It is composed of a memory unit 2602 and a main memory 203.

The instruction unit 201 has the same structure as the instruction unit of the embodiment shown in FIG.

The memory unit 2602 includes a first cache memory 101, a second cache memory 2590 and a selector 10 for inputting / outputting data to / from these.
4, 2595 and a control unit 2592. The first cache memory 101 has the same configuration as the first cache memory of the embodiment shown in FIG. 1, and is a large-capacity one-port cache memory. The second cache memory 2590 accesses the memory reference instruction and
It has three ports for parallel processing of writing ST command data and writing transfer data from the main memory. The memory unit 2602 sends data and a wait signal to the instruction unit 201 via the 4-byte width read data bus 212 and the wait signal line 214, and sends a request signal to the main memory 203 via the request signal line 218. To do.

The main memory 203 has the same structure as the main memory of the embodiment shown in FIG.

The format of the operation code of the instruction processed by the instruction unit 201 of FIG. 25 is the same as that shown in FIG. The types of instructions to be processed are the same as those shown in FIG.

FIG. 27 is a diagram for explaining the pipeline processing. IF is an instruction read stage, D is a decode stage, E is an operation and address addition stage, A
Is a cache access stage, W is a register write stage, R is a stage for redoing cache access, X is a wait stage, and S is a data write stage of an ST instruction. In the pipeline of FIG. 27, unlike the pipeline of FIG.
Perform on the S stage, not the stage. First, FIG.
(A) will be described. Instruction 1 simultaneously accesses the first cache memory and the second cache memory in the A stage. Since the instruction 1 hits the second cache memory, the instruction 1 writes to the second cache memory in the S stage. Instruction 2 simultaneously accesses the first cache memory and the second cache memory in the A stage.
The instruction 2 is read from the second cache memory by the instruction 1
This is the same cycle as the data write to the second cache memory of, but the second cache memory can process the data read of the LD instruction and the data write of the ST instruction within one machine cycle. Processing can be performed without extra penalties. Since the instruction 2 hits the second cache memory, the data read from the second cache memory is written to the register at the W stage. Next, FIG. 27B will be described. Instruction 1 simultaneously accesses the first cache memory and the second cache memory in the A stage. Instruction 1
Writes to the second cache memory in the S stage because the second cache memory hits. Instruction 2
Simultaneously accesses the first cache memory and the second cache memory at the A stage. The read of the second cache memory of the instruction 2 is the same cycle as the data write of the instruction 1 to the second cache memory, but the second cache memory reads the data of the LD instruction and the S
Since the data writing of the T instruction can be processed within one machine cycle, the processing of the instruction 2 can be executed without an extra penalty. Since the instruction 2 hits the first cache memory, the data read from the first cache memory is written to the register at the W stage. Next, FIG. 27C will be described. Instruction 1 is A
At the stage, the first cache memory and the second cache memory are simultaneously accessed. Since the instruction 1 hits the first cache memory, the instruction 1 writes to the first cache memory in the S stage. Instruction 2 accesses only the second cache memory at the A stage. Since the reading of the first cache memory of the instruction 2 cannot be executed in the same cycle as the data writing of the instruction 1 to the first cache memory, the first cache memory is not accessed in the A stage. Since the instruction 2 hits the second cache memory, it does not access the first cache memory and writes the data read from the second cache memory into the register at the W stage. Next, FIG. 27D will be described. Instruction 1 is A
At the stage, the first cache memory and the second cache memory are simultaneously accessed. Since the instruction 1 hits the first cache memory, the instruction 1 writes to the first cache memory in the S stage. Instruction 2 accesses only the second cache memory at the A stage. Since the reading of the first cache memory of the instruction 2 cannot be executed in the same cycle as the data writing of the instruction 1 to the first cache memory, the first cache memory is not accessed in the A stage. Since the instruction 2 misses the second cache memory, it accesses the first cache memory at the R stage. As a result of accessing the first cache memory in the R stage, the first cache memory is hit, so the data read from the first cache memory is written in the register in the W stage.

As described above, since the hit check of the ST instruction and the writing of data are performed in different stages, 1
The amount of processing performed on the stage is reduced, and processing can be performed at high speed. Further, when the ST instruction hits the second cache memory, the next LD instruction is processed without extra penalty. Therefore, by transferring the data to the second cache memory by using the PF2 instruction, the processing can always be performed without an extra penalty, and the performance is improved.

FIG. 26 shows the memory unit 260 of FIG.
2 is a configuration example of No. 2. 101 is the first cache memory,
2590 is a second cache memory, 102 is a 4-entry prefetch queue, 2503 is a control circuit, 10
4, 2640 are selectors, and 2631, 2632 are registers.

The first cache memory 101 has an address 2530, transfer data 215, and selector control signal 25.
23, write signal 2522, write data 2644
Of the read data 2512 and the hit signal 2513 are output. Second cache memory 259
0 is a read address 210 and a write address 26
13, transfer address 216, transfer data 215, registration signal 2524, write signal 2525, write data 2
644 is received, and read data 2510 and hit signal 2511 are transmitted. The prefetch queue 102 has a cache selection signal 213-1, a transfer address 216, an address 210, a set signal 120, and a reset signal 121.
In response, the full signal 114, the hit signal 115, and the cache selection signal 116 are output.

The control circuit 2503 receives the control signal 213-2 from the instruction unit and the full signal 114, hit signal 115, cache select signal from the prefetch queue 102.
116, the response signal 217 from the main memory, the hit signal 2511 from the second cache memory 2590, the hit signal 2513 from the first cache memory 101, and the wait signal 214 to the instruction unit and the prefetch queue 102. The signal 120 and the reset signal 121, the transfer request signal 218 to the main memory, the registration signal 2524 and the write signal 2525 to the second cache memory 2590, the write signal 2522 and the selector control signal 2523 to the first cache memory 101, Selector control signals 2523 and 2527 are sent to the selector 2640, respectively.

The selector 104 receives the data 2510 and the hit signal 2511 from the second cache memory 2590, the data 2512 and the hit signal 2513 from the first cache memory 101, and when the hit signal 2511 is asserted, the data 2510 and the hit signal 2511. If 2513 is asserted, data 2512 is read as output,
Output to the data bus 212. Also selector 2640
Are address 210, address 2613, transfer address 21 under the control of selector control signals 2523 and 2527.
6 is selected and sent as the output 2530 to the first cache memory 101.

When the write signal 2522 instructs the first cache memory 101 to read, the first cache memory 101 reads the cache memory with the contents of the address 2530,
The read data 2512 and the hit signal 2513 are transmitted. When the write signal 2522 is instructing to write, the transfer data 215 is written when the selector control signal 2523 is 1, and the content of the write data 2644 is written when the selector control signal 2523 is 0.

The second cache memory 2590 checks the contents of the cache at the address 210 and sends the read data 2510 and the hit signal 2511. When the write signal 2525 is asserted and the write is instructed, the address 2613 is searched in the cache,
If there is a hit, the contents of the write data bus 2644 are written. In parallel with the above operation, when the registration signal 2524 is asserted, the pair of the transfer address 216 and the transfer data 215 is registered.

The operation of the prefetch queue 102 is shown in FIG.
The operation of the prefetch queue 102 is the same.

The register 2631 stores the write data 211.
Is received and output to the data bus 2644 in the next cycle. Register 2632 receives address 210,
Output to the bus 2613 in the next cycle.

FIG. 30 shows a configuration example of the control circuit 2503. The control circuit 2503 decodes the control signal 213-2 and receives activation of each instruction of LD, ST, PF1, and PF2. The control signal 2527 is a signal indicating that the store data is written to the first cache memory. When this signal is 1, another instruction cannot access the first cache memory. When the control signal 2527 is 1, the LD, ST, PF1, and PF2 instructions are being executed, and the hit signal 2511 from the second cache memory is negated, it is necessary to access the first cache memory in the next cycle. Because there is
Assert wait signal 214. In addition, the control signal 252
When 7 is 0, the LD instruction is being executed, and both the hit signal 2513 from the first cache memory and the hit signal 2511 from the second cache memory are negated, both caches miss. Therefore, the wait signal 214 is asserted to make the instruction unit wait while the data is transferred from the main memory. Also, control signal 2
527 is 0, and LD, PF1, and PF2 instructions are being executed.
Both the hit signal 2513 from the cache memory and the hit signal 2511 from the second cache memory are negated, and the hit signal 115 from the prefetch queue is also negated, but the full signal 114 from the prefetch queue is When asserted,
Since the prefetch queue is full and the instruction cannot be accumulated in the queue, the wait signal 214 is asserted in order to make the instruction unit wait until the prefetch queue becomes available. Further, when the control signal 2527 is 0, LD, PF
1, the PF2 instruction is being executed, both the hit signal 2513 from the first cache memory and the hit signal 2511 from the second cache memory are negated, and
When both the hit signal 115 and the full signal 114 from the prefetch queue are negated, the transfer request signal 218 to the main memory is asserted. At the same time, the set signal 120 for the prefetch queue is asserted and registered in the prefetch queue. When the control signal 2527 is 0, the ST instruction is being executed, and the hit signal 2513 from the first cache memory is asserted, the control signal 3001 is asserted. Register 3011
Asserts the control signal 2527 in the next cycle when the control signal 3001 is asserted. OR gate 30
13 asserts the write signal 2522 to the first cache memory when the control signal 2527 is asserted. As a result, the store data is written in the first cache memory. Similarly, when the hit signal 2511 from the second cache memory is asserted during execution of the ST instruction, the control signal 3002 is asserted. When the control signal 3002 is asserted, the register 3012 asserts the write signal 2525 to the second cache memory in the next cycle. By this, the second
Store data is written in the cache memory of.

When the response signal 217 from the main memory is asserted, the reset signal 121 to the prefetch queue is asserted to reset the entry from the prefetch queue 102. At the same time, in order to register the transfer data in the cache, the cache selection signal 116 is looked at, and when it indicates the writing to the first cache memory, the write signal 2522 to the first cache memory and the selection signal 2523. Is asserted to instruct to write to the second cache memory, the registration signal 25 to the second cache memory 25
Assert 24.

FIG. 28 is a configuration example of the second cache memory 2590 of FIG. The cache memory in FIG. 28 is a full-associative cache memory with a block size of 4 bytes and a capacity of 256 bytes. 2800
Is a decision circuit, and 2801 to 2803 are valid bits, addresses,
A cell that holds a pair of data. Cell 2801
2803 is a read address 210, a write address 2613, a registration request 2524, and write data 264.
4, write request 2525 is received as input, and data 2
510 is output. The cells 2801 to 2803 output the hit signals 2810 to 2812, respectively, to the determination circuit 2800.
Send to. The cell 2801 receives the transfer address 216 and the transfer data 215, and receives the address 2813 and the data 281.
4 to cell 2802. Similarly, cell 2802 sends address 2815, data 2816 to the next cell. The last cell 2812 has an address 2817, data 2818
Receive.

Judgment circuit 2800 has cells 2801 to 280.
If any one of the hit signals 2810 to 2812 from 3 is asserted, the hit signal 2511 is asserted. The cell 2801 compares the read address 210 with the address held internally and, if they match and is valid, sends a hit signal 2810 and outputs the corresponding internally held data to the bus 2510. When the write request 2525 is asserted, the address held internally is compared with the write address 2613 and they match,
If the valid bit is asserted, the contents of the write data 2644 are fetched. In parallel with the above operation, when the registration request 2524 is asserted, the valid bit is asserted and the transfer address 216 and the transfer data 215 are fetched inside. At this time, cell 2802 is cell 2
The address and data held in 801 are fetched through signals 2813 and 2814, respectively. That is, cell 28
01 to 2803 are FIFO.

FIG. 29 is a structural example of the cell 2801 of FIG. Reference numerals 2900, 2901, and 2902 are registers that hold valid bits, addresses, and data, respectively. 29
04, 2914 are comparators, 2906, 2915,
2916 is an AND gate, and 2903 is a tri-state buffer. The registration request 2524 includes a register 2900 holding a valid bit and a register 29 holding an address.
01, and is connected to a register 2902 that holds data. When the registration request 2524 is asserted, the valid bit 2900 is set, the register 2901 holding the address fetches the transfer address 216, and the register 2902 holding the data fetches the transfer data 215. The comparator 2904 compares the read address 210 with the output 2813 of the register holding the address. The AND gate 2906 is connected to the comparator 2904.
When the output of is asserted and the valid bit is asserted, the hit signal 2810 is asserted, the tri-state buffer 2903 is opened, and the content of the register holding the data is sent to the data bus 2510. On the other hand, the comparator 2914 compares the output 2813 of the register holding the address with the write address 2613. The AND gate 2916 has a comparator 2914.
The hit signal 2920 is asserted when the output of is asserted and the valid bit is asserted.
Hit signal 2920 is asserted, write request 252
When 5 is asserted, the AND gate 2915 asserts the signal 2918 to the register 2902 which holds the data, and fetches the write data 2644 into the register 2902 which holds the data.

As described above, the cache memory of FIG. 28 is of the fully associative type, and is configured to perform parallel processing of memory reference instruction access, ST instruction data writing, and transfer data writing from the main memory. Is complicated, but its capacity is smaller than 256 bytes, so the overall size is small and the speed can be increased. FIG. 31 is a schematic diagram of the fourth embodiment of the present invention. Figure 31
16 are the same as those in the embodiment of FIG. 16, and the same numbers are given to them. The feature of this embodiment is that a 1-port cache memory is used for both the first cache memory and the second cache memory.
The memory reference to the cache memory and the memory reference to the second cache memory are processed in parallel. In the embodiment of FIG. 16, since the second cache memory has a small capacity, there is a problem that the hit rate is lowered for data having high reusability. On the other hand, FIG.
In the embodiment, since the second cache memory can be made large in capacity with a relatively small amount, the hit rate does not decrease even if highly reusable data is put in the second cache memory. Therefore, by dividing a plurality of highly reusable data into the first cache memory and the second cache memory separately, it becomes possible to perform parallel processing of memory reference instructions for highly reusable data. .

The format of the operation code of the instruction processed by the instruction unit 3151 of FIG. 31 is the same as that shown in FIG.

FIG. 33 is a diagram showing the types of instructions processed by the instruction unit shown in FIG. AND, OR, NOT,
The ADD, SUB, and BRA instructions are the same as those explained in FIG.

The load instruction LD1 stores the read data in the register C using the sum of the contents of the register A and the contents of B as an address. This instruction is used when there is a high possibility that there is data in the first cache memory, and the first cache memory is accessed with priority when processing this instruction.

The load instruction LD2 stores the read data in the register C with the address obtained by adding the contents of the registers A and B. This instruction is used when there is a high possibility that there is data in the second cache memory, and the second cache memory is preferentially accessed when processing this instruction.

The store instruction ST1 writes the contents of register A using the contents of register B as an address. This instruction is used when there is a high possibility that there is data in the first cache memory, and the first cache memory is accessed with priority when processing this instruction.

The store instruction ST2 writes the contents of register A using the contents of register B as an address. This instruction is used when there is a high possibility that there is data in the second cache memory, and the second cache memory is preferentially accessed when processing this instruction.

The PF1 and PF2 instructions are the same as those explained in FIG.

FIG. 32 is a diagram for explaining the pipeline processing. IF is an instruction read stage, D is a decode stage, E is an operation and address addition stage, A
Is a cache access stage, W is a register write stage, R is a stage for reattempting cache access, and X is a wait stage. LD1 command or S
When executing the T1 instruction, the first cache memory is accessed at the A stage, and the second cache memory is accessed at the R stage only when a miss occurs. On the other hand, LD
When executing two instructions or ST2 instructions, the second cache memory is accessed at the A stage, and the first cache memory is accessed at the R stage only when a miss occurs. First, the pipeline in FIG. 32A will be described. When two load instructions, instruction 1 and instruction 2, are processed in parallel, instruction 1 accesses the first cache memory at the A stage, and instruction 2 accesses the second cache memory at the A stage. Since the instruction 1 hits the first cache memory, the data read from the first cache memory is written to the register at the W stage.
Instruction 2 hits the second cache memory, so
The data read from the second cache memory is written to the register in the W stage. When the instructions 3 and 4 are processed in parallel, the instruction 3 accesses the first cache memory in the A stage, and the instruction 4 accesses the second cache memory in the A stage. Since the instruction 3 hits the first cache memory, the data read from the first cache memory is written to the register at the W stage. Since the instruction 4 misses the second cache memory, the first cache memory is accessed in the R stage and the read data is written in the register in the W stage. When the instructions 5 and 6 are processed in parallel, the instruction 5 accesses the first cache memory in the A stage, and the instruction 6 accesses the second cache memory in the A stage. Since the instruction 5 misses the first cache memory, the second cache memory is accessed at the R stage, and the read data is written to the register at the W stage. Since the instruction 6 hits the second cache memory, the data read from the second cache memory is written to the register at the W stage. Instruction 7 and instruction 8
In parallel processing, the instruction 7 accesses the first cache memory in the A stage, and the instruction 8 accesses the second cache memory in the A stage. Instruction 7 misses the first cache memory, so the second cache memory is accessed at the R stage and the read data is
Write to register at W stage. Since the instruction 8 misses the second cache memory, the first cache memory is accessed at the R stage, and the read data is written as W
Write to register on stage. Next, the pipeline of FIG. 32 (b) will be described. In FIG. 32B, instructions 1, 3, 5, and 7 are LD2 instructions, and instructions 2, 4, 6, and
8 is an LD1 instruction. In this case, instructions 1, 3,
5, 5 and 7 access the second cache memory in the A stage, and instructions 2, 4, 6, and 8 access the first cache memory in the A stage. Other processing contents are shown in FIG.
The same as 2 (a).

The pipeline processing at the time of executing the store instruction is the same as that at the time of executing the load instruction. The cache is checked at the A stage or the R stage, and if it hits, the writing to the cache is performed at the A stage or the R stage.

As described above, when the LD1 or ST1 instruction hits the first cache memory and the LD2 or ST2 instruction hits the second cache memory, parallel processing of memory reference instructions can be performed. it can. Therefore, when accessing the data transferred to the first cache memory with the PF1 instruction, the LD1 instruction, S
L is used when accessing the data transferred to the second cache memory by using the T1 instruction and the PF2 instruction.
By using the D2 instruction and the ST2 instruction, it becomes possible to perform parallel processing of memory reference instructions, and the performance is improved.

Next, the embodiment shown in FIG. 31 will be described.
The data processing device shown in FIG. 31 includes an instruction unit 3151, a memory unit 3152 and a main memory 1703.

The instruction unit 3151 has almost the same configuration as the instruction unit described with reference to FIG. 18, but since the type of instruction to be processed is changed from FIG. 13 to FIG. 33, the configuration of the decoder and the memory interface for identifying the type of instruction. Is slightly different. The instruction unit 3151 is a bus 3210.
3212 and first through buses 3213-3215
Data is exchanged with the cache memory 3191 and the second cache memory 3190. That is, the address, data and control signals are sent to the memory unit 3152 and the main memory 1703 via the address buses 3210 and 3213, the 4-byte width write data buses 3211 and 3214, and the control signal line 3216.

The memory unit 3152 includes a first cache memory 3191 and a second cache memory 3190.
And a selector 31 for inputting / outputting data to / from these
81 to 1184 and a control unit 3192. The first cache memory 3191 and the second cache memory 3190 are direct-map type cache memories with a capacity of 512 Kbytes, a block size of 16 bytes, and are the same as the cache memories described in FIG. 11 except that they have different capacities. It has the same structure. The memory unit 3152 sends data and a wait signal to the instruction unit 3151 via the 4-byte width read data buses 3212 and 3215 and the wait signal line 3217, and transfers the transfer request signals 1723 and 1724 to the main memory 1.
703.

The main memory 1703 is a storage device for storing instructions and data, and transfers data to the first cache memory 3191 and the second cache memory 3190 via the buses 1720 and 1721. That is, the main memory 1
703 sends out data, address and response signals to the memory unit 3152 via the transfer data bus 1720, the transfer address bus 1721 and the response signal line 1722.

When the first instruction is the LD1 instruction, the instruction unit 3151 places the address of the data to be loaded on the address bus 3213, and the LD1 is sent by the control signal 3216.
Indicates that it is an instruction. Memory unit 3152
First, the selector 3181 selects the address 3213.
Is selected to read the first cache memory 3191. When the first cache memory 3191 is hit, the selector 3183 selects the first cache memory 319.
The data read from 1 is selected, and the data bus 3215 is selected.
Output to. When the first cache memory 3191 misses, a wait signal 3217 to the instruction unit 3151
Is set to 1, and the address 3213 is selected by the selector 3182 in the next cycle, and the second cache memory 3190 is selected.
Read out. When the second cache memory 3190 hits, the selector 3183 selects the data read from the second cache memory 3190, outputs the data to the data bus 3215, and sets the wait signal 3217 to 0. When the second cache memory 3190 misses,
1 for data transfer request signal 1723 to main memory 1703
To When the transfer request signal 1723 is received, the main memory 17
03 reads the data and transfers the data to the transfer data bus 172.
Then, the response signal 1722 is returned to the memory unit 3152. The memory unit 3152 writes the transferred data to the first cache memory 3191 and at the same time transfers the data to the instruction unit 3151 through the data bus 3215 and sets the wait signal 3217 to 0.

When the first instruction is the LD2 instruction, the instruction unit 3151 places the address of the data to be loaded on the address bus 3213, and the LD2 is issued by the control signal 3216.
Indicates that it is an instruction. Memory unit 3152
First, the selector 3182 selects the address 3213 and reads the second cache memory 3190. When the second cache memory 3190 hits, the selector 3183 selects the data read from the second cache memory 3190 and outputs it to the data bus 3215. When the second cache memory 3190 misses, the wait signal 3217 to the instruction unit 3151 is set to 1, and the selector 3181 selects the address 321 in the next cycle.
3 is selected and the first cache memory 3191 is read. When the first cache memory 3191 is hit, the selector 3183 selects the first cache memory 31
The data read from 91 is selected, and the data bus 321 is selected.
At the same time as outputting to 5, the wait signal 3217 is set to 0.
When the first cache memory 3191 misses, the data transfer request signal 1723 to the main memory 1703 is set to 1. Upon receiving the transfer request signal 1723, the main memory 1703
Reads the data, puts it on the transfer data bus 1720, and returns a response signal 1722 to the memory unit 3152.
The memory unit 3152 writes the transferred data to the second cache memory 3190 and at the same time transfers the data to the instruction unit 3151 through the data bus 3215 and sets the wait signal 3217 to 0.

When the first instruction is the ST1 instruction, the instruction unit 3151 transfers the write address to the address bus 3
In 213, the data to be written is placed on the data bus 3214, and the control signal 3216 is used to instruct the ST1 instruction. First, the memory unit 3152 has a selector 3
The address 3213 is selected in 181 and the first cache memory 3191 is read. First cache memory 3
When 191 hits, the selector 3181 selects the write data 3214, and the first cache memory 3
Write to 191. When the first cache memory 3191 misses, the wait signal 3 to the instruction unit 3151
217 is set to 1, the address 3213 is selected by the selector 3182 in the next cycle, and the second cache memory 31
Read 90. When the second cache memory 3190 is hit, the write data 321 is selected by the selector 3182.
4 is selected and written in the second cache memory 3190. When the second cache memory 3190 misses, the wait signal 3217 is set to 0 without transferring the data from the main memory 1703. In parallel with the above operation, the main memory 1
703 also writes the same data to the main memory.

When the first instruction is the ST2 instruction, the instruction unit 3151 transfers the write address to the address bus 3
In 213, the data to be written is placed on the data bus 3214, and the control signal 3216 indicates that the instruction is the ST2 instruction. First, the memory unit 3152 has a selector 3
At 182, the address 3213 is selected and the second cache memory 3190 is read. Second cache memory 3
When 190 is hit, the selector 3182 selects the write data 3214, and the second cache memory 3
Write to 190. When the second cache memory 3190 misses, a wait signal 3 to the instruction unit 3151
217 is set to 1, the address 3213 is selected by the selector 3181 in the next cycle, and the first cache memory 31
Read out 91. When the first cache memory 3191 is hit, the write data 321 is selected by the selector 3181.
4 is selected and written in the first cache memory 3191. When the first cache memory 3191 misses, the wait signal 3217 is set to 0 without transferring the data from the main memory 1703. In parallel with the above operation, the main memory 1
703 also writes the same data to the main memory.

When the first instruction is the PF1 instruction, the instruction unit 3151 places the address of the data to be prefetched on the address bus 3213, and the control signal 3216 is used.
Indicates that it is a PF1 command. Memory unit 315
2 is address 321 by selectors 3181 and 3182
3 is selected and the first cache memory 3191 and the second cache memory 3190 are read simultaneously. The first cache memory 3191 or the second cache memory 3
When 190 is hit, the process ends without transferring the data from the main memory. When both the first cache memory 3191 and the second cache memory 3190 miss, the data transfer request signal 1723 to the main memory 1703 is set to 1. Upon receiving the transfer request signal 1723, the main memory 1703 reads the data, places it on the transfer data bus 1720, and returns a response signal 1722 to the memory unit 3152. The memory unit 3152 writes the transferred data in the first cache memory 3191. The processing when the first instruction is the PF2 instruction is almost the same, except that the data transferred from the main memory 1703 is written in the second cache memory 3190.

The processing of the second instruction is similar, and data is exchanged using the address bus 3210, the read data bus 3212, and the write data bus 3211.

[0159]

According to the present invention, a computer having a prefetch function for a cache memory is used in a small-to-medium-sized program that reuses data stored in the cache memory and a large-scale computer that does not reuse data stored in the cache. There is an effect that the performance can be improved inexpensively for both of the scale programs.

[Brief description of drawings]

FIG. 1 is an overall view of an embodiment of the present invention.

FIG. 2 is a first configuration example of the memory unit 202 of FIG.

FIG. 3 is a configuration example of an instruction unit 201 in FIG.

FIG. 4 is a diagram illustrating a pipeline.

5 is a configuration example of a prefetch queue 102 in FIG.

6 is a configuration example of a cell 502 in FIG.

7 is a configuration example of a priority circuit 500 of FIG.

8 is a configuration example of a determination circuit 501 in FIG.

9 is a configuration example of the second cache memory 100 of FIG.

10 is a configuration example of a cell 901 in FIG.

11 is a configuration example of the first cache memory 101 of FIG.

FIG. 12 is a diagram illustrating an instruction format.

FIG. 13 is a diagram illustrating types of instructions.

14 is a configuration example of a control circuit 103 in FIG.

FIG. 15 is a second configuration example of the memory unit 202 in FIG.

FIG. 16 is an overall view of a second embodiment of the present invention.

17 is a configuration example of the memory unit 1702 of FIG.

18 is an exemplary configuration of an instruction unit 1701 shown in FIG.

19 is a diagram illustrating a pipeline when an instruction is executed by the data processing device of FIG.

20 is a configuration example of the second cache memory 1690 of FIG.

FIG. 21 is a configuration example of the cell 2001 of FIG. 20.

22 is a configuration example of the control circuit 1603 in FIG.

FIG. 23 is a second of the first cache memory 101 of FIG.
Configuration example.

FIG. 24 is a second of the second cache memory 100 of FIG.
Configuration example.

FIG. 25 is an overall view of a third embodiment of the present invention.

FIG. 26 is a configuration example of the memory unit 2602 of FIG. 25.

FIG. 27 is a diagram illustrating a pipeline when an instruction is executed by the data processing device of FIG. 25.

28 is a configuration example of the second cache memory 2590 of FIG.

FIG. 29 is a configuration example of the cell 2801 in FIG. 28.

30 is a configuration example of the control circuit 2503 in FIG.

FIG. 31 is an overall view of a fourth embodiment of the present invention.

32 is a diagram illustrating a pipeline when an instruction is executed by the data processing device of FIG. 31.

FIG. 33 is a diagram for explaining the types of instructions processed by the data processing device of FIG. 31.

FIG. 34 is an overall view of a data processing device of the present invention.

[Explanation of symbols]

Reference numeral 100 ... Second cache memory, 101 ... First cache memory, 201 ... Instruction unit, 203 ... Main memory, 1600 ... Control unit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeya Tanaka 7-1-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Hideo Sawamoto 1 Horiyamashita, Hadano City, Kanagawa Stock Company Hitachi Co., Ltd. General-purpose computer division (72) Inventor Akira Okuno 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Co., Ltd. Hitachi Research Laboratory (56) Reference JP-A-5-143451 (JP, A) JP 54-9535 (JP, A) JP 4-270431 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08

Claims (15)

(57) [Claims] 1. A data processing unit that executes instructions and processes data, a plurality of cache memories that hold data prefetched from a memory, and a cache memory that prefetches is specified from among the plurality of cache memories to specify data. the prefetch instruction prefetching, have a control unit for prefetching data into the cache memory that is specified from the memory, the control unit during the execution of the prefetch instruction, the
The data processing unit is used for any of the plurality of cache memories.
If the data to be processed by is not stored in the above memory
A data processing device that outputs a transfer request signal to . 2. The control unit according to claim 1, wherein the control unit transfers data from the specific cache memory to the data processing unit by a plurality of load instructions, and the prefetch instruction transfers data from the memory to a predetermined cache memory. A data processing device characterized by prefetching. In any one of the claims 3] according to claim 1 or 2, a plurality of cache memory of one port in mass 1
And a small-capacity two-port second cache memory, the control unit stores frequently accessed data in the first cache memory and infrequently accessed data is stored in the second cache memory. A data processing device characterized by storing in a cache memory. 4. The machine according to claim 3, wherein the second cache memory performs a data transfer process from a main memory and a data reference process in the second cache memory instructed by the instruction processing unit on one machine. A data processing device characterized by being executed in a cycle. 5. The prefetch queue according to claim 3 , wherein the controller holds at least one address of data being transferred from the main memory,
A data processing device comprising: a control processing unit that controls access of data to the first or second cache memory based on the held address. 6. The prefetch queue according to claim 5, wherein the prefetch queue holds write information for instructing whether to write prefetched data in the first cache memory or the second cache memory. And data processing device. 7. A cache memory unit comprising a plurality of cache memories between a main memory for storing data or instructions and an instruction processing unit for processing the data based on the instructions, the cache memory unit comprising: The control unit has a control unit controlled by a prefetch instruction that stores the data transferred from the main memory by designating one of the cache memories, and the control unit stores the plurality of caches in order to store the data. Controls memory and prefetches
Any of the above cache memories while executing the instruction
Also stores the data to be processed by the data processing unit.
A data processing device, which outputs a transfer request signal to the memory when there is no data. 8. The cache memory unit according to claim 7, wherein the cache memory unit has a first cache memory and a second cache memory, and the number of ports of the second cache memory is the same as that of the first cache memory. A data processing device characterized by having more ports. 9. The cache memory unit according to any one of claims 7 to 8, wherein the cache memory unit includes a first cache memory and a second cache memory. A data processing device, wherein the capacity of the cache memory is larger than the capacity of the second cache memory. 10. The data in the second cache memory according to any one of claims 7 to 9 , wherein the second cache memory is a data in the second cache memory of a first memory reference instruction instructed by the instruction processing unit. A data processing device, wherein a reference process and a data write process in a second cache memory of a second memory reference instruction instructed by the instruction processing unit are executed within one machine cycle. 11. The cache memory unit according to claim 7 , further comprising a data bus for transferring data from the first cache memory to the second cache memory. Data processing device. 12. The prefetch queue according to claim 7 , wherein the controller holds at least one address of data being transferred from the main memory,
And a control processing unit that controls access to data to the plurality of cache memories based on the held address. 13. The data processing device according to claim 12, wherein the prefetch queue holds write information that indicates to which of the plurality of cache memories the prefetched data is written. 14. The cache memory unit according to any one of claims 7 to 12 , wherein the cache memory unit has a first cache memory and a second cache memory, and the cache memory unit is the instruction processing unit. Data reference processing in the first cache memory of a first memory reference instruction instructed by the following, and data reference processing in the second cache memory of a second memory reference instruction instructed by the instruction processing unit A data processing device, characterized in that and are executed within one machine cycle. 15. Any one of claims 7 to 12 and 14.
In the paragraph, the cache memory unit has a control unit controlled by a memory reference instruction designating that data is likely to exist in one of the plurality of cache memories, and the control unit is the memory unit. A data processing device characterized by controlling the plurality of cache memories for processing a reference instruction.