JP3464872B2 - Monitoring and control system for units to be separated - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention monitors a unit in which a plurality of processing packages for executing various processes are loaded and a unit in which a main monitoring control package for monitoring and controlling these processing units is loaded. Control system

[0002]

2. Description of the Related Art As a transmission device that separates / multiplexes signals on a transmission line, there is a device that is separated into a unit that executes various processes and a unit that monitors and controls this unit. These units are connected by a unit connection cable.

A unit for executing various processes has a plurality of slots, and each slot is loaded with a printed circuit board (hereinafter referred to as a process package) mounted with a package for performing a process according to the purpose. Each processing package is, for example, a transmission package that transmits 10 Gb / s data, a reception package that receives 10 Gb / s data,
The packages are classified according to transmission speed, such as a package that transmits 1.2 Gb / s data or a package that receives 1.2 Gb / s data.

The unit for monitoring and controlling the unit loaded with the processing package has a slot for loading a printed circuit board (hereinafter referred to as a main monitoring control package) on which a package for monitoring and controlling the processing package is mounted.

Further, the unit for loading the processing package has a slot for loading the unit monitoring control package in which a package for transferring signals between the main monitoring control package and each processing unit is mounted.

Two serial signal lines are connected to the unit supervisory control package. One of the two signal lines is a command signal line for transmitting a command CMD transmitted from the unit monitoring control package to the processing package, and a plurality of processing packages are provided in this command signal line. It is connected. in this case,
The command CMD from the unit supervisory control package is
It is distributed to all processing packages via the command signal line. The other signal line of the two signal lines is a response signal line for transmitting a response ST transmitted from the processing package to the unit monitoring control package, and the response signal line has a plurality of processing lines. Unit is connected.

The command CMD and the response ST transmitted and received between the main supervisory control package and the processing package are signals having a data length of 64 bits, and the first 2 bytes of this signal are the address indicating the destination. And a control code indicating the type of instruction are stored. In addition, a CRC check code calculated by CRC is stored in the last 1 byte of the above signal. Further, in the above signal, a 5-byte (40-bit) area between the control code and the CRC check code is a data field for storing command data and response data.

The main supervisory control package sends a command CMD addressed to the processing package to the unit supervisory control package via an inter-unit connection cable, and
A CMD / ST transmission / reception unit that receives a response ST transmitted from each processing package via the unit monitoring control package, and a CPU that generates a command CMD or analyzes the response ST are provided. The CPU generates a command CMD addressed to each processing package, and transmits the generated command CMD from the CMD / ST transmission / reception unit to the unit monitoring control package. Also, the CPU is CMD / ST
The response ST received by the transmitter / receiver is analyzed.

The unit supervisory control package temporarily stores the command CMD from the main supervisory control package, then temporarily stores the command buffer to be output to the signal line for the command, and the response ST from the processing package, and then inter-units. A response buffer for outputting the connection cable 2 is provided.

Each processing package receives the command CMD from the unit monitoring control package and inputs it to the device in the package, and at the same time, sends the response ST from the device in the package to the unit monitoring control package via the signal line for response. A CMD / ST transmitting / receiving unit for transmitting to

When transmitting a command from the main supervisory control package to the processing package, the CPU of the main supervisory control package generates instruction data addressed to a certain processing command, and in this instruction data, the address of the destination processing package is generated. Command C with control code indicating the type of command CMD and CRC check code added
Generate MD. The generated command CMD is CMD
/ ST Transmitted from the transceiver unit to the unit monitoring control package via the unit connection cable.

The command buffer of the unit supervisory control package temporarily stores the command CMD from the main supervisory control package, and then outputs it to the signal line for command transmission.

The command CMD output to the signal line for command transmission is distributed to all processing packages. When the CMD / ST transceiver of each processing package receives the command CMD from the unit monitoring control package,
By referring to the address of the command CMD, it is determined whether or not the command CMD is addressed to itself. Where CMD / S
When the T transmitter / receiver unit determines that the received command CMD is the command CMD addressed to itself, the T transmitter / receiver unit
D is converted from the serial signal format to the parallel signal format and input to the device in the package. The device in the package takes out the instruction data stored in the data field of the command CMD and executes the processing according to the instruction data. When the device finishes the processing in accordance with the instruction data, the result of the termination is used as response data,
Generate the response ST. Specifically, the device adds the address and control code added to the command CMD and the newly generated CRC check code to the response data to generate the response ST. Generated response ST
Is converted from the parallel signal format to the serial signal format by the CMD / ST transmission / reception unit, and then transmitted to the unit monitoring control package via the ST signal line.

Upon receiving the response ST from the processing package, the unit monitoring control package temporarily stores it in the response buffer and then outputs it to the unit connecting cable. The response ST output to the unit connection cable is
It is sent to the main supervisory control package via the unit connection cable.

CMD / ST of main supervisory control package
The transmitter / receiver receives the response S from the unit monitoring control package.
When T is received, the received response ST is input to the CPU. The CPU analyzes the input response ST to determine the processing result of the command CMD, the operating state of the processing package, the normality of the processing package, and the like.

[0016]

By the way, when the above-mentioned monitoring control by serial communication is performed, the following problems occur.

When the command CMD is transmitted from the unit monitoring control package, this command CMD is distributed to all the processing packages, so that a certain processing package malfunctions and a response ST to the command CMD addressed to another processing package is transmitted. Then, in the response signal line, the response ST transmitted from the processing package of the destination of the command CMD collides with the response ST transmitted from the malfunctioning processing package, and the response ST is transmitted to the unit monitoring control package and the main monitoring control package. Is not sent.

When a command CMD is sent to a slot in which a processing package is not loaded, or a processing package which cannot respond due to a power failure or the like, the main monitoring control package sends the command C
It cannot be determined that the processing package of the MD destination is not loaded in the slot, or that the processing package of the command CMD destination has a power failure,
Wait for a response from the processing package. The main supervisory control package waiting for a response from the processing package must suspend its operation, which causes a problem that the performance of the entire apparatus is deteriorated.

Further, as the number of processing packages increases,
There is a problem that the burden on the main supervisory control package is heavy and high-speed processing becomes difficult. Therefore, the present invention is
In view of the above problems, a technique capable of reliably transmitting a response from a processing package, which is a destination of a command, to the main monitoring control package, a technique for determining whether each slot is loaded or unloaded, It is an object of the present invention to provide a technique for preventing processing delay even when the processing package is loaded, to reduce the load on the main monitoring and control package and to speed up the processing.

[0020]

The present invention adopts the following means in order to solve the above problems. That is,
A supervisory control system for a separation unit, comprising a first unit loaded with a plurality of treatment packages and a second unit loaded with a main supervisory control package for controlling the treatment packages loaded in the first unit. In addition, the main monitoring control package has a destination discriminating means for discriminating a processing package as a destination of a command sent to the processing package, and an information storage area corresponding to each of the plurality of processing packages. Response storing means for storing a response to the command in the information storing area corresponding to the processing package, and in the information storing area corresponding to the processing package of the destination discriminated by the destination discriminating means among the response storing means. The information selection means for reading the response that has been read, and the information selection means. The read response and wherein the loading unit monitoring control package and a response transmitting means for transmitting to the main monitor and control package of the second unit to the first unit.

In addition to the above configuration, the unit monitoring control package may include a loading information discriminating means for discriminating the processing package loaded in the first unit. In this case, the response transmission means determines that the destination of the command is the unit monitoring by the destination determination means.
When it is determined that the package is a control package , information for identifying the processing package determined to be loaded in the first unit by the loading information determination means is transmitted to the main monitoring control package. Good.

Further, the unit monitoring control package is
A loading information determination unit that determines the processing package loaded in the first unit may be further provided. In this case, the response transmission means, if the response from the processing package is not sent within a predetermined time from the time when the command from the main monitoring control package is sent to the processing package, the loading information determination means. By first
The information for identifying the processing package determined to be loaded in the unit may be transmitted to the main monitoring control package.

Further, the unit monitoring package includes command creating means for creating a command addressed to the processing package, and command sending means for sending the command created by the command creating means to the processing package.
A response receiving means for receiving a response from the processing package to the command transmitted by the command transmitting means, and a response received by the response receiving means,
Information storage means for storing together with the information for identifying the processing package, and when receiving a command from the main monitoring control package, searching the information storage means,
A response reading unit for reading a response from the processing package of the command destination may be further provided.
In this case, the response transmitting means may transmit the response read by the response reading means to the main monitoring control package. As a result, the unit supervisory control package can collect information regarding the processing package in advance, and can return the gathered information when the command from the main supervisory control package is received. That is, the main monitoring control package does not need to send a command to the processing package to collect information.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a schematic configuration of a transmission device to which a supervisory control system for separating units according to the present invention is applied. This transmission device includes a unit A including a common slot and a unit B including n + 1 slots (1) to (n + 1). Unit A and Unit B
And are connected by an inter-unit connection cable.

The common slot of the unit A is loaded with the printed circuit board on which the main monitoring and control package 1 is mounted.
Of the n + 1 slots (1) to (n + 1) of the unit B, the highest slot (1) is loaded with the printed circuit board on which the unit monitoring package 2 is mounted. Unit B
Among the n + 1 slots (1) to (n + 1) of n, the n slots from the second highest slot (2) to the lowest slot (n + 1) are processing packages (1) to (n). Load the printed circuit board on which is mounted.

FIG. 2 is a block diagram for explaining the configurations of the units A and B. The unit A is connected to the unit B by the inter-unit connection cable 4 as described above. A connector 6 is provided at a connection portion between the unit A and the inter-unit connection cable 4. Four signal lines L1 to L4 are connected to the terminal of the connector 6 on the unit A side. These four signal lines are bundled in the connector 6 and connected to the inter-unit connection cable 4. Here, the inter-unit connection cable 4 is assumed to be composed of four signal lines. Each of these four signal lines is connected to one of the above signal lines L1 to L4 via the connector 6 in a one-to-one relationship.

Of the above four signal lines L1 to L4, the signal lines L1 and L3 are connected to the CMD transmission section 11 mounted on the main monitoring and control package 1. 4 above
The signal line L2 of the book signal lines L1 to L4 is connected to the ST receiving unit 12 mounted in the main monitoring control package 1.

The signal line L4 of the above-mentioned four signal lines L1 to L4 is connected to the I / O register 14 mounted on the main monitoring and control package 1. Then, in the middle of the signal line L4 connecting the connector 6 and the I / O register 14, a pull-up resistor R and a positive power source (5V) are provided.
And are connected. Further, the signal line L4 is terminated at the ground level of the unit B via the inter-unit cable 4. In this case, if the unit A and the unit B are connected by the inter-unit connection cable 4, the electric signal (Low signal) indicating the ground level of the unit B is I / O via the inter-unit connection cable 4 and the signal line L4.
It is input to the O register 14. If the unit A and the unit B are not connected by the inter-unit connection cable 4, the positive power source (5
The electric signal (Hi signal) from V) is input to the I / O register 14 via the signal line L4.

The CMD transmission unit 11 of the main supervisory control package 1 is connected to the above-mentioned signal lines L1 and L3, and is also a CP mounted on the main supervisory control package 1.
It is connected to U10 and the clock 13. This CMD
The transmitter 11 outputs the clock signal CLK output from the clock 13 to the signal line L3, and at the same time, CP
The command CMD generated by U10 is output to the signal line L1. The clock signal CLK and the command CMD output from the CMD transmission unit 11 are sent to the inter-unit connection cable 4 by the signal lines L3 and L1 and further sent to the unit B by the inter-unit connection cable 4.

The ST receiver 12 of the main supervisory control package 1 is connected to the above-mentioned signal line L2, and
It is connected to the CPU 10. This ST receiver 12
Unit B to unit connection cable 4 and signal line L
The response ST sent via 2 is received, and the received response ST is input to the CPU 10.

The I / O register 14 of the main supervisory control package 1 is connected to the signal line L4 and also to the CPU 10. This I / O register 14 is a Low level signal from the unit B via the signal line L4.
The signal or the Hi signal 6 from the positive power source (5V) is input. Then, the I / O register 14 holds the input electric signal (Hi signal or Low signal), and the CPU
The electric signal held when the request from 10 is received is output. The electric signal output from the I / O register 14 is input to the CPU 10.

Next, the structure of the unit B will be described.
The unit B is connected to the inter-unit connection cable 4 via the connector 7. Four signal lines L1 'to L4' are connected to the terminal of the connector 7 on the unit B side. Each of these four signal lines L1 ′ to L4 ′ is connected to the unit A via the inter-unit connection cable 4.
Are connected to the four signal lines L1 to L4. For example, the signal line L1 ′ is connected to the signal line L1 of the unit A via the inter-unit connection cable 4. The signal line L2 ′ is connected to the signal line L2 of the unit A via the inter-unit connection cable 4. Further, the signal line L3 ′ is connected to the signal line L3 of the unit A via the inter-unit connection cable 4. Furthermore, the signal line L4 ′ is connected to the signal line L4 of the unit A via the inter-unit connection cable 4.

The signal lines L1 ', L2' and CL3 'of the above four signal lines L1'-L4' are connected to the unit monitoring control package 2 loaded in the slot (1) of the unit B. Has been done. In addition, the signal line L4 ′ of the above four signal lines L1 ′ to L4 ′ is connected to the ground level of the unit B as described above.

The unit monitoring control package 2 of the unit B is connected to one CMD transmission line T and n ST transmission lines S1 to Sn wired on the backboard of the unit B.

The CMD transmission line T is branched into n transmission lines on the backboard of the unit B, and these branched transmission lines are slots (2) to (n + 1) of the unit B.
Connected to the processing packages (1) to (n) loaded in the. This CMD transmission line T outputs the signal output from the unit monitoring control package to n processing packages (1).
~ (N).

The ST transmission lines S1 to Sn have the processing units (1) to (n) loaded in the slots (2) to (n + 1) of the unit B and the unit monitoring control package 2 one to one. Connecting. For example, in the example of FIG.
The T transmission line S1 is connected to the processing package (1), and ST
The transmission line Sn is connected to the processing package (n). Each of the ST transmission lines S1 to Sn has processing packages (1) to
It is a cable for transmitting the signal from (n) to the unit monitoring control package 2.

The CMD transmission line T and the ST transmission line S1 are connected to the processing package (1) loaded in the slot (2) of the unit B. Here, the ST transmission line S1
Is composed of three signal lines L7, L8, L9, and the CMD transmission line T is composed of two signal lines L5, L6.

The signal lines L7 and L8 of the three signal lines constituting the ST transmission line S1 are connected to the ST transmission unit 32 mounted in the processing package (1). Also, ST
The signal line L8 among the three signal lines that form the transmission line S1
Are connected to the ground level of the processing package (1).

The signal lines L5 and L6 of the two signal lines constituting the CMD transmission line T are connected to the CMD receiving unit 33 mounted on the processing package (1). CMD receiver 3 mounted on processing package (1)
3 is connected to the above-mentioned two signal lines L5 and L6, and is also connected to the device 34 mounted in the processing package (1). The CMD receiving unit 33 sends a command CMD sent from the unit monitoring control package 2 via the CMD transmission line T and the signal line L5, and a command CMD sent from the unit monitoring control package 2 to the CMD transmission line T and the signal line L6. The received clock signal CLK is received, and the command CMD and the clock signal CLK are input to the device 34 in the processing package (1).

ST transmitter 32 of processing package (1)
Is the signal L7 of the above-mentioned three signal lines L7 to L9,
Processing package (1) while being connected to L9
Is connected to the device 34 inside. This ST transmitter 3
2 inputs the response data and PUALM information from the device 34 to the command CMD. Then, the ST transmission unit 32 sends the response data from the device 34 to the signal line L.
7, and the PUALM information from the device 34 is output to the signal line L9. The response data output to the signal line L7 and the PUALM information output to the signal line L9 are sent to the unit monitoring control package 2 via these signal lines L7 and L9 and the ST transmission line S1. The above PUALM information is Low when the power supply of the processing package (1) is normal.
It becomes a signal indicating the level, and becomes a signal indicating the Hi level when the power supply of the processing package (1) is abnormal.

Slots (3) to (n + 1) of unit B
The configuration of the processing packages (2) to (n) loaded in the
It is similar to the above processing package (1). Next, the configuration of the unit monitoring control package 3 will be described with reference to FIG. Unit monitoring control package 3 is CM
D buffer 22, CLK buffer 23, address latch circuit 24, ST selector 25, ST buffer 26, command shift circuit 27, ST creation circuit 28, mounting information selector 29, mounting information buffer 200, PUALM selector 210, and PUALM buffer 220. Has been implemented.

Further, the unit monitoring control package 3 is connected with three signal lines L1 'to L3' connected to the inter-unit connection cable 4 and one C line.
The MD transmission line T and the n ST transmission lines S1 to Sn are connected.

As described above, the CMD transmission line T is composed of the two signal lines L5 and L6, and the signal line L5 of the two signal lines L5 and L6 is the unit monitoring control package. It is connected to the CMD buffer 22 mounted on the No. 2. The signal line L6 of the two signal lines L5 and L6 forming the CMD transmission line T is connected to the CLK buffer 23 mounted in the unit monitoring control package 2.

In addition, the above-mentioned n ST transmission lines S1 to Sn
As described above, each of the three signal lines L7, L
8 and L9, and these three signal lines L
The signal line L7 of 7, L8, and L9 is connected to the ST buffer 26 mounted in the unit monitoring control package 2, and the signal line L8 is connected to the mounting information buffer 200 mounted in the unit monitoring control package 2. Line L9
Is a PUAL installed in the unit monitoring control package 2
It is connected to the M buffer 220. Further, a positive power supply (5V) is connected to the middle of the signal line L8 via pull-up resistors R1 to Rn.

As described above, the CMD buffer 22 mounted on the unit monitor control package 2 has the signal line L5.
And the signal line L1 ′ are connected. The CMD buffer 22 receives the command CMD from the main monitoring and control package 1 and the unit connecting cable 4 and the signal line L1 ′.
To enter via. Then, the CMD buffer 22 temporarily stores the input command CMD and then stores the command CMD in the signal line L5.
Output to. Command CMD output to signal line L5
Are distributed to n processing packages (1) to (n) via the signal line L5 and the CMD transmission line T.

In the CLK buffer 23, as described above,
The signal line L3 'and the signal line L6 are connected. This C
The LK buffer 23 inputs the clock signal CLK from the main monitoring and control package 1 via the inter-unit connection cable 4 and the signal line L3 ′. Then, the CLK buffer 23 temporarily stores the input clock signal CLK and then outputs it to the signal line L6. The command CMD output to the signal line L6 is distributed to the n processing packages (1) to (n) via the signal line L6 and the CMD transmission line T.

In the ST buffer 26, as described above, n
The signal line L7 of the book is connected. This ST buffer 2
Although not shown in FIG. 6, n memory elements (1) to
(N), and each of the n memory elements (1) to (n) has the above-mentioned n signal lines L.
One of the seven is connected. In this case, the memory device (n) is connected to the one processing package (n) in a one-to-one correspondence via the signal line L7 and the ST transmission line Sn.

Further, the processing elements (1) to (n) of the ST buffer 26 are connected to the memory elements (1) to (n) via the signal line L7 and the ST transmission lines S1 to Sn.
An address associated with the address assigned to (n) is assigned. For example, processing package (1)
An address (1) is assigned to the memory device (1) connected to the memory device, and an address (n) is assigned to the memory device (n) connected to the processing package (n).

The memory elements (1) to (n) of the ST buffer 26 are the signal line L7 and the ST transmission lines S1 to S.
The response data from the processing packages (1) to (n) connected via n is stored. This response data is data indicating a response to the command CMD sent from the aforementioned CMD buffer to the processing packages (1) to (n).

Further, the mounting information buffer 200 mounted on the unit monitoring control package 2 has, as described above,
The n signal lines L8 are connected. The mounting information buffer 200 is composed of n memory elements (1) to (n) similarly to the ST buffer 26 described above, and each of the n memory elements (1) to (n) includes , One of the above n signal lines L8 is connected. In this case, the memory element (n) is connected to the one processing package (n) in a one-to-one correspondence via the signal line L8 and the ST transmission line Sn.

Further, each of the memory elements (1) to (n) of the mounting buffer 200 has the same signal line L8 and ST transmission lines S1 to Sn as the memory element of the ST buffer 26.
The addresses associated with the addresses assigned to the processing packages (1) to (n) connected via the are assigned. For example, the memory device (1) connected to the processing package (1) is assigned the address (1), and the memory device (n) connected to the processing package (n) is assigned the address (n).

Each of the n memory elements (1) to (n) forming the above mounting information buffer 200 is connected to the processing packages (1) to (n) through the signal line L8 and the ST transmission lines S1 to Sn. The mounting information of (n) is stored. This mounting information indicates whether the unit monitoring control package 2 and the processing packages (1) to (n) are connected by the ST transmission lines S1 to Sn, that is, the processing packages (1) to (n) are the units B. Slots (2) to (n +
It is information indicating whether or not it is loaded in 1). For example, if the unit monitoring control package 2 and the processing package (n) are connected by the ST transmission line Sn,
The signal line L8 connected to the memory element (n) of the mounting information buffer 200 is connected to the ground level of the processing package (n) via the ST transmission line Sn. In this case, an electric signal (Low signal) indicating the ground level of the processing package (n) is input to the memory element (n) of the mounting information buffer 200. If the unit monitoring control package 2 and the processing package (n) are not connected by the ST transmission line Sn, that is, if the processing package (n) is not loaded in the slot (n + 1) of the unit B, the mounting information is set. The signal line L8 connected to the memory element (n) of the buffer 200 is terminated by the positive power supply (5V) provided on the way. In this case, in the memory element (n) of the mounting information buffer 200,
An electric signal (Hi signal) from the positive power source (5V) is input.

As described above, the n signal lines L9 are connected to the PUALM buffer 220 mounted in the unit monitor control package 2. This PUALM buffer 22
0 is composed of n memory elements (1) to (n) like the ST buffer 26 described above, and each of the n memory elements (1) to (n) has the above-mentioned n. One of the signal lines L9 is connected. In this case, the memory device (n) is connected to the one processing package (n) in a one-to-one correspondence via the signal line L9 and the ST transmission line Sn.
Further, each of the n memory devices (1) to (n) forming the PUALM buffer 220 is connected to the address of the processing package (1) to (n) via the signal line L9 and the ST transmission line Sn. The address associated with is assigned.

The n memory elements (1) to (n) forming the PUALM buffer 220 are connected to the processing packages (1) to (n) via the signal line L9 and the ST transmission lines S1 to Sn. Store the PUALM information from. This PUALM information is used for each processing package (1) to (n).
Is information indicating whether the power source of is normal or abnormal.

The address latch circuit 24 mounted on the unit monitoring control package 2 has signal lines L1 'and L3'.
Are connected. The address latch circuit 24 operates according to the clock signal CLK sent from the main monitoring control package 1 via the inter-unit connection cable 4 and the signal line L3 '. Then, the address latch circuit 24 inputs the command CMD sent from the main monitoring control package 1 through the inter-unit connection cable 4 and the signal line L1 ′, reads the destination address of the command CMD, and outputs it.

FIG. 4 is a diagram showing the internal structure of the address latch circuit 24 described above. As shown in FIG. 4, the address latch circuit 24 includes a serial / parallel conversion circuit (S / P) 24a and a flip-flop (FF) 24.
b, a latch timing generation counter 24c.

A signal line L1 'and a signal line L3' are connected to the S / P 24a. And S / P 24a
Operates according to the clock signal CLK sent from the main monitoring and control package 1 via the unit connecting cable 4 and the signal line L3 ′, and from the main monitoring and controlling package 1 via the unit connecting cable 4 and the signal line L1 ′. Command CM in serial data format
Convert D to 1 byte (8 bits) parallel data format. The command CMD converted into the parallel data format by the S / P 24a is input to the FF 24a via eight signal lines connecting the S / P 24a and the flip-flop (FF) 24b.

A signal line branched from the signal line L1 ′ connected to the S / P 24a and a signal line branched from the signal line L3 ′ are connected to the latch timing generation counter 24c, and the main monitoring control package 1 is connected. Command CMD and clock signal CLK sent from S / P2
4a is input at the same time. Then, the latch timing generation counter 24 c operates in accordance with the clock signal CLK from the main supervisory control package 1, and outputs the command CMD from the main supervisory control package 1.
The position of the bit indicating the destination address of the command CMD is detected from the (serial data). Further, the latch timing generation counter 24c displays the command CMD.
F when the bit position indicating the destination address of
A timing pulse is output to F24b.

The FF 24b receives the timing pulse from the latch timing generation counter 24c,
The output (parallel data) from the S / P 24a at that time is captured and input to the ST selector 25. For example, the command CMD and the response S according to the present embodiment
As shown in FIG. 5, T is a 1-bit head flag indicating the head of the command CMD or the response ST, a 2-bit head flag, a 6-bit destination address, a 1-byte birth code, and a 5-byte head code. 64 consisting of command data or response data and 1-byte CRC check code
It is bit data. In this case, the latch timing generation counter 4, as shown in FIG. 6, is triggered by the input of the head flag of the command CMD to start counting the number of bits of the command CMD. Then, the latch timing generation counter 4 outputs a timing pulse when the eighth bit from the head bit of the command CMD, that is, the last bit (PA0 in the figure) of the destination address is counted. At this time, the parallel data output from the S / P 24a includes 8 bits including a 6-bit destination address.
It is bit parallel data. This 8-bit parallel data is taken into the FF 24b to which the timing pulse from the latch timing generation counter 4 is input, and only 6 bits indicating the destination address of the command CMD are FF.
It is output from 24b. The 6-bit address output from the FF 24b is input to the ST selector 25, the mounting information selector 29, and the PUALM selector 210 mounted in the unit monitoring control package 2.

Now, returning to FIG. 2, the ST selector 25 mounted on the unit monitoring control package 2 is connected to each of the n memory elements of the ST buffer 26 via a signal line. At the connecting portion between these signal lines and the ST selector 25, n connecting terminals (1) (not shown) are provided.
(N) are provided. The same address as that of the memory elements (1) to (n) of the ST buffer 26 connected via the signal line is assigned to each of these n connection terminals (1) to (n). As a result, the address of the connection terminal (n) of the ST selector corresponds to the address of the processing element (n) connected via the memory device (n) of the ST buffer 26, the signal line L7, and the ST transmission line Sn. Will be attached.

However, the connection terminal (1) of the ST selector 25
~ (N) and processing packages (1) to (n) are associated with each other, processing package (1)
It is necessary to sufficiently consider the addresses assigned to (n) when designing the transmission device. If processing package (1)
If the addresses assigned to (n) to (n) are not sufficiently considered, the address (1) is assigned to the processing package (1) and the address (3) is assigned to the processing package (2) as shown in (a) of FIG. ) May be added. At this time, the processing package (1) is connected to the connection terminal (1) of the ST selector, the processing package (2) is connected to the connection terminal (3), and any processing is performed on the connection terminal (2). The package will not be connected either. Further, in the example shown in FIG. 7A, since the address (5) is assigned to the processing package (3) and the address (9) is assigned to the processing package (4), the addresses (6), ( No processing package is connected to the three connection terminals (6), (7) and (8) to which 7) and (8) are assigned. In this way, if the addresses assigned to the processing packages (1) to (n) are not considered, the number of the processing packages (1) to (n) is 2
It is necessary to provide more than twice the number of connection terminals in the ST selector, which unnecessarily increases the circuit scale of the ST selector.

Therefore, in the transmission device according to the present embodiment, as shown in FIG. 7B, the processing package (1)
Consecutive hexadecimal values are assigned as addresses (n) to (n). In this case, the number of connection terminals of the ST selector 25 is the same as the number of the processing packages (1) to (n), and the circuit scale of the ST selector 25 is reduced. ST selector 25 configured as described above
Is a command C by the address latch circuit 24 described above.
Input the address read from the MD. And S
The T-selector 25 discriminates the connection terminal (n) to which the address corresponding to the input address is assigned, and the memory element (n) of the ST buffer 25 connected to the discriminated connection terminal (n) via a signal line. To access the response data stored in the memory element (n).

The mounting information selector 29 mounted on the unit monitoring control package 2 is the mounting information buffer 2 described above.
00 is connected to each of the n memory elements (1) to (n) that make up 00 through a signal line. At the connection portion between these signal lines and the mounting information selector 29, n connection terminals (1) to (n) are provided. Each of the n connection terminals (1) to (n) is connected to the memory element (1) to the mounting buffer 200 via the signal line.
The same address as (n) is assigned. As a result,
The address of the connection terminal (n) of the mounting information selector 29 is
The memory element (n) of the mounting buffer 200, the signal line L8,
Also, it is associated with the address of the processing package (n) connected via the ST transmission line Sn.

The mounting information selector 29 having the above-described structure is controlled by the address latch circuit 24 to generate a command CM.
Input the address read from D. Then, the mounting information selector 29 determines a connection terminal (n) to which an address corresponding to the input address is assigned, and the memory element of the mounting information buffer 200 connected to the connection terminal (n) via a signal line. (N) is accessed to read the mounting information (Hi signal or Low signal) stored in the memory element.

The PUALM selector 210 installed in the unit monitoring control package 2 is the PUALM buffer 2
It is connected to each of the n memory elements (1) to (n) forming 20 via a signal line. These signal lines and P
The connection portion with the UALM selector 210 is provided with n connection terminals (1) to (n). The same addresses as those of the memory elements (1) to (n) of the PUALM buffer 220 connected via the above-mentioned signal line are assigned to these n connection terminals (1) to (n), respectively.
As a result, the connection terminal (n) of the PUALM selector 210
Will be associated with the address of the processing element (n) connected via the memory element (n) of the PUALM buffer 220, the signal line L8, and the ST transmission line Sn.

The PUALM selector 210 configured as described above inputs the address read from the command CMD by the address latch circuit 24. And
The PUALM selector 210 determines the connection terminal (n) to which the address corresponding to the input address is assigned, and connects to the connection terminal (n) via a signal line.
The memory element (n) of the UALM buffer 220 is accessed, and the PUAL stored in the memory element (n) is accessed.
Read M information.

A signal line L1 'is connected to the command shift circuit 27 mounted on the unit supervisory control package 2, and a command CMD sent from the main supervisory control package 1 via the signal line L1'. Is input, the command CMD is output after being held for a certain period of time. Processing package (1) ~
It may be set for each (n). In that case,
The time from the time when the command CMD is sent to each processing package (1) to (n) to the time when the response data is sent, that is, the time required for each processing package (1) to (n) to respond normally. Is measured and the time is set as a fixed time for each of the processing packages (1) to (n).

A signal line L2 'is connected to the ST creation circuit 28. Further, the ST creation circuit 28 is connected to each of the ST selector 25, the mounting information selector 29, the PUALM selector 210, and the command shift circuit 27 via a signal line. This ST creation circuit 28
Is response data output from the ST selector 25, mounting information read from the mounting information selector 29, PUAL
This is a circuit that uses the PUALM information output from the M selector 210 or the command CMD output from the command shift circuit 27 to create a response ST to the main monitoring control package 1 of the unit A. For example, when the ST creation circuit 28 inputs the response data from the ST selector 25 before the command CMD from the command shift circuit 27, that is, the command shift circuit 27 outputs the command CMD from the main monitoring control package 1. When the response data from the ST selector 25 is input while the data is held (within a fixed time), the start flag, the address, the control code, and the CRC check code are added to the response data from the ST selector 25. Create a response ST. The response ST created by the ST creation circuit 28 is sent to the main monitoring control package 1 of the unit A via the ST transmission line L2 ′ and the inter-unit connection cable 4.

Further, the ST creation circuit 28 has the command shift circuit 27 before the response data from the ST selector 25.
When the command CMD from the ST selector 25 is input, that is, while the command shift circuit 27 holds the command CMD from the main monitoring control package 1 (within a fixed time), the response data from the ST selector 25 is input. If not, the mounting information selector 2 is placed in the empty area of the command CMD from the command shift circuit 27, for example, the empty area of the CRC check code in the format shown in FIG.
9 from the mounting information and P from the PUALM selector 210
Write UALM information. Command C in which mounting information and PUALM information are written by the ST creation circuit 28
The MD is transmitted to the main monitoring control package 1 via the ST transmission line L2 'and the inter-unit connection cable 4.

The operation and effect of the transmission device according to this embodiment will be described below. In the transmission device, the unit A
The main monitoring and control package 1 loaded in the common slot of the unit B constantly sends the clock signal to the unit B, and the unit monitoring and control package 2 and the processing package loaded in the slots (1) to (n) of the unit B (1)
(N) to (n) operate according to the clock signal CLK from the main supervisory control package 1. Further, the CPU 10 of the main supervisory control package 1 executes I / O at regular intervals.
The O register 14 is accessed and its I / O register 14 is accessed.
Whether the signal stored in is a Hi signal or Lo
It is determined whether it is a w signal. Here, the CPU 10
If the signal of the / O register 14 is a Low signal, it is determined that the unit A and the unit B are connected by the inter-unit connection cable 4. On the other hand, the CPU 10
If the signal of the / O register 14 is a Hi signal, it means that the unit A and the unit B are not connected by the inter-unit connection cable 4, that is, the unit monitoring control package 2 is loaded in the slot (2) of the unit B. Determine that not.

CPU 10 of main supervisory control package 1
When it is determined that the unit A and the unit B are connected by the inter-unit connection cable 4 by referring to the signal stored in the I / O register 14, the slot (2) to the slot of the unit B A command CMD addressed to the processing packages (1) to (n) to monitor and control the processing packages (1) to (n) loaded in (n + 1)
To send.

On the other hand, the CP of the main supervisory control package 1
If the U10 refers to the signal stored in the I / O register 14 and determines that the unit A and the unit B are not connected by the inter-unit connection cable 4, the U10 stores them in the I / O register 14. Signal is continuously monitored, and the system waits until the unit A and the unit B are connected.

Main supervisory control package 1 of unit A
When transmitting a command CMD addressed to the processing packages (1) to (n) of the unit B, the CPU 10 of the main monitoring control package 1 creates instruction data for the processing package (n) of the unit B. Then, the CPU 10 of the main supervisory control package 1 adds the start flag, the address of the processing unit (n),
Control code for identifying the type of instruction data and CRC
A check code is added to create a command CMD.
The command CMD created by the CPU 10 is input to the CMD transmission unit 11 of the main monitoring control package 1.

The CMD transmitter 11 of the main supervisory control package 1 sends the command CMD from the CPU 10 to the signal line L.
Output to 1. At this time, the command CMD output to the signal line L1 is sent from the signal line L1 to the inter-unit connection cable 4, and is further input to the connector 7 of the unit B by the inter-unit connection cable 4.

Command CMD input to connector 7
Is input to the unit monitoring control package 2 via the signal line L1 ′ of the unit B. The command CMD input to the unit monitor control package 2 is simultaneously input to the CMD buffer 22, the address latch circuit 24, and the command shift circuit 27 of the unit monitor control package 2.

First, the CMD buffer 22 to which the command CMD is input stores the input command CMD once and then outputs it. The command CMD output from the CMD buffer 22 is sent to the processing packages (1) to (n) loaded in the slots (2) to (n + 1) of the unit B via the signal line L5 and the CMD transmission line T. To be

Further, the address latch circuit 24 to which the command CMD is input converts the input command CMD from the serial data format to the parallel data format, and the command CMD converted to the parallel data format is the 6-bit data indicating the destination address. Pull out. The destination address extracted by the address latch circuit 24 is the ST selector 25, the mounting information selector 29, and the PUALM.
It is input to the selector 220.

Further, the command shift circuit 27 to which the command CMD is input holds the input command CMD for a certain period of time. The command CMD sent from the CMD buffer 22 of the unit monitoring control package 2 to the processing packages (1) to (n) is the processing packages (1) to (n).
Entered in. The command CMD input to the processing packages (1) to (n) is the processing packages (1) to (n).
Is input to the CMD receiving unit 33 via the signal line L5.
The CMD receiving unit 33 of the processing packages (1) to (n),
The command CMD input via the signal line L5 is input to the device 34 in the package. Here, the devices 34 of the processing packages (1) to (n) read the destination address from the input command CMD, and determine whether the read destination address matches the address of their own package. In this case, since the destination address of the command CMD indicates the address of the processing package (n), only the device 34 of the processing package (n) has the same destination address as the command CMD and the address of its own package. And process package (n)
The other devices 34 determine that the destination address of the command CMD and the address of their own package do not match.

The device 34 of the processing package (n), which has determined that the destination address of the command CMD and the address of its own package match, sends the command C
Response data for MD is created, and the created response data is output. The response data output from the device 34 is input to the ST transmission unit 32.

The ST transmitter 32, which has input the response data,
The input response data is output to the signal line L7. Signal line L
The response data output to 7 is ST by the signal line L7.
It is sent to the transmission line Sn and further sent to the unit monitoring control package 2 by the ST transmission line Sn.

Further, the device 34 of the processing package (processing package other than the processing package (n)) which has determined that the destination address of the command CMD does not match the address of the own package is the command C described above.
Discard the MD.

From the processing package (n) to the ST transmission line Sn
The response data sent to the unit monitoring control package 2 via the is input to the unit monitoring control package 2. Then, the response data input to the unit monitoring control package 2 is sent to the ST buffer 26 via the signal line L7.
Is input to the memory element (n). Here, since the ST selector 25 of the unit monitoring control package 2 inputs the address of the processing package (n) as the address from the address latch circuit 24, the ST buffer 2
6 memory devices (n) will be accessed. Then, the ST selector 25 reads the response data (response data from the processing package (n)) stored in the memory element (n) of the ST buffer 26.

The response data read by the ST selector 25 is input to the ST creation circuit 28 of the unit monitoring control package 2. Here, the ST creation circuit 28 uses S
When the response data from the T selector 25 is input, the command CMD from the command shift circuit 27 has not been input yet, that is, the processing package ( If you input the response data from n), ST
A head flag, an address, a control code and a CRC check code are added to the response data from the selector 25 to create a response ST to the command CMD.

The response ST created by the ST creation circuit 28 is sent to the connector 6 of the unit A via the signal line L2 'and the inter-unit connection cable 4. Unit A
The response ST input to the connector 6 is input to the ST receiving unit 12 via the signal line L2.

The ST receiving section 12 which has input the response ST from the unit monitoring control package 2 inputs the input response ST to the CPU 10. On the other hand, in the unit supervisory control package 2, if the response data from the processing package (n) is not input within a certain time from the time when the command shift circuit 27 inputs the command CMD from the main supervisory control package 1, Shift circuit 2
7 outputs the command CMD held at the time when the above-mentioned certain time has elapsed. The command CMD output from the command shift circuit 27 is input to the ST creation circuit 28.

When receiving the command CMD from the command shift circuit 27, the ST creation circuit 28 writes the mounting information and PUALM information from the mounting information selector 29 and the PUALM selector 210 into the empty area of the above command CMD.

The above mounting information is the address latch circuit 2
It is the information read from the memory element (n) of the mounting information buffer 200 by the mounting information selector 29, which has received the address of the processing package (n) as the address from 4.
In addition, the PUALM information is the address latch circuit 2
It is the information read from the memory element (n) of the PUALM buffer 220 by the PUALM selector 210 which has input the address of the processing package (n) as the address from 4.

The ST creation circuit 28 implements the mounting information and PU.
The command CMD in which the ALM information is written is sent to the main monitoring control package 1 of the unit A via the signal line L2 ′ and the inter-unit connection cable 4. This command CMD is input to the CPU 10 of the main supervisory control package 1 in the same process as the response ST described above.
The CPU 10 which has input the command CMD refers to the mounting information and the PUALM information written in the input command CMD, and loads the processing package (n) of the destination of the above command CMD into the slot (n + 1) of the unit B. Is determined and whether or not the processing package (n) at the destination of the above command CMD has a power failure. For example, when the mounting information written in the command CMD from the unit monitoring control package 2 is a signal indicating the Hi level, the CPU 10 of the main monitoring control package 1 determines that the processing package (n) of the command CMD destination is the unit. B slot (n + 1)
It is determined that it is not loaded in. Further, when the PUALM information written in the command CMD from the unit monitoring control package 2 is a signal indicating the Hi level, the CPU 10 of the main monitoring control package 1 determines that the processing package (n) of the command CMD destination is the power supply. It is determined that something is wrong.

According to the embodiment described above, the unit monitoring control package 2 of the unit B and the n processing packages (1) to (n) are connected to the n ST transmission lines S1 to Sn.
Since they are connected in parallel with each other, a certain processing package malfunctions and a command CM addressed to another processing package is sent.
Even in the case of responding to D, it is possible to prevent the response from the processing package of the destination of the command CMD and the response from the malfunctioning processing package from colliding.

Further, the unit monitoring control package 2
Is the command CMD from the main supervisory control package 1
By transmitting the command CMD to the processing packages (1) to (n), it is possible to receive only the response data from the processing package (n) of the latched address. As a result, even if a certain processing package malfunctions and responds to the command CMD addressed to another processing package, the unit monitoring control package does not accept the response from the malfunctioning processing package and receives the processing package ( Only the response from n) can be accepted. Therefore, the unit monitoring control package 2 uses the command CMD
Only the response data from the destination processing package (n) can be transmitted to the main monitoring control package 1.

The unit monitoring control package 2 is
If there is no response from the processing package (n) within a fixed time after the command CMD from the main monitoring control package 1 is sent to the processing package (n), the mounting information and PUALM information regarding the processing package (n) Can be sent to the main supervisory control package 1.
As a result, the main supervisory control package 1 can determine that the processing package (n) has not been loaded in the slot of the unit B, or that the processing package (n) has a power failure. It is possible to reduce the time to wait for the response from the package (n), that is, the time to suspend the operation. Therefore, the time during which the main monitoring and control package 1 suspends its operation is shortened, so that the performance degradation of the entire transmission device can be suppressed. <Second Embodiment> A second embodiment of the supervisory control system for separating units according to the present invention will be described with reference to FIG. The supervisory control system for separating units according to the present embodiment will be described by taking as an example the case where it is applied to a transmission device as in the first embodiment. Here, only the differences from the first embodiment described above will be described, and the same aspects as those of the first embodiment will be denoted by the same reference numerals in the drawings and description thereof will be omitted.

FIG. 8 is a block diagram showing the internal structure of the unit monitoring control package 2 according to the second embodiment. The unit monitoring control package 2 shown in FIG.
CMD buffer 22, CLK buffer 23, address latch circuit 24, ST selector 25, ST buffer 26,
Command receiving circuit 230, ST transmitting circuit 240, mounting information buffer 200, PUALM buffer 220, and
The extension circuit 250 is mounted.

Each of the n memory elements forming the mounting information buffer 200 is connected to the signal line L8 and also connected to the ST transmission circuit 240 mounted in the unit monitoring control package 2. A latch circuit 250 and a hazard suppression circuit 290 as shown in FIG. 9 are provided in the middle of the signal line L8. Latch circuit 250
Is a circuit for latching the mounting information sent via the signal line L8, and the hazard suppression circuit 290 inserts or removes the processing packages (1) to (n) into or from the slots (2) to (n + 1). Hazard (noise) that occurs (Fig. 10
(See (a)) to prevent the latch circuit 250 from taking noise. The hazard suppression circuit 290 includes, for example, a resistor R, a capacitor C, and
It is a CR integrating circuit composed of an inverter 270.
Here, by specifying the time constant t of the resistor R and the capacitor C by the following integral formula, the hazard time to be suppressed can be set. t = −RC × 1n (VtH / VDD) where VtH is the threshold voltage of the inverter 270 and VDD is the power supply voltage of the inverter 270. This suppresses the hazard that occurs when the processing packages (1) to (n) are inserted and removed from the slots (2) to (n + 1) of the unit B (see (a) of FIG. 10), and the latch circuit 250 is It is possible to prevent taking in a hazard.

Further, each of the n memory elements forming the PUALM buffer 220 is connected to the signal line L9 and also connected to the ST transmission circuit 240 mounted on the unit monitoring control package 2. Signal line L9
In the middle of, like the mounting information buffer 200 above,
A hazard suppression circuit 290 and a latch circuit 260 are provided (see FIG. 9), and the processing packages (1) to (n) are provided.
Are suppressed from being inserted into and removed from slots (2) to (n + 1) so that the latch circuit 260 does not take in the hazard.

The address latch circuit 24 uses the signal line L
It is connected to the ST selector 25 while being connected to 1'and L3 '. The internal configuration of this address latch circuit 24 is similar to that of the first embodiment described above.

The ST selector 25 is the same as that of the first embodiment.
In contrast to the ST selector having n connection terminals, it has n + 1 connection terminals (1) to (n + 1). Among these n + 1 connection terminals, the n connection terminals (1) to (n) are the n memory elements (1) to (n) forming the ST buffer 26 as in the first embodiment.
One-to-one connection with each of. The remaining one connection terminal (n + 1) is connected to the ST transmission circuit 240 mounted on the unit monitoring control package 2 via a signal line. An address associated with the address assigned to the unit monitoring control package 2 is assigned to the remaining one connection terminal (n + 1). In this case, when the address of the unit monitoring control package 2 is input as the address from the address latch circuit 24, the ST selector 25 receives the above-mentioned connection terminal (n
Data input to +1), that is, the ST transmission circuit 2
Enter the data from 40. Also, the ST selector 25
A signal line L2 ′ is connected to the ST selector 2
The data output from 5 is transmitted to the main monitoring control package 1 of the unit A via the signal line L2 ′ and the inter-unit connection cable 4. Here, in the present embodiment, since the output from the ST selector 25 is directly transmitted to the main monitoring control package 1 of the unit A, the data output from the ST buffer 26, that is, the processing packages (1) to ( The data sent from n) is response data to which the head flag, address, control code, and CRC check code are added.

The command receiving circuit 230 mounted on the unit monitoring control package 2 is connected to the signal line L1 'and at the same time, the unit monitoring control package 2
Is connected to the ST transmission circuit 240 mounted in the above through a signal line. The command receiving circuit 230 receives the command CMD sent from the main monitoring control package 1 via the signal line L1 ′, and then receives the command CMD.
The destination address is read out from the above, and the read destination address is compared with the address assigned to the unit monitoring control package 2. When the destination address of the input command CMD and the address of the unit monitoring control package 2 match, the command receiving circuit 230 outputs the command CMD input via the signal line L1 ′.
Command CMD output from command receiving circuit 230
Is input to the ST transmission circuit 240 mounted on the unit monitoring control package 2. Also, enter the command C
If the MD destination address and the unit monitoring control package 2 address do not match, the command receiving circuit 23
0 discards the input command CMD.

The ST transmission circuit 240 mounted on the unit monitor control package 2 includes the command reception circuit 230 and the n memory elements (1) to (n) of the mounting information buffer 200.
(N), n memory elements (1) to (n) of the PUALM buffer 220, and the ST selector 25 are connected via signal lines. This ST transmission circuit 240
Is the command C output from the command receiving circuit 230.
MD, mounting information output from n memory elements (1) to (n) of the mounting information buffer 230, and PUA
N memory elements (1) to (n) of the LM buffer 220
The response S to the command CMD from the main supervisory control package 1 using the PUALM information output from
Create T. For example, when the ST transmission circuit 240 receives the command CMD from the command reception circuit 230, the n memory elements (1) of the mounting information buffer 200 are input.
To (n) and the PUALM information stored in the n memory elements (1) to (n) of the PUALM buffer 220 are read. Then, the ST transmission circuit 240 converts the read mounting information and PUALM information from the parallel data format to the serial data format. Further, the ST transmission circuit 240 creates the response ST to the command CMD by rewriting the command data portion of the command CMD from the command reception circuit 230 into the mounting information in the serial data format and the PUALM information. The response ST created in this way is ST
It is input to the connection terminal (n + 1) of the selector 25.

Further, the extension circuit 250 mounted on the unit monitor control package 2 is connected in the middle of the signal line L1 '. A light emitting diode LED is connected to the extension circuit 250. Then, when the extension circuit 250 inputs the command CMD in the serial data format from the main monitoring control package 1 via the inter-unit connection cable 4 and the signal line L1 ′, the extension circuit 250 extends the command CMD and inputs it to the light emitting diode LED, The light emitting diode LED is turned on. The extension circuit 250 may be composed of, for example, a CR integration circuit including a capacitor and a resistor. At this time, the time constants of the resistor and the capacitor that form the CR integration circuit are set so that the lighting time of the light emitting diode LED can be visually observed. Then, when the command CMD from the main monitoring control package 1 of the unit A is input to the unit monitoring control package 2, the light emitting diode L
The ED is turned on, and the maintenance person of the transmission device can recognize that the main monitoring control package 1 of the unit A is accessing the unit monitoring control package 2 of the unit B.

The other structure is the same as that of the first embodiment, and the description thereof is omitted. Hereinafter, the operation and effect of the transmission device according to the present embodiment will be described. In the transmission device, C of the main supervisory control package 1 of the unit A
If the signal stored in the I / O register 14 is a Low signal, the PU 10 receives slots (1) to
In order to monitor and control the unit monitoring control package 2 and the processing packages (1) to (n) loaded in the slot (n + 1), a command CMD addressed to the unit monitoring control package 2 or the processing packages (1) to (n) is issued. Send. Here, the operation of the transmission device when the command CMD addressed to the processing packages (1) to (n) is transmitted is the same as that in the first embodiment described above, and the description thereof will be omitted.

Main supervisory control package 1 of unit A
When sending a command CMD addressed to the unit monitoring control package 2 of the unit B, the CPU 10 of the main monitoring control package 1 creates command data for the unit monitoring control package 2 of the unit B. Then, the CPU 10 of the main supervisory control package 1 adds the start flag, the address of the unit supervisory control package 2, the control code for identifying the type of instruction data, and the CRC check code to the created instruction data to give the command C.
Create MD. The command CMD created by the CPU 10 is input to the CMD transmission unit 11 of the main monitoring control package 1.

The CMD transmitter 11 of the main supervisory control package 1 sends the command CMD from the CPU 10 to the signal line L.
Output to 1. At this time, the command CMD output to the signal line L1 is sent from the signal line L1 to the inter-unit connection cable 4, and is further input to the connector 7 of the unit B by the inter-unit connection cable 4.

Command CMD input to connector 7
Is input to the unit monitoring control package 2 via the signal line L1 ′ of the unit B. The command CMD input to the unit supervisory control package 2 includes the extension circuit 250, the CMD buffer 22, and the address latch circuit 2.
4 and the command receiving circuit 230.

First, the extension circuit 250 that has input the command CMD extends the input command CMD and inputs it to the light emitting diode LED, and then the light emitting diode LE.
Turn on D. At this time, the maintenance person of the transmission device can recognize that the main monitoring control package of the unit A is accessing the unit B by turning on the light emitting diode LED.

The command CMD output from the CMD buffer 22 is processed via the signal line L5 and the CMD transmission line T into the processing packages (1) to (1) to the slots (2) to (n + 1) of the unit B. Sent to (n). In this case, since the destination of the command CMD is the unit monitoring control package 2, the processing packages (1) to (n) that have received the command CMD are the received command CMD.
Will be discarded.

The address latch circuit 24 to which the command CMD is input converts the input command CMD from the serial data format to the parallel data format, and extracts the 6-bit data indicating the destination address from the command CMD converted to the parallel data format. . Address latch circuit 2
The destination address extracted by 4 is input to the ST selector 25.

The command receiving circuit 230 to which the command CMD is input reads the destination address from the input command CMD and compares the read destination address with the address of the unit monitoring control package 2. In this case, since the destination address of the command CMD matches the address of the unit monitoring control package 2, the command receiving circuit 2
30 receives the input command CMD from the ST transmission circuit 240
To enter.

Command C from command receiving circuit 230
The ST transmission circuit 240 which has input the MD accesses the mounting information buffer 200 and the PUALM buffer 220,
The n memory elements (1) to (1) of the mounting information buffer 200
The mounting information stored in (n) and P stored in the memory elements (1) to (n) of the PUALM buffer 220.
Read the UALM information. Then, the command receiving circuit 230 converts the mounting information and the PUALM information read from the mounting information buffer 200 and the PUALM buffer 220 from the parallel data format to the serial data format. Further, the ST transmission circuit 240 creates the response ST by overwriting the mounting information and PUALM information converted into the serial data format on the command data portion of the command CMD from the command receiving circuit 230. The response ST created in this way is connected to the connection terminal (n
+1) is input.

Since the ST selector 25 inputs the address of the unit monitoring control package 2 as the address from the address latch circuit 24 as described above, the connection of the address associated with the address of this unit monitoring control package 2 is connected. The data input to the terminal (n + 1), that is, the response ST from the ST transmission circuit 240 is input. Then, the ST selector 25 has a connection terminal (n +
The response ST input via 1) is output to the signal line L2 '.

The response ST output to the signal line L2 'is sent to the main monitoring control package 1 of the unit A via the signal line L2' and the unit connecting cable 4. At this time, the main monitoring control package 1 is loaded in the unit B by referring to the response data (data including mounting information and PUALM information) stored in the response ST from the unit monitoring control package 2. It is possible to grasp the processing package and the processing package in which the power supply abnormality has occurred.

According to the above-described embodiment, the main supervisory control package 1 of the unit A receives the command C addressed to the unit supervisory control package of the unit B at any time.
By transmitting the MD, the mounting information and PUALM information in the unit B can be acquired. Therefore, the main supervisory control package 1 refers to the mounting information and the PUALM information in the unit B, so that the unprocessed processing packages (1) to (n) and the processing packages (1) to ( Since it is possible to prevent the command CMD from being transmitted to n), the processing load on those processing packages (1) to (n) is reduced.

Further, by providing the light emitting diode LED in the unit monitoring control package 2 of the unit B and turning on the light emitting diode LED during the access from the main monitoring control package 1, the maintenance person of the transmission device can By referring to the LEDs, the timing of inserting / removing each package can be grasped. <Third Embodiment> A third embodiment of the supervisory control system for separating units according to the present invention will be described with reference to FIGS.
It will be described based on 2. The supervisory control system for separating units according to the present embodiment will be described by taking as an example the case where it is applied to a transmission device as in the first embodiment.
Here, only the differences from the first embodiment described above will be described, and the same aspects as those of the first embodiment will be denoted by the same reference numerals in the drawings and description thereof will be omitted.

First, FIG. 11 is a block diagram showing the internal structure of the unit monitoring control package 2 according to the third embodiment. The unit monitoring control package 2 shown in FIG. 10 has a CMD buffer 22, a CLK buffer 23, an address latch circuit 24, as in the second embodiment.
ST selector 25, ST buffer 26, command receiving circuit 230, ST transmitting circuit 240, mounting information buffer 20
0 and PUALM buffer 220 are mounted.
Further, the unit monitoring control package 2 has a CPU 29
0, ROM 300, RAM 310, interface dual port RAM 320, CMD / ST interface 330, address decoder 340, READ register group 350, WRITE register group 360, and unit dual port RAM 370 as a bus (address bus, data bus, and (Including control bus).

Dual port R for the above interface
The main monitoring and control package 1 is connected to one port of the AM 320 via the CMD / ST interface 330 and the unit connection cable 4. Also,
The bus of the unit monitor control package 2 is connected to the other port. The interface dual-port RAM 320 is divided into a CMD storage area and an ST storage area, as shown in FIG. And CM
The D storage area has 256 areas CMD # 001 to CM.
Each of these areas is configured to store 8-byte data. In each area CMD # 001 to CMD # 256 of this CMD storage area, the command CMD addressed from the main supervisory control package 1 to the unit supervisory control package 2 is stored. Also, the ST storage area of the interface dual port RAM 320 has 256 areas ST # 0 as in the CMD storage area.
01 to ST # 256, each of these areas is 8
It is designed to store bytes of data. This ST
In each area ST # 001 to ST # 256 of the storage area,
The response ST from the unit monitoring control package 2 to the command CMD from the main monitoring control package 1 is stored.

Now, returning to FIG. 11, the CMD / ST interface 330 includes the main monitoring control package 1
The signal line L1 ′ for transmitting the command CMD from the main monitor control package 1 and the signal line L3 ′ for transmitting the clock signal CLK from the main monitoring and control package 1 are connected. This CMD / S
The T interface 330 is a command CM from the main supervisory control package 1 to the unit supervisory control package 2.
When D is input, the input command CMD is written to the interface dual port RAM 320, and the response ST corresponding to the written command CMD is read from the interface dual port RAM 320. For example, CMD / ST interface 3
Reference numeral 30 denotes a serial / parallel converter S / P, an address latch register 330b, a data latch register 330c, and a timing generator 330 as shown in FIG.
d and a parallel / serial conversion unit P / S.

The serial / parallel conversion section S / P operates in accordance with the clock signal CLK from the main monitoring control package 1, and the main monitoring control package 1
From the serial data format to the parallel data format. The command CMD converted into the parallel data format by the serial / parallel conversion unit S / P is input to the address latch register 330b, the data latch register 330c, and the timing generator 330d of the CMD / ST interface 330.

The address latch register 330b extracts the address of the interface dual port RAM 320 from the command CMD from the serial / parallel converter S / P, and inputs the extracted address to the interface dual port RAM 320. here,
In the present embodiment, the command CMD from the main supervisory control package 1 to the unit supervisory control package 2 configures the CMD storage area of the interface dual port RAM 320 in the 5-byte instruction data area as shown in FIG. A memory address specifying each of the 256 areas and write data are stored. In this case, the address latch register 330b
Is the command CMD from the main supervisory control package 1
The memory address stored in the instruction data area is extracted and input to the interface dual port RAM 320.

The data latch register 330c extracts the write data from the command CMD shown in FIG. 14 and outputs the interface dual port RAM 32.
Enter 0. The timing generator 330d includes a latch timing signal T1 for the address latch register 330b, a latch timing signal T2 for the data latch register 330c, a chip select signal for the interface dual port RAM 320, and an REA for the interface dual port RAM 320.
It outputs a control signal for D / WRITE, an address that specifies each of 8 bytes in the area forming the interface dual port RAM 320, a switching signal between the CMD storage area and the ST storage area of the interface dual port RAM 320, and the like.

The parallel / serial converter P / S converts the response ST read from the interface dual port RAM 320 from a parallel data format to a serial data format. Response S in serial data format output from the parallel / serial conversion unit P / S
T is input to the ST buffer 26.

Returning to FIG. 11, the bus of the unit monitor control package 2 is connected to one port of the unit dual port RAM 370, and the UCMD transmitting unit 380 and the UST receiving unit 390 are connected. The unit dual-port RAM 370 distinguishes commands created by the CPU 290 and addressed to the processing packages (1) to (n) (hereinafter referred to as commands CMD from the main monitoring control package 1 to the processing packages (1) to (n)). Command UCMD). Command UCM stored in unit dual port RAM 370
D is read by the UCMD transmitter 380 and transmitted to the processing packages (1) to (n). The unit dual-port RAM 370 also includes a UST receiver 39.
A response (hereinafter, referred to as a response UST in order to distinguish it from the response ST addressed to the main monitoring control package 1 from the processing packages (1) to (n)) is stored.

Next, the address decoder 340, READ
Register group 350 and WRITE register group 360
The configuration will be described with reference to FIG. The address decoder 340 is connected to the CPU 290 via an address bus, and is also connected to each circuit forming the READ register group 350 and each circuit forming the WRITE register group 360 via signal lines. When the address from the CPU 290 is input, the address decoder 340 determines the circuit indicated by the input address and outputs an access permission signal for the determined circuit.

The READ register group 350 includes an enable control buffer 350b and an OR circuit 350a. The above-mentioned OR circuit 350a includes the CPU 290 and R
It is connected via the EAD control bus and also connected to the address decoder 340 via a signal line. The OR circuit 350a is a circuit that outputs an enable signal to the enable control buffer 350b when the READ signal from the CPU 290 and the access permission signal from the address decoder 340 are input.

The enable control buffer 350b.
A signal line L8 for transmitting mounting information from the processing packages (1) to (n) is connected to the. Further, the enable control buffer 350b is connected to the CPU 290 via a data bus. The enable control buffer 350b stores the mounting information sent from the processing packages (1) to (n) via the signal line L8, and stores it when the enable signal from the OR circuit 350a is input. The existing mounting information is output to the data bus.

The WRITE register group 360 includes a failure diagnosis circuit A, an LED lighting control circuit B, and a firmware debug L.
It is composed of an ED lighting control circuit C. The failure diagnosis circuit A is a circuit that detects runaway of the CPU 290, and includes an OR circuit 360a, a WDT (watch dog timer) monitoring circuit 360b, and a protection circuit 360c.

The OR circuit 360a of the fault diagnosis circuit A is C
It is connected to the PU 290 via the WRITE control bus, and is also connected to the address decoder 340 via a signal line. This OR circuit 350a has a C
WRITE signal from PU290 and address decoder 3
When the access permission signal from 40 is input, WD
An access signal is input to the T monitoring circuit 360b.

WDT monitoring circuit 360b of fault diagnosis circuit A
Has a timer (not shown) that is set when an access signal from the OR circuit 360a is input and is reset when the next access signal from the OR circuit 360a is input. When the predetermined time is exceeded, that is, when there is no access from the CPU 290 within the predetermined time, it is determined that the CPU 290 has runaway and WD
Output T alarm.

Here, the CPU 290 is normally held immediately when the WDT alarm is output even once.
Once the CPU 290 is held, the CPU does not function in the system at all, so that monitoring control cannot be performed until the CPU is restarted, and the system may be disconnected. Therefore, in the present embodiment, a protection circuit 360h as shown in FIG. 16 is provided in order to reset the CPU 290 and automatically recover it except when a fatal failure with high reproducibility occurs. This protection circuit 1
6 is three flip-flop circuits 500a, 500
b and 500c are connected in series. This FIG.
Then, the WDT alarm output from the WDT monitoring circuit 360b is input to the clock signal input terminal C of the above-mentioned three flip-flop circuits 500a, and the CP
It is input to the reset signal input terminal of U290. In FIG. 16, a positive power supply of 5V is connected to the data input terminal of the first-stage flip-flop circuit 500a. Furthermore, the output terminal Q of the first-stage flip-flop circuit 500a and the second-stage flip-flop circuit 500b.
The data input terminal D of is connected via a signal line. Further, the output terminal Q of the second-stage flip-flop circuit 500b and the third-stage flip-flop circuit 500c
The data input terminal D of is connected via a signal line. Furthermore, the third-stage flip-flop circuit 50
The output terminal Q of 0c and the hold signal input terminal of the CPU 290 are connected via a signal line.

The protection circuit 360h configured as described above
In the initial state, only the data input terminal of the first-stage flip-flop circuit 500a receives the current from the positive power source 5V and is at the Hi level. The data input terminals of the other flip-flops 500b and 500c are L
It is at ow level.

Then, the WDT monitoring circuit 360b changes the WDT
When the alarm is output, the WDT alarm output from the WDT monitoring circuit 360b indicates the three flip-flops 500.
a, 500b, and 500c, and the reset signal input terminal of the CPU 290. In this case, only the first-stage flip-flop circuit 500a of the protection circuit 360h outputs a Hi level signal. The Hi-level signal output from the first-stage flip-flop circuit 500a is input to the data input terminal of the second-stage flip-flop circuit 500b.

The second WD from the WDT monitoring circuit 360b
When the T alarm is output, the first-stage flip circuit 500a of the protection circuit 360h outputs a Hi-level signal from the positive power supply 5V and the second-stage flip circuit 5a.
00b outputs a Hi-level signal from the first-stage flip-flop circuit 500a. In this case, the Hi-level signal output from the second-stage flip-flop circuit 500b is input to the data input terminal D of the third-stage flip-flop 500c.

Then, from the WDT monitoring circuit, the third WD
When the T alarm is output, the flip-flop circuit 500a of the first stage of the protection circuit 360h causes the Hi voltage from the positive power source 5V to rise.
The second-stage flip-flop circuit 500b outputs a level signal and the first-stage flip-flop circuit 500a
From the second stage flip-flop circuit 500b, and the third-stage flip-flop circuit 500c outputs the Hi-level signal from the second-stage flip-flop circuit 500b.
The Hi-level signal output from the third-stage flip-flop circuit 500c is input to the hold signal input terminal of the CPU 290.

Now, returning to FIG. 15, the LED lighting control circuit B of the WRITE register group 360 has the OR circuit 36.
0c, flip-flop 360d, and four ANDs
The circuit 360e is provided.

OR circuit 360c of LED lighting control circuit B
Are connected to the CPU 290 via the WRITE control bus, and are also connected to the address decoder 340 via a signal line. This OR circuit 360c
Is a flip-flop 360d of the LED lighting control circuit B when the WRITE signal from the CPU 290 and the access permission signal from the address decoder 340 are input.
The access signal is output to. The access signal output from the OR circuit 360c is input to the clock signal input terminal of the flip-flop 360d of the LED lighting control circuit B.

The flip-flop 360d of the LED lighting control circuit B is connected to the CPU 290 via the data bus and also connected to each of the four AND circuits 360e via signal lines. The flip-flop circuit 360d inputs the LED lighting control command from the CPU 290 via the data bus, and the above-mentioned OR
When the access signal from the circuit 360c is input, the input LED lighting control command is output. The LED lighting control command output from the flip-flop 360d is input to each of the four AND circuits 360e.

Each of the four AND circuits 360e of the LED lighting control circuit B has a hold signal from the failure diagnosis circuit A and a flip-flop 360 of the LED lighting control circuit B.
The logical product with the LED lighting control command from d is calculated and the calculation result is transmitted to the processing packages (1) to (n). When the hold signal from the failure diagnosis circuit A is valid (CPU 290). Is held), the output from the flip-flop 360d is suppressed. The LED lighting control mentioned here is a control for turning on or off a fail lamp (LED which is turned on at the time of failure) provided in each of the processing packages (1) to (n). The fail lamp in each of the processing packages (1) to (n) is composed of a pull-up resistor, two inverting buffers connected in series, and an LED for the fail lamp, as shown in FIG. AND circuit 360e
The lighting control signal from L passes through two inverting buffers
It is designed to be input to the ED.

Now, returning to FIG. 15, the LED debugging control circuit C for firmware debug of the WRITE register group is
An OR circuit 360f, a flip-flop 360g, and a plurality of firmware debugging LEDs 360i are provided.

LED lighting control circuit C for firmware debugging
The OR circuit 360f of the
When the signal and the access permission signal from the address decoder 340 are input, the access signal is output. This O
The access signal output from the R circuit 360f is input to the clock signal input terminal of the flip-flop 360g of the firmware lighting LED lighting control circuit C.

LED lighting control circuit C for firmware debugging
The flip-flop 360g is connected to the CPU 290 via the data bus and is connected to the plurality of LEDs 3
Each of the 60i is connected via a signal line. The flip-flop circuit 360g inputs the lighting control command from the CPU 290 via the data bus, and outputs the lighting control command that has been input when the access signal from the OR circuit 360f is input. The lighting control command output from the flip-flop 360f is
It is input to each LED 360i.

According to the firmware debugging LED lighting control circuit C thus constructed, a simple program branch check or judgment data etc. can be sent to the LED 360 during debugging.
It can be represented by, which is useful for improving debugging efficiency. Not only for debugging, but also for several bits of LED
By using the to program the firmware to show the state inside the farm, it is possible to visually support the trouble response after the device system test or after being operated at the user's site, which is useful for trouble investigation.

Now, returning to FIG. 11, the inhibition circuit 400 is provided in the middle of the signal line L2 ′ connected to the ST selector 25 of the unit monitoring control package 2.
The inhibition circuit 400 is connected to the failure diagnosis circuit A of the WRITE register group 360, and is a circuit that masks the output from the ST selector 25 when the hold signal from the failure diagnosis circuit A is input. For example, if the unit monitoring control package 2 fails, the accuracy of the signal output from the unit monitoring control package 2 to the outside cannot be guaranteed, which may lead to system malfunction. The output to the outside can be suppressed to prevent the influence on the surroundings due to the failure.

Further, as shown in FIG. 18, the power-on extension circuit 410 of the unit monitor control package 2 has a power-on extension circuit 410a for extending the reset time of the CPU 290, and the unit monitor control package 2 is placed in the slot 1 of the unit B. The power-on extension circuit 410b extends the transmission timing of the mounting information transmitted to the main monitoring and control package 1 when loaded. However, a time difference is provided between the time t1 extended by the power-on extension circuit 410a that extends the reset time of the CPU 290 and the time t2 extended by the power-on extension circuit 410b that extends the transmission time of the mounting output, and a predetermined time is set after the CPU 290 is reset. After the time t has passed, the unit monitoring control package 2 sends the mounting information to the main monitoring control package 1 (see FIG. 19). As a result,
Access from the main monitoring control package 1 can be prevented during the reset period of the CPU 290 immediately after the unit monitoring control package 2 is loaded in the slot (2) of the unit B.

Returning to FIG. 11, the RAM 310 mounted in the unit monitoring control package 1 stores the traveling operation history of the CPU 290. It is preferable that the time of occurrence of a failure can be specified in this traveling operation history in consideration of analyzing the occurrence of a failure. Therefore, a clock function capable of displaying the date and time may be provided, but in the case of a package without the clock function, the CPU 29
An internal timer of 0 is used to store the time elapsed from power-on until a failure occurs together with error occurrence information. For example, if an event timer that outputs a signal every 50 msec is used as the internal timer of the CPU 290, the elapsed time from when the power is turned on is 50.
It can count in msec units. When a failure occurs, the count value of the event timer of the CPU 290 (the elapsed time from the time of power-on in days, hours, minutes, and seconds), the failure type, and error information are stored in the RAM.
Write to 310. However, since the memory area of the RAM 310 is limited, when the memory area is full, it is overwritten.

The CPU 290 operates in accordance with the application program stored in the ROM 300, and periodically operates slots (2) to (B) of the unit B.
Processing packages (1) to (n) loaded in (n)
Operation history, etc. are collected. For example, the CPU 290 creates a command UCMD addressed to the processing packages (1) to (n), and writes the created unit command UCMD in the unit dual port RAM 370. The unit command UCMD written in the unit dual port RAM 370 is read by the UCMD transmitting unit 380 and transmitted to the processing packages (1) to (n). The response UST from the processing package (n) to the unit command UCMD is received by the UST receiving unit 390. The UST receiving unit 390 that has received the unit response UST writes the received unit response UST in the unit dual port RAM 370. The unit response UST written in the unit dual port RAM 310 is read by the CPU 290 and written in the interface dual port RAM 320.

Further, the CPU 290 periodically accesses the interface dual port RAM 320 to read out the command CMD written by the main monitoring control package 1 via the CMD / ST interface 330. If this command CMD is an error occurrence history transmission command, the error occurrence history stored in the RAM 310 is read and the interface dual port R is read.
Write to ST area of AM330. Further, if the command CMD stored in the CMD area of the interface dual port RAM 330 is a request for transmitting the mounting information, the CPU 290 reads the mounting information stored in the READ register group 350 and stores the interface dual port RAM 330. Write in the ST area.

The operation of the unit monitoring control package 2 according to this embodiment will be described below. First, the unit monitoring control package 2 is installed in the slot (2) of the unit B.
Power-on extension circuit 410 when loaded into
Is the reset time of the CPU 290 and mounting information sent to the main supervisory control package 1 (information indicating that the unit supervisory control package 2 has been loaded into the slot (2)).
Extend the transmission time of. In this case, the mounting information is sent to the main monitoring control package 1 after a predetermined time from the time when the reset of the CPU 290 of the unit monitoring control package 2 is released.

[0146] The main monitoring control package 1 that has received the mounting information from the unit monitoring control package 2 starts transmission of the command CMD on the units monitoring control package 2.

Here, the operation of the unit monitoring control package 2 when the command CMD addressed to the processing packages (1) to (n) of the unit B is transmitted from the main monitoring control package 1 is the same as that of the second embodiment. The same is true, and the description is omitted.

The operation of the unit monitoring control package 2 when the command CMD addressed to the unit monitoring control package 2 is transmitted from the main monitoring control package 1 will be described with reference to the flowchart of FIG.

In the unit supervisory control package 2, the command CMD from the main supervisory control package 1 is input to the CMD / ST interface 330 via the signal line L1 '(S2001).

CMD / ST interface 330 to which the command CMD from the main supervisory control package 1 is input
Extracts the memory address and the write data from the command data area of the input command CMD (S200
2).

Then, the CMD / ST interface 33
0 is an address for designating a CMD storage area of the interface dual port RAM 320 together with the write data and the memory address extracted from the command CMD, and an 8-byte address in the area specified by the memory address of the CMD storage area. , WRIT
The E control signal is output (S2003). Where CP
If the U290 is accessing the CMD / ST interface 330 (S2004), the write data output from the CMD / ST interface 330, the memory address, the address designating the CMD storage area of the interface dual port RAM 320, and the address are specified. Address of 8 bytes in the area specified by the memory address in the CMD storage area,
Also, the WRITE control signal indicates that the dual port RAM 320 for interface is used after the access of the CPU 290 is completed.
Entered in. The interface dual port RAM 330 to which these data have been input writes the above-mentioned write data to the area specified by the input address (S2005).

Further, in S2003, the CPU 290
Is not accessing the interface dual port RAM 320, the CMD / ST interface 33
The write data output from 0, the memory address, the address that specifies the CMD storage area of the interface dual port RAM 320, and the 8 bytes in the area specified by the memory address in the CMD storage area specified by this address. Address and W
The RITE control signal is immediately input to the interface dual port RAM 320, and the write data is written in the area specified by the input address (S2).
008).

On the other hand, the CMD / ST interface 330
Is the command CMD from the main supervisory control package 1
The number of bits of the command CMD is counted by using the input of the first bit of
Command CMD when 64 bits of
Along with the memory address extracted from the address, an address designating the ST storage area of the interface dual port RAM 320, and an 8-byte address in the area specified by the memory address of the ST storage area,
A READ control signal is output (S2006).

A memory address output from the CMD / ST interface 330, an address designating an ST storage area of the interface dual port RAM 320,
The 8-byte address in the area specified by the memory address of the ST storage area and the READ control signal are the dual port RAM 320 for interface.
Entered in. At this time, the interface dual port RAM 320 reads out the data stored in the area specified by the input address. And dual port RAM3 for interface
The data read by 30 is converted from the parallel data format to the serial data format by the parallel / serial conversion unit P / S of the CMD / ST interface 330. The data converted into the serial data format by the parallel / serial conversion unit P / S is input to the ST buffer 26. Since the address of the unit monitoring package 2 is input to the ST selector 25 as the address read from the command CMD by the address latch circuit 24, the ST selector 25 sets S
Of the memory elements (1) to (n + 1) of the T buffer 25, the data stored in the memory element (n + 1) of the address corresponding to the address of the unit monitoring control package 2, that is, written by the CMD / ST interface 330. Read the data. ST selector 2
The data read by 5 is sent to the main monitoring control package 1 via the signal line L2 ′ and the inter-unit connection cable 4. When the inhibition circuit 400 provided in the middle of the signal line L2 ′ is inputting the hold signal from the failure diagnosis circuit A of the WRITE register group,
The data read from the ST selector 25 is masked by the inhibition circuit 400 and then sent to the main supervisory control package 1 (S2007).

As described above, according to the unit monitoring control package 2 of the present embodiment, the data from the processing packages (1) to (n) can be collected in advance, so that the main monitoring control package 1 can be It is not necessary to collect data from the processing packages (1) to (n), and the burden on the main monitoring and control package 1 can be reduced.

In this embodiment, an example in which one main monitoring control package 1 is loaded in the common slot of the unit A has been described. However, two main monitoring control packages (A) 1 and 1 are loaded in the common slot of the unit A. The main supervisory control package (B) 100 may be loaded, and the supervisory control of the unit B may be performed by the two main supervisory control packages (A) 1 and (B) 100. In this case, the interface dual-port RAM 320 mounted in the unit supervisory control package 2 is a CMD for the main supervisory control package (A) 1 as shown in FIG.
The storage area and the ST storage area are divided into the CMD storage area and the ST storage area for the main monitoring control package (B) 100.

Further, C of the unit monitoring control package 2
PU290 is the CM for the main supervisory control package (A)
The command CMD stored in the D storage area is copied to the ST storage area for the main monitoring control package (B) 100, or is stored in the CMD storage area for the main monitoring control package (B) 100. Command CMD S for main monitoring control package (A) 1
By copying to the T storage area, the main monitoring control package (A) 1 and the main monitoring control package (B) 10
It is also possible to exchange information with 0.

Further, in the unit monitoring control package 2 according to this embodiment, the interface dual port RAM 3 is used when the firmware is initialized.
It is necessary to perform 20 Read / Write checks. If the main supervisory control package 1 makes an access while the interface dual port RAM 320 is undergoing a memory check, the access from the main supervisory control package 1 conflicts with the memory check. RAM32
A memory check error of 0 is determined. Therefore, FIG.
As shown in 2, dual port RA for interface
WRITE register group 360 that outputs an enable signal when the memory check of M320 is completed, and the WR described above.
An enable control gate 420 for inputting a control signal from the CMD / ST interface 330 to the interface dual port RAM 320 when an enable signal from the ITE register group 360 is input is provided. In this case, during the initial setting of the firmware such as when the unit monitoring control package 1 is loaded in the slot (2) of the unit B, the main monitoring is performed while the memory check of the interface dual port RAM 320 is being performed. Access from the control package 1 to the interface dual-port RAM 320 is disabled, and it is possible to prevent a conflict between the memory check and the access from the main monitoring control package 1 and prevent a memory check error from occurring.

Further, like the unit monitoring control package 1 according to the present embodiment, the processing packages (1) to (1) to
When the LED lighting control circuit B for controlling the lighting of the fail lamp of (n) is provided, a hazard that occurs when the unit monitoring control package 2 is inserted into and removed from the slot (2) of the unit B is the processing package (1). To (n), the LEDs for the fail lamps of the processing packages (1) to (n) blink. Therefore, FIG.
As shown in (a) or (b) of 3, the output from the LED lighting control circuit B is output through the gate with three-state output control or the open collector output gate, and the power-on reset signal is input. The output from the LED lighting control circuit B may be masked during the period. In this case, hazards that occur when the unit monitoring control package 2 is inserted and removed from the slot (2) of the unit B are suppressed, and the fail lamp LEDs of the processing packages (1) to (n) are prevented from blinking. .

Further, when the CPU 290 collects data from the processing packages (1) to (n) at regular intervals like the unit monitoring control package 1 according to this embodiment, the interface dual port RAM 3 is used.
The data stored in 20 (the data collected by the CPU 290 from the processing packages (1) to (n)) is updated at regular intervals. On the other hand, the main supervisory control package 1 also has an interface dual port R at regular intervals.
The AM 320 will be accessed to read the data collected by the CPU 290. Therefore, the main supervisory control package is the dual port R for interface.
In consideration of the cycle of accessing the AM 320 and the cycle of updating the data of the interface dual port RAM 320 by the CPU 290, the main monitoring control package 1
It is preferable that the state generated during the access cycle of the user can be retained without being updated and the main monitoring control package 1 can be notified.

The states that occur in the processing packages (1) to (n) include, for example, the following three types of alarms. "Warning" --- An alarm that occurs within 1 second and recovers "minor" --- An alarm that continues for 1 second or longer,
Alarm "major" that recovers within 2 seconds ... Alarm that continuously occurs for 3 seconds or more In order to hold the above three alarm occurrences in the interface dual port RAM 320, the processing packages (1) to ( The state of n) must be held in seconds. For example, as shown in FIG. 24, when the access cycle of the main monitor control package 1 is set to 1 second and the data collection cycle of the unit monitor control package 2 is set to about several us, an alarm (Warning) is generated within 1 second. In order to notify the main supervisory control package 1, it is necessary to synchronize the access timing from the main supervisory control package 1 with the data update timing of the main supervisory control package 2. Therefore, as shown in FIG. 25, a collection end flag writing area is provided in the interface dual port RAM 320. In this collection end flag writing area, "01" (collection end flag) is set when the main monitoring control package 1 reads data. Then, the collection end flag “01” in the collection end flag writing area is reset to “00” when the CPU 290 updates the data.

Here, the data collection processing of the unit monitoring control package 2 will be described with reference to the flowchart of FIG. CPU of unit monitoring control package 2
290 reads the mounting information of the processing packages (1) to (n) from the READ register group 350 (S260).
1).

The CPU 290 accesses the interface dual port RAM 320 and refers to the flag of the collection end flag writing area (S2602). In S2602, the CPU 290 determines whether or not the flag of the collection end flag writing area is “01” (S2603).

If the flag "01" is written in the collection end flag writing area in S2603, the CPU 290 writes "1" in the collection end flag writing area.
00 "is written (S2604).

Then, the CPU 290 clears the mounting information of the interface dual port RAM 320 (the mounting information collected last time) (S2605), and newly writes the mounting information read from the READ register group 350 (S2606).

If "00" is stored in the collection end flag writing area in S2603,
The CPU 290 is a dual port RA for interface.
The mounting information (the mounting information collected last time) stored in the M320 is read (S2607), the logical sum of the read mounting information and the mounting information collected this time is calculated, and the mounting information obtained by this logical sum calculation ( The cumulative information of the mounting information collected last time and the mounting information collected this time is written to the interface dual port RAM 320 (S26).
08).

Thus, the main supervisory control package 1
By synchronizing the access timing from the data update timing with the data update timing in the unit monitoring control package 2, it is possible to eliminate the omission of information and notify the main monitoring control package of the above-mentioned alarm.

Further, a pseudo alarm generating jig as shown in FIG. 27 may be loaded in the common slot of the unit A of the transmission apparatus according to this embodiment. The pseudo-alarm generation jig is an arbitrary alarm (Warning, minor, major, etc.) for the processing packages (1) to (n).
c. ) Is output, and when the output enable signal of the pseudo alarm generation command is input from the main monitoring control package 1, the command C including the pseudo alarm generation command is input.
Output MD.

The command CMD output from the pseudo alarm generating jig is converted from the serial data format to the parallel data format in the CMD receiving section 230 of the unit monitoring control package and sent to the processing packages (1) to (n).

Here, the command CMD from the false alarm generating jig and the command C from the main monitoring control package 1
It is necessary to prevent the MD from colliding with the inter-unit connection cable 4. For example, as shown in FIG. 24, the access from the main supervisory control package 1 to the unit supervisory control package 2 is performed in a cycle of 1 second,
The path of the inter-unit connection cable 4 that connects the main monitoring package 1 and the unit monitoring control package 2 is used only for several tens of ms in a cycle of 1 second, and the remaining time is idle. Therefore, the main monitoring control package 1 outputs the output permission signal for the pseudo alarm generating jig at a time other than the time occupied by the normal command CMD (see FIG. 28).

A command CM including a pseudo alarm generation command
D is a process package (1) to the CMD receiving unit 230.
Although it may be transmitted to (n), as shown in FIG. 29, it may be transmitted to the processing packages (1) to (n) via the interface dual port RAM 320. In this case, the unit monitoring control package 2
The dual port RAM 320 for the interface of
An area for storing the command CMD for pseudo alarm is provided.
Further, the WRITE register group 360 of the unit monitoring control package 2 outputs an I / O that outputs a pseudo alarm generation command.
Have a port. Then, the unit monitoring control package 2 writes this command CMD in the command storage area for the pseudo alarm when the command CMD for generating the pseudo alarm is interrupted during the time other than the time when the normal command CMD is processed. Then, the CPU 290 of the unit monitoring control package 2 once accesses the command storage area for the pseudo alarm of the interface dual port RAM 320 in a time zone other than the time when the normal command CMD is processed, and stores it in the command storage area. The stored command CMD is set to I in the WRITE register group 360.
/ O port to process packages (1) to (n).

By the way, if a pseudo alarm is generated by using a pseudo alarm generating jig and a pseudo alarm is generated by mistake during operation of the device, the transmission device malfunctions. It is preferable to prohibit the generation of an alarm. Therefore, as shown in FIG.
When the pseudo alarm generation jig is mounted, the ground level in the jig is sent to the unit monitoring control package 1 through the inter-unit cable, and when the ground level signal is input, the CMD receiving section 230 sends the signal. You may make it provide the buffer with the enable which validates a pseudo alarm generation instruction. Normally, since the pseudo alarm generation jig is not loaded during the operation of the transmission device, the enable buffer of the unit monitoring control package 1 receives a signal from the positive power source 5V connected via the pull-up resistor. Therefore, the output from the enable buffer is prohibited.

Further, the unit monitor control package 2 uses a buffer with enable control as a CMD buffer, and the command CM from the above-mentioned pseudo alarm generating jig is used.
The buffer with enable control may be controlled by D. In this case, the disconnection state of the signal line for transmitting the command CMD can be simulated by inputting the disable signal from the pseudo alarm generating jig to the enable control buffer. Here, the processing package (1)-
When there are a plurality of (n), the cut state can be simulated for each of the processing packages (1) to (n).
This makes it possible to test whether the unit monitoring control package 2 turns on the fail lamp LED of the processing package (n) when the disconnection state of a certain processing package (n) is simulated. It is possible to verify whether the fail lamp lighting control of the package 2 is normal.

Next, FIG. 31 is a diagram showing a system for performing a performance test of an application program stored in the ROM 300 of the unit monitoring control package 2 according to this embodiment.

The jig 1 in the figure simulates the main monitoring and control package and transmits and receives CMD and ST. This jig 1 is used to send the command CMD set by the test program of the personal computer and to send the command CMD.
A response ST to is received.

The jig 2 in the figure is the processing package (1)-
By simulating (n), a response ST to the command CMD from the unit monitoring control package 2 is transmitted, and DC information is input / output. The jig 2 transmits a response ST to the command CMD by the test program of the personal computer. Here, the CMD DPRA of the jig 2
M and ST DPRAM are unit monitoring and control package 2
Is a part that simulates a CMD / ST interface for the processing package (n). CMD DPRAM
Extracts the address in the command CMD,
At the same time as writing to the PRAM, the response data preset by the test program of the personal computer is read from the ST DPRAM. The unit monitoring control package 2 transmits the response ST from the jig 2 to the jig 1.

Thus, the command CMD from the jig 1
Is monitored by the personal computer of the jig 2 via the unit monitoring control package 2, and the response ST from the jig 2
The personal computer of the jig 1 monitors the unit monitoring control package 2 to debug the firmware of the unit monitoring control package 2.
It can be simulated in the absence of an actual device.

As a jig for performing the performance test of the unit monitoring control package 2, as shown in FIG. 32, a device capable of simulating the main monitoring control package and the processing package (n) with one unit may be used.

[0179]

According to the present invention, it is possible to prevent the response from the processing package which is the destination of the command from colliding with the response from the malfunctioning processing package, and at the same time, the response from the processing package which is the destination of the command. Can be reliably sent to the main supervisory control package.

Also, according to the present invention, it is possible to determine the mounted or unmounted state of the processing package.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a transmission device.

FIG. 2 is a block diagram showing an internal configuration of a transmission device.

FIG. 3 is a block diagram showing a configuration of a unit monitoring control package according to the first embodiment.

FIG. 4 is a block diagram showing a configuration of an address latch circuit.

FIG. 5 is a diagram showing a format of a command CMD and a response ST.

FIG. 6 is a timing chart showing an address detection process.

FIG. 7 is a diagram illustrating an address assigned to a connection terminal of an ST selector.

FIG. 8 is a block diagram showing the configuration of a unit monitoring control package according to the second embodiment.

FIG. 9 is a diagram illustrating a hazard suppression mechanism.

FIG. 10 is a diagram showing a waveform of a signal input to the hazard suppression mechanism and a waveform of a signal output from the hazard suppression mechanism.

FIG. 11 is a block diagram showing a configuration of a unit monitoring control package according to a third embodiment.

FIG. 12 is a diagram illustrating a configuration of a dual port RAM.

FIG. 13 is a block diagram showing an internal configuration of a CMD / ST interface.

FIG. 14 is a diagram showing a format of a command CMD in the third embodiment.

FIG. 15 is a diagram showing a configuration of a WRITE register group and a READ register group.

FIG. 16 is a diagram showing a configuration of a protection circuit.

FIG. 17 is a diagram showing a configuration of an LED for a fail lamp of a processing package.

FIG. 18 is a block diagram showing the configuration of a power-on extension circuit.

FIG. 19 is a diagram showing a reset signal and mounting information extended by a power-on extension circuit.

FIG. 20 is a flowchart showing an operation process of the unit monitoring control package when receiving a command CMD.

FIG. 21 is a block diagram showing the configuration of a unit monitoring control package according to another embodiment.

FIG. 22 is a block diagram showing the configuration of a unit monitoring control package according to another embodiment.

FIG. 23 is a diagram showing a configuration of a circuit for masking an output from the LED lighting control circuit B while a power-on reset signal is being input.

FIG. 24 is a timing chart showing the data collection cycle of the main supervisory control package 1 and the data update cycle of the unit supervisory control package.

FIG. 25 is a block diagram showing a configuration of a unit monitoring control package according to another embodiment.

FIG. 26 is a flowchart showing the data update processing of the unit monitoring control package.

FIG. 27 is a block diagram showing the configuration of a transmission device according to another embodiment.

FIG. 28 is a timing chart showing the timing of outputting a command CMD for generating a false alarm.

FIG. 29 is a block diagram showing the configuration of an apparatus for performing a performance test of a unit monitoring control package.

FIG. 30 is a block diagram showing the configuration of an apparatus for performing a performance test of a unit monitoring control package.

FIG. 31 is a block diagram showing the configuration of an apparatus for performing a performance test of a unit monitoring control package.

FIG. 32 is a block diagram showing the configuration of an apparatus for performing a performance test of a unit monitoring control package.

[Explanation of symbols]

1 ... Main supervisory control package 2 ... Unit monitoring control package 3 ... Processing packages (1) to (n) 22 ... CMD buffer 23 ... CLK buffer 24 .. Address latch circuit 25 ... ST selector 26 ... ST buffer 27 ... Command shift circuit 28 ... ST creation circuit 29 ... Mounting information selector 200 ... Mounting information buffer 210 ··· PUALM selector 220 ··· PUALM buffer

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Tanaka 2-6, Jomi, Chuo-ku, Osaka-shi, Osaka Within Fujitsu Kansai Digital Technology Co., Ltd. (72) Satoshi Nishimura, Chuo-ku, Osaka-shi, Osaka 2-6, Jomi, Fujitsu Kansai Digital Technology Co., Ltd. (72) Inventor, Kazuyuki Miura 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (56) References 6-103177 (JP, A) JP 7-143149 (JP, A) JP 5-265945 (JP, A) JP 6-139183 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) G06F 15/16-15/177 G06F 13/00 H04L 13/02-13/18 H04L 29/00-29/12

Claims (4)

(57) [Claims] 1. A separating unit comprising a first unit for loading a plurality of processing packages and a second unit for loading a main monitoring control package for controlling the processing packages loaded in the first unit. And a destination discriminating means for discriminating a processing package of a destination of a command sent from the main monitoring control package to a processing package, and an information storage area corresponding to each of the plurality of processing packages. A response storage unit for storing a response to the command from the processing package in an information storage area corresponding to the processing package; and a response processing unit corresponding to the destination processing package determined by the destination determination unit of the response storage unit. Information selecting means for reading a response stored in the information storage area; The response read by the selecting means is the second
And a response transmitting means for transmitting the unit monitor control package to the main monitor control package of the unit. The unit monitor control system for separating units, wherein the unit monitor control package is loaded in the first unit. Wherein said unit monitoring control package further comprises said Yu destination of the command by the destination determination unit loading information determination means for determining processing package that is loaded in the first unit
When it is determined that the package is a knit monitoring control package , the response transmitting unit monitors the main monitoring information for identifying the processing package determined to be loaded in the first unit by the loading information determining unit. The supervisory control system of the separating unit according to claim 1, wherein the monitoring control system transmits to a control package. 3. The unit supervisory control package further comprises loading information discriminating means for discriminating a processing package loaded in the first unit, and the response transmitting means sends a command from the main supervisory control package. Information for identifying the processing package which is determined to be loaded in the first unit by the loading information determination means unless a response is sent from the processing package within a predetermined time from the time of sending the processing package. Is transmitted to the main monitoring and control package. 4. The unit monitoring control package, a command creating unit that creates a command addressed to the processing package, a command sending unit that sends the command created by the command creating unit to the processing package, and the command sending unit. A response receiving means for receiving a response from the processing package to the command transmitted by the means, and a response received by the response receiving means,
Information storage means for storing the processing package together with information for identifying the processing package, and when receiving a command from the main monitoring control package, searches the information storage means and reads a response from the processing package at the destination of the command. The supervisory control system of the separating unit according to claim 1, further comprising: a response read-out means, wherein the response sending means sends the response read by the response read-out means to the main supervisory control package. .