JP3461428B2 - Clock non-stop switching device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives a clock supplied in duplicate from the outside, selects one of the clocks as an internal reference clock, and operates the apparatus without a clock using a clock phase synchronization method. It relates to the device.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing the structure of a conventional apparatus disclosed in Japanese Patent Laid-Open No. 5-268197. In the figure, based on the clock selected by the first selection unit 511, the delay unit 521 generates a plurality of delayed clocks. Based on the phase difference measured by the phase comparing unit 512, the one having the smallest phase difference from the output clock of the second selecting unit 514 is selected by the third selecting unit 518, and the control is performed by the clock pulse generating circuit 515A. To do. Since the two input clocks of the fourth selection unit 519 are suppressed to the minimum phase difference, the switching here can be performed without interruption.

The above-mentioned publication also discloses a basic configuration in which a phase delay unit for obtaining an output with a variable phase delay is provided as FIG. 1 in the publication. In this basic configuration, the clocks to be switched are sequentially delayed, for example, continuously, and switched when the phase difference disappears.

[0004]

Since the conventional device is constructed as described above, the clocks of the two systems external to the device, for example, the 0 system as the working system and the 1 system as the backup system are directly switched. Therefore, it is necessary to suppress the phase difference for switching to be extremely small, and the delay unit needs to generate a large number of clocks having different delays. That is, there is a problem that a large number of delay circuits are required. Further, in the case where one continuous variable delay circuit is used, there is a problem that the allowable phase difference is not so large or the time until the phase difference is eliminated becomes long.

The present invention has been made to solve the above-mentioned problems, and even if there is a large phase difference between the clocks of the two systems from the outside of the device, the required clocks can be switched without interruption with a small type of delay. The purpose is to obtain the device.

[0006]

SUMMARY OF THE INVENTION A clockless uninterruptible switching device according to the present invention receives an input side clock of two systems of a working system and a standby system by a corresponding receiving section and selects one of them to select an internal clock. In the clock switching device for outputting as the above, a delay circuit for sequentially giving a plurality of phase delays different by a predetermined delay amount to one side of the input side clock of each system, and the currently selected clock of the active system which is the switching partner.
Based on the click, pre for the clock to be the reference
And comparison and selection circuit for selecting a clock most phase difference is small from the output of the delay circuit of Bei system, the comparison and selection of auxiliary system
A single clock to switch between the active clock and the active reference clock
Receive clock system selection circuit and this receive clock system selection
It was equipped with a single phase difference absorption circuit that obtains an output that eliminates the phase difference between the clock selected by the circuit and the clock of the active system .

Further, a selection for instructing the comparison / selection circuit to sequentially switch and select the output of the delay circuit at every predetermined time so that the output of the comparison / selection circuit becomes equal to the input clock of the delay circuit. A signal control circuit was added.

Furthermore, a phase difference monitoring unit is added to issue an alarm when the difference between the two inputs to be selected by the comparison / selection circuit is a predetermined value or more.

[0009]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. FIG. 1 is a block diagram of a clockless hitless switching device according to a first embodiment of the present invention. In the figure,
Reference numeral 11 is, for example, a clock supply device for inputting the clocks of the active system and the standby system, 12a and 12b are clock receiving units, 1
Reference numerals 3a and 13b are delay circuits, 14a and 14b are comparison / selection circuits that compare phases and select the one having the smallest phase difference, 15 is a reception clock system selection unit, and 16 is a PLL circuit as a phase difference absorption circuit. . Also, CLK2, CLK
3 is a 0-system, 1-system comparison / selection circuit 14a, 14b
Is the selected output. The delay circuits 13a and 13b have a plurality of phase delays, for example, 1 / n of the clock cycle.
N clocks each having a different phase are generated using a delay line or the like. The comparison / selection circuits 14a and 14b select the output of the delay circuits 13a and 13b having the smallest phase difference as compared with the clock CLK2 or CLK3 after the selection of the other system. This configuration is characterized in that a PLL circuit is provided.

The operation of the above apparatus will be described. The two clocks from the clock supply device 11 are received by the clock receivers 12 for the 0 system and the 1 system, respectively, and CL
Obtain K0 and CLK1. Next, in the delay circuit 13a,
Based on CLK0, n outputs with different delays are generated. The comparison / selection circuit 14a uses the clock CLK after selecting another system.
Compared with 3, the output of the delay circuit 13a having the smallest phase difference from the n outputs of the delay circuit 13a is selected and output.
Clock CLK2 output from the comparison / selection circuit 14a
Is synchronized with the clock CLK3 in the other system device with accuracy determined by the value of n. Further, for the phase difference that cannot be completely removed, the phase difference is gradually absorbed by the PLL circuit 16. The clock can be switched without instantaneous interruption. With this configuration, even if the phase difference at the time of switching is small, the last PLL circuit 16 can eliminate the difference. Conversely, the number of delay clocks n generated by the delay circuit can be reduced.

FIG. 2 is a block diagram of another non-instantaneous clock switching device according to the present embodiment. In the configuration of FIG. 2, an interruption detection signal is obtained from the clock reception units 12a and 12b, and the reception clock system selection unit 15 operates to switch between the 0-system clock and the 1-system clock by using this as a trigger.

Embodiment 2. An apparatus will be described in which the internal clock is always close to the input clock of either the 0 system or the 1 system, and therefore the delay circuit and the like are reduced. FIG. 3 is a configuration diagram of the clockless hitless switching device according to the second embodiment. In the figure, the same symbols as in FIG. 1 indicate the same devices, and there are 40 selection signal control units as new elements.

In the first embodiment, only the frequency of the clock received from the outside is taken into the device, and those having completely different phases are used in the device.
In the present embodiment, it is possible to receive the phase information of the external clock at the same time. Selection signal control unit 40
For example, when the output of the comparison / selection circuit 14a has a phase different from that of the clock CLK0 received by the clock reception unit 12a, the system is switched to the own system by the non-instantaneous switching and then selected by the comparison / selection circuit 14. The counter circuit is used to shift the generated signal in a direction approaching the clock CLK0 received by the clock receiving unit 12a at a speed that the PLL circuit 16 can follow. In this way, the clock CL finally received from outside the device
Either K0 or CLK1 is the comparison / selection circuit 1 as it is.
4 is output.

In the above control operation, CLK2 becomes CLK
After it becomes equal to 0, CLK0 is switched to be directly input to the reception clock system selection unit 15. Further, thereafter, the delay circuit 13a, the comparison / selection circuit 14a, and the selection signal control unit 4
Switch 0 together to 1 system. In this state, if there is an instruction to select another system again, a delay clock group having a small phase difference is selected from the delay clock group obtained by delaying CLK1 and the shift operation is performed. The comparison / selection / selection signal control unit needs only one system, and the circuit scale can be small.

Another clockless uninterruptible switching device according to the present embodiment will be described. FIG. 4 is a configuration diagram thereof. In the figure, 50a and 50b are phase difference monitoring circuits. If the selection signal controller 40 is provided, the comparison / selection circuit 1
4a and 14b, the selected signal is the clock CLK0 received by the clock receiving units 12a and 12b,
When it becomes CLK1 itself, the fact is notified to the other system by the shift completion signal STC. After the shift is completed, the outputs of the comparison / selection circuits 14a and 14b are the clocks 0CLK0 and 0CLK from the clock supply device 11.
Therefore, the phase difference of the selected clock with respect to the input clock represents the phase difference of the two clocks from the clock supply device 11. Therefore, the phase difference monitoring circuit 50 monitors the phase difference and issues an alarm if the phase difference is out of regulation.

Further, according to the above configuration, the delay circuit 13
Output cannot be sent in sequence a and 13b, next is 1 / n
Cycle deviation, third is 2 / n cycle deviation, ..., k
If the (k <n) th is arranged in the order of (k + 1) / n cycle shifts, the phase difference monitoring circuit 50 selects simple clocks indicating which clock has been selected when the clock is selected by the comparison / selection circuit 14a. The phase shift from CLK0 can also be known. That is, a monitoring circuit that inputs two signals and calculates the analog amount of the difference is unnecessary.

The configuration of FIG. 4 can be combined with the configuration of FIG. That is, the delay circuit 13a, the comparison
The selection circuit 14a, the selection signal control circuit 40a, and the phase difference monitoring circuit 50a can be combined into one set.

[0018]

As described above, according to the present invention, 2
Since the delay circuit and the phase difference absorbing circuit that may have a small number of delays are provided for switching the clocks having different phases of the system, the circuit scale is small and there is an effect that clocks with a large phase difference can be switched without interruption.

Furthermore, since a simple phase difference monitoring circuit is provided, there is an effect that it is easy to monitor the phase difference between the two clocks.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a clockless hitless switching device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of another non-instantaneous clock switching device according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a clockless hitless switching device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of another non-instantaneous clock switching device according to the second embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional clockless hitless switching device.

[Explanation of symbols]

11 Clock Supply Device, 12a, 12b Clock Reception Unit, 13a, 13b Delay Circuit, 14a, 14b Phase Comparison / Selection Circuit, 15 Reception Clock System Selection Unit, 16
PLL circuit, 40, 40a, 40b selection signal control unit,
50a, 50b Phase difference monitoring circuit.

Claims (4)

(57) [Claims] 1. A clock switching device for receiving input clocks of two systems, a working system and a standby system, at corresponding receiving units, selecting one of them and outputting it as an internal clock. A delay circuit that sequentially gives a plurality of different phase delays to each side by a predetermined delay amount, and the currently selected clock of the active system that is the switching partner.
As a reference, a comparison / selection circuit for selecting a clock having the smallest phase difference from the output of the delay circuit of the standby system with respect to the reference clock, the comparison / selected clock of the standby system, and the current clock
A single reception clock that switches between the above-mentioned reference clocks for use
Click system selection circuit and, and on the selected clock by the receiving clock system selection circuit
A simple output that eliminates the phase difference from the active clock
A non- instantaneous clock switching device, which is equipped with one phase difference absorption circuit. 2. A clock switching device for receiving input clocks of two systems, a working system and a standby system, at corresponding receiving units, selecting one of them and outputting it as an internal clock. A delay circuit that sequentially gives a plurality of different phase delays to each side by a predetermined delay amount, and the currently selected clock of the active system that is the switching partner.
As a reference, a comparison / selection circuit for selecting a clock having the smallest phase difference from the output of the delay circuit of the standby system with respect to the reference clock, the comparison / selected clock of the standby system, and the current clock
A non- instantaneous-clock-switching device for a clock, which is provided with a single phase difference absorption circuit that obtains an output that eliminates the phase difference from the system clock . 3. The comparison / selection circuit is instructed to sequentially switch and select the output of the delay circuit at predetermined time intervals so that the output of the comparison / selection circuit becomes equal to the input clock of the delay circuit. 3. The clockless instantaneous interruption switching device according to claim 1, further comprising a selection signal control circuit. 4. Two of the objects to be selected by the comparison / selection circuit
A phase difference monitor that issues an alarm if the input difference exceeds a specified value.
Claim 1 or Claim characterized by adding a visual part
2. A non-instantaneous clock switching device according to any one of 2.