JP3456074B2 - DC-DC converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter such as a down converter for converting a power supply voltage into a lower voltage.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for a low voltage (for example, V _CC / m) power supply which is independent of the power supply voltage V _CC inside the LSI, such as inter-chip and intra-chip small-amplitude transfer.

Conventionally, as a low voltage power source of this type,
A series regulator as shown in Fig. 5 is used.
ing. This series regulator is shown in Figure 5.
The inverting input (-) is a constant voltage V _LConnected to the supply line of
The operational amplifier 1 and the gate are connected to the output of the operational amplifier 1.
Source is power supply voltage V_CCIn the supply line of the
P channel M connected to non-inverting input (+) of amplifier 1
It is composed of an OS transistor 2 and has a node N₁To low
Voltage V_LIs supplied to the circuit block 3.

Now, considering the power loss of the series regulator, the p-channel M shown by the following equation
There is a loss P _LS due to the OS transistor 2.

## EQU1 ## P _LS = (V _CC −V _L ) · i _L (1) When _VL <(V _CC / 2), the loss is 50% or more, which is a large reduction in the power consumption of the LSI. It was an obstacle. In particular, the V _CC Yogaibu supply, when using a lithium ion battery, the variation in V _CC is large, the power loss becomes a problem.

Therefore, there has been proposed a DC-DC converter which can obtain a desired low-voltage power supply potential composed of only a capacitive element and a switch element without using a MOS transistor as a driver.

FIG. 6 is a circuit diagram showing a configuration example of this conventionally proposed DC-DC converter. As shown in FIG. 6 , this DC-DC converter 10 includes a switch circuit 1
1 to 13 and capacitors 21 to 23. The switch circuits 11 to 13 are, for example, MOS
It is composed of system transistors. In addition, the capacitor 2
The same capacity is used as 1 and 22.

The operating contact a of the switch circuit 11 is connected to the supply line of the power supply voltage V _CC , the operating contact b is connected to the output node ND _OUT , and the fixed contact c is connected to one electrode of the capacitor 21. The operation contact a of the switch circuit 12 is connected to the operation contact a of the switch circuit 13, the operation contact b is grounded, and the fixed contact c is connected to the other electrode of the capacitor 21. The operating contact b of the switch circuit 13 is connected to the output node ND _OUT , and the fixed contact c is connected to one electrode of the capacitor 22. The other electrode of the capacitor 22 is grounded.

The capacitor 23 is connected to the output node ND
A stabilizing capacitor connected between _OUT and the ground line for stabilizing the voltage drop at the output node ND _OUT due to the load current I _L. The stabilizing capacitor 23 need not be provided when the parasitic capacitance of the output power supply line is large.

The switch circuits 11, 12, 13 connect the fixed contact c to the operating contact a when the clock signal φ is at the V _CC level (high level), and when the clock signal φ is at the ground level (low level). The fixed contact c is connected to the working contact b.

In such a configuration, the clock signal φ
Is at a high level, the two capacitors 21 and 22 are connected in series between the supply line of the power supply voltage V _CC and the ground line, and the capacitors 21 and 22 are charged with electric charges. When the clock signal φ is at the low level, the two capacitors 21 and 22 are connected in parallel and discharging is performed. Since the capacitors 21 and 22 have the same capacitance, the output voltage Va appearing at the output node ND _OUT is caused by the charging / discharging operation described above.
_Becomes V _CC / 2 and is supplied to the circuit block 30 operating at this low voltage V _CC / 2.

[0011]

By the way, in the down converter shown in FIG. 6, when the nodes ND1 and ND2 are discharged from the power supply voltages V _CC , 0.5V _CC to 0.5V _CC , 0V, respectively, the electric power expressed by the following equation is obtained. Pd is consumed.

[0012]

[Number 2] Pd = (1/2) · (Cs1 + Cs2) · (V CC / 2) 2 · (1 / τ) ... (2) here, Cs1, Cs2 is a parasitic capacitance of the node ND1, ND2.

Similarly, the same amount of power is consumed during charging,
As a result, the total power P shown by the following equation is consumed.

[Formula 3] P = (1/4) · (Cs1 + Cs2) · (V _CC / τ) ² (3)

However, the power consumption shown by the equation (3) does not sufficiently satisfy the demand for low power consumption of the LSI, and a DC-DC converter capable of obtaining a stable output voltage with lower power loss. Realization of is desired.

The present invention has been made in view of such circumstances, and an object thereof is to provide a DC-DC converter capable of obtaining a stable output voltage with low power loss.

[0016]

In order to achieve the above object, the present invention provides a method of connecting a plurality of capacitive elements in series between an external power source and a reference power source and charging the capacitive elements.
A DC-DC converter that is connected in parallel between an output node and the reference power supply to discharge to obtain an output voltage having a value between an external power supply voltage and the reference power supply voltage.
A power supply for a potential higher than the above external power supply voltage , and above
One electrode of one of the plurality of capacitors and
Operatively connect the external power supply or the output node
First switch circuit and the other electrode of the one capacitance element
And the other electrode of the above-mentioned capacitive element,
Source, or a second switch for operatively connecting the reference power source.
Switch circuit and the above-mentioned first switch circuit when charging
Connect one electrode of one capacitive element to the above external power source.
The other electrode to the second switch circuit.
Connected to one electrode of the capacitive element,
Connect another capacitor in parallel between the output node and the reference power supply.
And turn off the first switch circuit.
The other electrode of the second switch circuit to the other electrode.
Connect to the low potential power source in place of one electrode of the capacitive element.
To the second switch circuit, and
The other electrode is replaced with the low potential power source, and the reference power source is used.
Connected to the first switch circuit,
Connect one of the electrodes of the measuring element to the output node
And means for causing discharge . Also, the above capacity
A first electrode connecting one electrode of the element and the output node
The switch circuit is turned off, and the second switch circuit is connected to the above.
Replace the other electrode of one capacitive element with the above reference power source.
After connecting to the low potential power supply, turn the second switch
The path is turned off and the one capacitance is added to the first switch circuit.
One of the electrodes is connected to the external power source
Means for causing the charging of the capacitor element and organic in further.

The DC-DC converter of the present invention is
There is at least two systems of the plurality of arrays of the plurality of capacitors in which switching between the series connection and the parallel connection of the capacitive elements is performed based on the clock signal, and the clock signal of the opposite phase is supplied to at least two systems.

Further, in the DC-DC converter of the present invention, the capacitance element is a ferroelectric capacitance, a high dielectric capacitance, M
It is composed of any one of an IM (metal-insulator-metal) structure capacitor, a DRAM trench and stack capacitor, a planar capacitor, an external capacitor, and a MOS gate capacitor.

According to the DC-DC converter of the present invention ,
A plurality of capacitive elements are connected in series between the external power source and the reference power source, and then connected in parallel, and the charging / discharging is performed by sequentially switching the connection / disconnection state from the switch means connected to the external power source. The output voltage having a value between the external power supply voltage and the reference power supply voltage is obtained.

Further, switching between series connection and parallel connection of the capacitive elements is performed based on the clock signal, and two systems of the plurality of capacitive elements are respectively driven by clock signals of opposite phases. This makes it possible to reduce the ripple associated with the load current.

Further, since the capacitive element is composed of an element having a high relative dielectric constant such as a ferroelectric capacitor, power loss can be reduced.

[0022]

1 is a block diagram of a DC-DC system according to the present invention.
It is a circuit diagram which shows 1st Embodiment of a converter. FIG. 2 is a timing chart of the circuit shown in FIG. As shown in FIG. 1, the DC-DC converter 10a is
Switch circuits 11a to 13a, capacitors 21, 22,
23, the power supply voltage V _CC external power 40,0.25V _CC power source 50, and the clock signal φ at the timing shown in FIG. 2
It is configured by a timing generation circuit 60 that generates 1 to φ7.

Switch circuit (first switch circuit) 11a
The fixed contacts c1 and c2 of the two on / off switches 111 and 112 are connected in parallel to one electrode of the capacitor 21, the operating contact a1 of the switch 111 is connected to the external power source 40, and the operation of the switch 112 is The contact a2 is connected to the output node ND _OUT . The switch 111 is on / off controlled by the clock signal φ1,
The switch 112 is on / off controlled by a clock signal φ5. Specifically, the switches 111 and 112 are turned on when the clock signal has a high level and turned off when the clock signal has a low level. These on / off operations are performed complementarily.

Switch circuit (second switch circuit) 12a
Are three on / off switches 121, 122, 123
Fixed contacts c1, c2, c3 are connected in parallel to the other electrode of the capacitor 21, and the operating contact a1 of the switch 121 is connected to the operating contact a1 of the switch 131 of the switch circuit 13a. Actuating contact a of switch 122
2 is connected to the 0.25V _CC power supply 50, and the switch 12
The operating contact a3 of 3 is grounded. The switch 121 is on / off controlled by the clock signal φ2,
The switch 122 is on / off controlled by a clock signal φ6, and the switch 123 is on / off controlled by a clock signal φ7. Specifically, the switches 121 and 12
2, 123 are in the ON state when the clock signal is at the high level, and are in the OFF state when the clock signal is at the low level. The switches 121, 122, 123 are sequentially turned on and off.

In the switch circuit 13a, the fixed contacts c1 and c2 of the two on / off switches 131 and 132 are connected in parallel to one electrode of the capacitor 22, and the operation contact a2 of the switch 132 is connected to the output node ND _OUT . It is connected. Then, the switch 131 causes the clock signal φ3.
ON / OFF is controlled by the switch 112, and the switch 112 is controlled by the clock signal φ4. Specifically, the switches 131 and 132 are turned on when the clock signal is at a high level and turned off when the clock signal is at a low level. These on / off operations are performed complementarily. The other electrode of the capacitor 22 is grounded.

The switch circuits 11a to 13a are composed of, for example, MOS transistors.

A stabilizing capacitor 23 is connected between the output node ND _OUT and the ground line to suppress the voltage drop at the output node ND _OUT due to the load current I _L. The stabilizing capacitor 23 need not be provided when the parasitic capacitance of the output power supply line is large. The capacitors 21 and 22 having the same capacitance are used.

FIG. 3 is a circuit diagram showing a configuration example of the 0.25V _CC power supply 50. This 0.25V _CC power supply 50 is
As shown in FIG. 2, it is composed of switch circuits 511 to 517 and capacitors 521 to 525. The switch circuits 511 to 517 are composed of, for example, MOS transistors. Also, the capacitors 521 to 5
As 24, those having the same capacity are used.

The operating contact a of the switch circuit 511 is connected to the supply line of the power supply voltage V _CC , the operating contact b is connected to the output node ND _OUT , and the fixed contact c is the capacitor 521.
Connected to one of the electrodes. The operating contact a of the switch circuit 512 is connected to the operating contact a of the switch circuit 513, the operating contact b is grounded, and the fixed contact c is the capacitor 5.
21 is connected to the other electrode. Switch circuit 51
The operating contact b of No. 3 is connected to the output node ND _OUT , and the fixed contact c is connected to one electrode of the capacitor 522. The operating contact a of the switch circuit 514 is the switch circuit 5
15 is connected to the working contact a, and the working contact b is grounded,
The fixed contact c is connected to the other electrode of the capacitor 522. The operating contact b of the switch circuit 515 is connected to the output node ND _OUT , and the fixed contact c is connected to one electrode of the capacitor 523. The operation contact a of the switch circuit 516 is connected to the operation contact a of the switch circuit 517, the operation contact b is connected to the output node ND _OUT , and the fixed contact c is connected to one electrode of the capacitor 524. The other electrode of the capacitor 524 is grounded.

The capacitor 525 is connected to the output node N
It is a stabilizing capacitor connected between D _OUT and the ground line for stabilizing the voltage drop of the output node ND _OUT due to the load current I _L. The stabilizing capacitor 525 need not be provided when the parasitic capacitance of the output power supply line is large.

The switch circuits 511 to 517 connect the fixed contact c to the operating contact a when the clock signal φ ₅₀ is at the V _CC level (high level), and when the clock signal φ ₅₀ is at the ground level (low level). The fixed contact c is connected to the working contact b.

In power supply 50 having such a structure, when clock signal φ ₅₀ is at a high level, four capacitors 521, 522, 523 are provided between the supply line of power supply voltage V _CC and the ground line. 524 are connected in series to charge the capacitors 521 to 524 with electric charges. When the clock signal φ ₅₀ is low level,
The four capacitors 421 to 424 are connected in parallel and discharged. Then, since the capacitor 521 to 524 is configured in what capacity is the same, the charge and discharge action described above, the output voltage Va appearing at the output node ND _OUT is V _CC /4=0.25V _CC, and the FIG. 1 Of the switch 122 of the switch circuit 12a in the circuit
2 is supplied.

The timing generating circuit 6 0, as shown in FIG. 2, initially, sets the clock signal φ1~φ3 the high level, the external power source 40 by holding the switch 111, 121, 131 in the ON state ground Two capacitors 21 and 22 are connected in series with the line to charge the capacitors 21 and 22 with electric charges. Next, at time t1, the clock signals φ1 to φ3 are switched to the low level, the clock signals φ4 and φ6 are set to the high level, the node ND2 is connected to the 0.25V _CC power supply 50, and the node ND2 is connected. Side capacitor 2
Discharging the first charge to the power supply 5 0. Then, at time t2 after a predetermined time, the clock signal φ6 is switched to the low level, the clock signal φ7 is set to the high level, the node ND2 is connected to the ground line, and the node ND1 is connected.
Causes 0.5V _CC to discharge the charge of the capacitor 21 so that the node ND2 becomes 0V. Next, at time t3, the clock signal φ5 is set to the high level to connect the node ND1 to the output node ND _OUT , and 0.5 V is applied.
_CC (V _CC / 2) is supplied to the output node ND _OUT . Further, at time t4, the clock signals φ5 and φ7 are switched to the low level, the clock signal φ6 is set to the high level, the node ND2 is connected to the 0.25V _CC power supply 50, and the node ND1 changes from 0.5V _CC to 0.5V _CC. 0.75V
_{The CC} is made to charge the capacitor 21 so that the node ND2 changes from 0V to 0.25. Next, time t5
, The clock signal φ6 is switched to the low level,
The clock signal φ1 is set to the high level and the node ND
1 is connected to the external power supply 40, the node ND1 is connected to V _CC ,
The capacitor 21 so that the node ND2 becomes 0.5V _CC
Charge the electric charge for.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. First, in the timing generation circuit 60, the clock signals φ1, φ2, and φ3 of the clock signals φ1 to φ7 are set to the high level, and the clock signal φ1 is set to the switch 111 of the switch circuit 11a.
The clock signal φ2 is supplied to the switch 121 of the switch circuit 12a, and the clock signal φ3 is supplied to the switch circuit 131. As a result, the switches 111 and 12
1, 131 are turned on, two capacitors 21 and 22 are connected in series between the external power supply 40 and the ground line, and the capacitors 21 and 22 are charged with electric charges.

Next, at time t1, the timing generation circuit 60 switches the clock signals φ1 to φ3 to the low level, sets the clock signals φ4 and φ6 to the high level, and sets the clock signal φ4 to the switch 132 of the switch circuit 13a. And the clock signal φ6 is the switch circuit 1
It is supplied to the switch 122 of 2a, respectively. As a result, switches 111, 121 and 131 are turned off, switches 132 and 122 are turned on, and supply of V _CC / 2 to capacitor 23 and circuit block 30 is started.

As the switch 122 is turned on, the node ND2 is connected to the 0.25V _CC power supply 50, and the capacitor 21 on the side connected to the node ND2 is discharged to the power supply 50. Here, the charge of 0.25V _CC (Cs1 + CS2) flows through the switch 122 to the power supply 5 0. At this time, the level of the node ND1 is 0.75
V _CC . In this case, the switch 122 consumes the power represented by the following equation.

[0037]

Equation 4] _{P 111 = (1/2) · (} Cs1 + Cs2) · (V CC / 4) 2 · (1 / τ) ... (4) Here, Cs1, Cs2 is parasitic capacitance of the node ND1, ND2 , The capacitance C _{21 of the} capacitor 21 is C ₂₁ >> Cs
1 and CS2.

Next, at time t2, the timing generation circuit 60 switches the clock signal φ6 to the low level, sets the clock signal φ7 to the high level, and supplies the clock signal φ7 to the switch 123 of the switch circuit 12a. . As a result, the switch 122 is turned off and the switch 123 is turned on.

As the switch 123 is turned on, the node ND2 is connected to the ground line. As a result, node ND1 is at 0.5V _CC and node ND2 is at 0V
The electric charge of the capacitor 21 is discharged so that
In this case, the switch 123 turns off the electric power equivalent to the electric power expressed by the equation (4). Then, at time t3, the clock signal φ5 is set to the high level by the timing generation circuit 60, and the switch 1 of the switch circuit 11a is switched.
12 are supplied. Thus, the switch 112 becomes Gao emissions <br/> _{state, 0.5V CC (V CC / 2} ) is the output node ND
Supplied on _OUT .

At time t4, the timing generation circuit 60 switches the clock signals φ5 and φ7 to low level, sets the clock signal φ6 to high level, and supplies the clock signal φ6 to the switch 122 of the switch circuit 12a. It As a result, the switches 112, 1
23 is turned off and the switch 122 is turned on.

With the switch 122 turned on, the node ND2 is connected to the 0.25V _CC power supply 50. As a result, node ND1 goes from 0.5V _CC to 0.75
To V _CC, the node ND2 is charged charges to the capacitor 21 so as to be 0.25 V _CC from 0V is performed. In this case, the switch 122 turns off the power equivalent to the power expressed by the equation (4). At this time, the electric charge of 0.25 V _CC (Cs1 + Cs2) flows from the power source 50 through the switch 122. Thus, with the 0.25V _CC power supply 50, discharge,
There is an inflow / outflow of 0.25 V _CC (Cs1 + Cs2) due to charging, and the charge is recycled. Therefore, better frequency of the clock signal phi ₅₀ of power source 50 is low, there is little power loss due to the circuit of FIG.

Next, at time t5, the timing generation circuit 60 switches the clock signal φ6 to the low level, sets the clock signal φ1 to the high level, and supplies the clock signal φ1 to the switch 111 of the switch circuit 11a. . As a result, the switch 122 is turned off and the switch 111 is turned on.

As the switch 111 is turned on, the node ND1 is connected to the external power supply 40. As a result, node ND1 is at V _CC and node ND2 is at 0.5 V
_The capacitor 21 is charged with electric charges so as to be _CC . In this case, the switch 111 uses the above (4)
The power equivalent to the power shown in the formula is extinguished.

The electric power PT consumed by the series of discharging and charging operations described above can be given by the following equation.

[Formula 5] PT = 4 × (1/2) ・ (Cs1 + Cs2) ・ (V _CC / 4) ²・ (1 / τ) = 4 × (1/8) ・ (Cs1 + Cs2) ・ V _CC ²・ (1 / Τ) (5)

This power consumption is the power consumption P of the conventional circuit.
= (1/4) · (Cs1 + CS2) · is 1/2 of (V _CC / τ) ^2.

As described above, according to the first embodiment, the two capacitors 21 and 22 are connected in series between the external power source and the reference power source (ground) by the clock signals φ1 to φ3 to charge them. , DC-D connected in parallel to obtain an output voltage Va of a value between the external power supply voltage and the reference power supply voltage
In C converter, an external power supply 40V _CC lower potential power source 5 0, and provided ground power supply, switch 121, 122 and 123 for connecting the external power source 40 and low potential power source 50 and the capacitor 21 and the operatively respectively, From the switch side connected to the external power supply, the connection and disconnection states are sequentially switched to charge and discharge the capacitor 21,
Since the circuit 50 for charging the capacitor 21 by sequentially switching the connection / non-connection state from the switch side connected to the ground power source side is provided and so-called adiabatic charging is performed, stable output with low power loss is provided. There is an advantage that a low voltage power supply that can obtain the voltage Va can be realized.

In the present embodiment, the so-called two-step charging method is used, but by adopting the n-step charging method in which the number of switches of the switch circuit 12a is increased to n, the power loss is reduced to 1 / the conventional value. can be reduced to n.

It is needless to say that the number of capacitors connected is not limited to this example, and various modes are possible. Further, the switch circuit can be composed of, for example, a CMOS type transfer gate, but it is desirable to select and use a p-channel MOS transistor and an n-channel MOS transistor according to the transfer potential.

Further, in order to reduce power loss, an external capacitor, a high dielectric capacity, MIM is used as a capacitor.
It is desirable to use a capacitor having a (metal-insulator-metal) structure, a trench for DRAM, a stack capacitor, a planar capacitor, a ferroelectric capacitor and the like. In particular, the ferroelectric substance such as PZT has a relative permittivity larger than that of SiO ₂ by two digits or more, and the parasitic capacitance can be sufficiently reduced.

FIG. 4 is a circuit diagram showing a second embodiment of the DC-DC converter according to the present invention. The second embodiment is different from the above-described first embodiment in that the A-system and B-system switch circuits and the capacitor arrays are connected in parallel, and clock signals of opposite phases (shifted by τ / 2 phase) are used. The driving is performed by φ1 to φ7 and / φ1 to / φ7 (where / indicates inversion). Since the basic operation of the circuit itself is the same as that of the first embodiment described above, its description is omitted here.

[0051] In such a configuration, the circuit of system A, for example node Nd1A, respectively ND2A V _CC, 0.75V _CC from 0.5V _CC, 0.25 V _CC
When discharging to the 0.25V _CC power source 50 via the switch 122A, in the circuit of the B system, conversely, the charging operation is performed by the same amount of charge, so that both are canceled. Therefore, the supply of electric charges from the 0.25V _CC power supply 50 is 0, and the 0.25V _CC power supply 50 has the advantage of being very stable. Output node ND _OUT accompanying load current I _L
Can reduce the ripple.

[0052]

As described above, according to the present invention,
There is an advantage that a stable output voltage can be obtained with low power loss.
Further, switching between the series connection and the parallel connection of the capacitive elements is performed based on the clock signal, and the number of the capacitive elements is 2 or more.
By driving the systems with clock signals of opposite phases, the load on the charge / recycling power supply can be significantly reduced, and the ripple associated with the load current can be reduced. Further, the power loss can be reduced by configuring the capacitive element with an element having a high relative dielectric constant such as a ferroelectric capacitance.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a DC-DC converter according to the present invention.

FIG. 2 is a timing chart of the circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration example of a 0.25V _CC power supply according to the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the DC-DC converter according to the present invention.

FIG. 5 is a circuit diagram showing a basic configuration of a series regulator as a conventional down converter.

FIG. 6 is a circuit diagram showing a configuration example of a conventional DC-DC converter.

[Explanation of symbols]

10, 10a ... DC-DC converters 11a to 13a, 11A to 13A, 11B to 13B ... Switch circuits 21 to 23, 21A to 23A, 21B to 23B ... Capacitor 40 ... External power supply 50 ... 0.25V _CC power supply 60 ... Timing Generation circuit

Claims (4)

(57) [Claims] 1. A plurality of capacitance elements are connected in series between an external power source and a reference power source for charging, and then the plurality of capacitance elements are connected.
A DC-DC converter that is connected in parallel between an output node and the reference power supply to discharge and obtain an output voltage having a value between an external power supply voltage and a reference power supply voltage, wherein the external power supply is higher than the reference power supply voltage. The power supply for the potential lower than the voltage and one of the capacitive elements among the above capacitive elements.
Actively connect the pole to the external power supply or the output node
Of the first switch circuit, the other electrode of the one capacitance element, and the other capacitance element
One electrode, the power source for the low potential, or the reference power source
And a second switch circuit that operatively connects the first switch circuit and the first switch circuit when charging.
One electrode of the element is connected to the external power source,
In the switch circuit, the other electrode is connected to the other capacitive element.
Connect to the other electrode, and during the above discharge, the other capacitive element
Connected in parallel between the output node and the reference power supply
In this state, the first switch circuit is turned off and the second switch circuit is turned off.
The other electrode of the one capacitive element is
Power source for the above low potential in place of one electrode of the other capacitive element
And the other electrode to the second switch circuit.
Connected to the reference power source instead of the low potential power source
Then, in the first switch circuit, the one capacitive element
Connect one of the electrodes to the output node to cause discharge.
And a DC-DC converter having means . 2. A first switch circuit connecting one electrode of the one capacitive element and the output node is turned off, and the other electrode of the one capacitive element is connected to the second switch circuit by the reference power source. Instead of connecting to the low-potential power supply, the second switch circuit is turned off, and the first switch circuit is connected to one electrode of the one capacitance element to the external power supply to connect the one capacitance. The DC-DC converter according to claim 1, further comprising means for charging the element. 3. At least two systems of the array of the plurality of capacitors, wherein switching between the series connection and the parallel connection of the capacitive elements is performed based on a clock signal, at least two systems are provided, and clock signals of opposite phases are provided in the at least two systems. The DC-DC converter according to claim 1, which is supplied. 4. The capacitance element is a ferroelectric capacitance, a high dielectric capacitance, a capacitance of MIM (metal-insulator-metal) configuration, D
RAM trench and stack capacitance, planar capacitance,
2. The DC-DC device according to claim 1, wherein the DC-DC device is configured by an element of either an external capacitance or a MOS gate capacitance.
converter.