JP3454175B2 - Image information transmission device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information transmitting apparatus for transmitting image information over a network having a bus structure such as Ethernet (registered trademark). FIG. 7 is a diagram showing an example of a network having a bus structure. This network is configured by connecting a plurality of terminal devices 101 to a network bus 100, and each terminal device 101 includes a control unit 102 and a communication interface 103. [0003] When one terminal device of such a network is used as an image information transmitting device and the image information of a moving image captured by a video camera or the like is subjected to information compression processing and transmitted over the network bus 100, conventionally, Was done like that. [0004] That is, as shown in FIG.
The hardware interrupt request is sent to the information compression process (for example, MPEG
1), and the CPU of the control unit 101 responds to the output from the encoder during the period T.
In step 1, the compressed image information is read from the memory, and a process of transmitting the read image information onto the network bus 100 is executed in a period T2. Japanese Patent Application Laid-Open No. 5-103181 discloses that
In order to prevent the image being transmitted from being temporarily interrupted on the receiving side due to network bus congestion, the receiving side always stores the received image data in the memory, and when the reception becomes impossible, While the image data stored in the memory is displayed again, the image data to be transmitted is stored in the memory on the transmission side, and the image data stored in the memory is transmitted from the time transmission becomes possible. A transmission system is shown. [0008] However, in the conventional method shown in FIG. 8, information is concentrated on the network bus once in a frame period, that is, in a period T2 immediately after a hardware interrupt occurs. This period T
In No. 2, the data on the bus suddenly increased, the possibility that packet collision occurred increased, and a situation where data was partially lost occurred. As a result, when the decoding process is performed on the receiving side, the image is disturbed on the way. Further, according to the system disclosed in Japanese Patent Laid-Open No. 5-103181, it is possible to avoid the disturbance (loss) of the image due to the bus congestion, but the image data is transmitted to both the receiving side and the transmitting side. It is necessary to increase the capacity of a memory for temporarily storing the data, and to add a process for switching control, which has a problem that the configuration is complicated and the cost is increased. SUMMARY OF THE INVENTION The present invention has been made to solve this problem. With a relatively simple configuration, image information can be appropriately transmitted to a network bus, and the possibility of packet collision occurring on the bus can be reduced. It is an object of the present invention to provide an image information sending device that can reduce the number of images. [0009] In order to achieve the above object, an invention according to claim 1 is connected to a network configured by connecting a plurality of terminal devices to a network bus, and the network bus is connected to the network bus. Compression encoding of incoming image information in an image information sending device that sends image information to
Compression means, and image information compressed and encoded by the compression means.
Storage means for temporarily storing information, and a file for incoming image information.
Multiple interrupt signals at specified intervals within the frame period
Interrupt signal generating means for generating the interrupt signal;
The image information is read from the storage means at each signal generation timing.
Performs the read-out operation and packetizes the read image information.
The network at intervals for each of the read operations.
And transmitting means for transmitting the data on a work bus . Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of an image information transmitting apparatus according to an embodiment of the present invention. This apparatus converts an analog image signal input from a video camera or the like into a digital signal. / D
The conversion unit 11 and an MPEG (Motion Picture Expert Group)
p) MPEG that performs image information compression processing conforming to the 1 standard
1 encoder 12 and F for storing compressed image information.
An IFO (First In First Out) memory 13 and a CPU (Central Processing Uniform) for overall control of the apparatus.
t) 15, a signal FRM (see FIG. 5B) indicating a frame period is generated based on the vertical synchronization signal VSYNC of the input image signal, and is supplied to the CPU 15 for use by the CPU control circuit 14 and the CPU 15 for calculation. RAM (Ra
ndom Access Memory) 16, an Ethernet unit 17 functioning as an Ethernet communication interface, and a FI
A FO memory 13, a CPU 15, a RAM 16, and a bus 18 for interconnecting the Ethernet unit 17 with each other;
The Ethernet unit 17 is connected to an Ethernet network bus 100. This network bus 10
A plurality of terminal devices are connected to 0 as in FIG. According to the configuration shown in FIG. 1, an input image signal is converted into a digital image signal by an A / D converter 11, and an information compression process conforming to the MPEG1 standard is performed by an MPEG1 encoder 12. The image data (elementary stream) obtained by the compression process is
It is stored in the IFO memory 13 and read out according to a request from the CPU 15. The read image data is input to the Ethernet unit 17, converted into a packet conforming to the Ethernet standard, and converted into an Ethernet IP (Intern
et Protocol) ・ TCP (Transmission control Protoc)
ol) A header is added and transmitted on the network bus 100. When image data output from the MPEG encoder 12 is stored in the FIFO memory 13,
The EG encoder 12 writes the number of bytes of data to be stored in the memory 13 to a FIFO data register 13a provided in the FIFO memory 13. The CPU 15 knows the amount of image data stored in the FIFO memory 13 by reading the contents of the FIFO data register 13a, and performs a process of reading data by this number of bytes. Then, when reading out all the data stored in the FIFO memory 13, the CPU 15 writes “0” into the FIFO data register 13a. FIG. 2 is a flowchart of a main routine executed by the CPU 15 for sending data to the network bus 100. First, in step S1,
Make initial settings such as hardware interrupts, then
The start of the PEG encoding is instructed to the MPEG1 encoder 12, and the hardware interrupt is permitted (step S2). Thereafter, the processing is interrupted until a call instruction from the memory read interrupt subroutine comes (step S3). When the MPEG1 encoder 12 starts encoding upon receiving a command from the CPU 15, a hardware interrupt is generated once in one frame period as shown in FIG. 5, and the frame interrupt subroutine shown in FIG. 3 is called. In the routine of FIG. 3, the software interrupt by the timer is permitted (step S11), and the process ends.
In the present embodiment, the timer is set so that an interrupt occurs every 時間 of the frame time. When step S11 of FIG. 3 is executed, a timer interrupt is generated every 1/5 frame, and
Is called. In step S21 of FIG. 4, the contents of the FIFO data register 13a are read, and at that time the FIFO data register 13a is read.
The amount of data stored in the O memory 13 is known. This data amount is stored in the memory area FHD of the RAM 16 managed by the CPU 15. In the following step S22, FI
Data amount (fixed value) RDN to be read from FO memory 13
Is determined in advance, and then it is determined whether (FHD-RDN) is 0 or more (step S23). In step S23, (FHD-RDN) ≧ 0
, The data of the data amount RDN is read out from the FIFO memory 13 and the RAM 16 managed by the CPU 15 is read.
(Step S2)
4). Next, the value of (FHD-RDN) is written into the FIFO data register 13a (step S25), the main routine of FIG. 2 is called (step S26), and this processing ends. On the other hand, in step S23, (FHD-RDN)
If <0, the data of the data amount FHD is
The data is read from the memory 13 and stored in the memory area DAREA (step S27). Next, "0" is written into the FIFO data register 13a (step S28), the timer interrupt is prohibited, and the main routine is called (step S29), and this processing ends. Returning to FIG. 2, in the main routine called from the memory read interrupt subroutine, the processing is restarted, data is read from the memory area DAREA of the RAM 16 and supplied to the Ethernet unit 17 and the Ethernet unit 17 Instruct processing such as addition of an IP / TCP header and transmission of data to the network bus 100 (steps S4 and S5). By repeating the above-described series of operations (operations in which a hardware interrupt is generated once per frame and then a timer interrupt is generated every 1/5 frame), as shown in FIG. Subsequent to the read process (memory read subroutine) P1 from the FIFO memory 13, the main routine data transmission process P2 is repeatedly executed, and data is transmitted every １ ／ frame period as shown in FIG. You. That is, in the present embodiment, the image information corresponding to one frame is divided into five pieces of partial image information corresponding to １ ／ frame, and distributed to the network bus 100 within one frame period. As compared with the case where data is transmitted once per one frame period as described above, the possibility of packet collision or loss can be reduced, and image disturbance on the receiving side can be prevented. The present invention is not limited to the above-described embodiment, but can be variously modified. For example, in the above-described embodiment, the cycle of the timer interrupt is set to 1/5 frame period. However, the present invention is not limited to this, and may be longer or shorter. By shortening the cycle of the timer interrupt, the amount of data transmitted at one time is reduced, so that the possibility of packet collision can be further reduced. As shown in FIG. 6, the vertical synchronizing signal VS
A hardware interrupt is generated using a counter based on YNC (FIG. 4B), and the memory read interrupt process shown in FIG.
1) The read data may be transmitted to the network bus 100 (P2). [0023] According to the present invention, as described above in detail, according to the present invention, off
A rate that is generated multiple times at predetermined intervals during the frame period
Image information at intervals of the
Since the packet is transmitted to the network bus, it is possible to reduce the possibility of occurrence of packet collision on the bus and to prevent the image from being distorted on the receiving side.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a main part of an image information transmitting device according to an embodiment of the present invention. FIG. 2 is a flowchart of a main routine executed by a CPU in FIG. 1; FIG. 3 is a flowchart of a frame interrupt process that occurs once in one frame period. FIG. 4 is a flowchart of a timer interrupt process. FIG. 5 is a time chart for explaining data transmission timing. FIG. 6 is a time chart for explaining data transmission timing. FIG. 7 is a diagram illustrating an example of a network having a bus structure. FIG. 8 is a time chart for explaining a conventional image information transmission process. [Description of Signs] 12 MPEG1 encoder 13 FIFO memory 14 CPU control circuit 15 CPU 16 RAM 17 Ethernet unit

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Claims (1)

(57) is connected to the Claims 1 network configured by a plurality of terminal devices to the network bus are connected, the image information transmitting apparatus for transmitting image information on the network bus, input Compression means for compressing and encoding incoming image information; and temporarily storing the image information compressed and encoded by the compression means.
Storage means, and a plurality of divisions within a frame period of incoming image information.
Interrupt signal generation method for generating an interrupt signal at predetermined intervals
And the storage means for each of the interrupt signal generation timings.
Image information readout operation from the
Packetize information and leave an interval for each read operation
Transmission means for transmitting the data on the network bus
Image information sending apparatus, characterized in that the.