JP3446056B2 - Data division device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data recording / reproducing apparatus for recording / reproducing digital data, and more particularly to a data dividing apparatus for digital data used in the digital data recording / reproducing apparatus or the like.

[0002]

2. Description of the Related Art With the recent increase in the size of home color television screens, the image quality of recording / reproducing media for video signals has been improved. Also, as a storage medium for recording and reproducing high-quality images with high image quality, a digital magnetic recording / reproducing device for home use (hereinafter referred to as a digital magnetic recording / reproducing device that digitizes a video signal and performs band compression (high efficiency coding) on the recording / reproducing) , Digital VTR) are being actively developed by each company.

Regarding the conventional recording / reproducing system of a home digital VTR, IEEE Transactionson Consumer Electro
nics, Vol. 34, No3 (AUGUST, 1988) PP.597-605 "A
NEXPERIMENTAL DIGITAL VCR WITH 40MM DURM, SINGLE A
The recording / reproducing system of Philips Corporation described in "CTUATOR AND DCT-BASED BIT-RATE REDUCTION" will be described.

FIG. 1 shows a block diagram of a recording system of a conventional home digital VTR. It should be noted that this system adopts a 2-channel recording system. In Figure 1
Reference numerals 1a to 1c are input terminals, 2a to 2c are A / D converters for converting analog data into digital data, and 3 is high efficiency encoding for applying high efficiency encoding to the input luminance signal Y, color signals CB and CR. Circuits 4 are error correction code circuits for adding error correction codes for correcting or detecting an error occurring during reproduction to the 2-channel data output from the high efficiency coding circuit 3, and 5a and 5b are error correction code circuits. A digital modulation circuit for digitally modulating the data output from 4, 6
Reference numerals a and 6b are sync signal adding circuits for adding a sync signal and an ID signal, 7a and 7b are recording amplifiers, 8a and 8b are rotary heads, and 9 is a magnetic tape.

FIG. 2 shows a block diagram of a reproducing system of a conventional home digital VTR. In FIG. 2, 8a, 8b and 9 are the same as those shown in FIG. Reference numerals 10a and 10b are head amplifiers for amplifying signals reproduced by the rotary heads 8a and 8b, 11a and 11b are data detection circuits for detecting data from the reproduction signals and detecting and correcting the jitter of the reproduction signals, and 12a and 12b are digital signals. A demodulation circuit, 13 is an error correction decoding circuit for correcting and detecting an error in the reproduced signal, 14
Performs high-efficiency decoding on the output of the error correction decoding circuit 13,
High-efficiency decoding circuit for restoring video signals, 15a to 15c are D / A converters for converting digital signals into analog signals,
16a to 16c are output terminals.

FIG. 3 shows a block diagram of a conventional high efficiency coding circuit 3 described in the above document. In FIG. 3, 17a and 17b are field memories, and 18 is a discrete cosine transform (hereinafter referred to as DCT) for the data of each block which is output from the field memories 17a and 17b after being divided into predetermined blocks. DCT circuit, 19 is DC
An adaptive quantizer that quantizes each coefficient converted by the T circuit 18, 20 is a variable length encoder that performs variable length coding on the output of the adaptive quantizer 19, and 21 is the variable length encoder 20. A buffer memory for changing the output to a fixed rate output, 22 is a component to be encoded by the variable length encoder 20 while switching the quantization parameter of the adaptive quantizer 19 so that the buffer memory 21 does not overflow. Is a buffer controller for selecting the. Field memories 17a, 17b, DCT circuit 1
The high-efficiency encoding circuit 3 is composed of the adaptive quantizer 19, the variable-length encoder 20, the buffer memory 21, and the buffer controller 22.

FIG. 4 shows a block diagram of a conventional high efficiency decoding circuit 14. In FIG. 4, 23 is a variable length decoder that converts variable length coded data into original fixed length data, and 24 is a buffer that outputs the output of the variable length decoder 23 at a fixed rate. Memory, 25 is an inverse adaptive quantizer, 26
Is an inverse DCT circuit that applies inverse discrete cosine transform (hereinafter referred to as inverse DCT) to the data output from the inverse adaptive quantizer 25, and 27a and 27b delay the reproduced digital signal output from the inverse DCT circuit 26 by a predetermined amount. Then, it is a field memory that decodes and outputs the blocking made at the time of recording. Variable length decoder 23, buffer memory 24, inverse adaptive quantizer 2
5, the inverse DCT circuit 26 and the field memories 27a and 27b constitute the high efficiency decoding circuit 14.

Next, the operation of the recording system will be described with reference to FIG. Luminance signal Y input from the input terminals 1a to 1c,
And the two color signals CR and CB are A / D converters 2a to 2c
The D / D conversion is performed, and the recording bit rate is reduced by the high efficiency encoding circuit 3. The detailed operation of the high efficiency encoding circuit 3 will be described later. The data whose recording bit rate has been reduced by the high-efficiency encoding circuit 3 is added to the recording signal by the error-correcting encoding circuit 4 for producing an error-correcting code for correcting and detecting an error occurring during reproduction. The recorded digital signal to which the error correction code (hereinafter referred to as check) is added by the error correction code circuit 4 is the digital modulation circuit 5a,
In 5b, the low frequency component of the recording signal is suppressed according to a predetermined modulation rule (digital modulation). The recorded digital data subjected to digital modulation is added with a synchronizing signal and an ID signal by synchronizing signal adding circuits 6a and 6b, amplified by recording amplifiers 7a and 7b, and then magnetic tapes are passed through rotary heads 8a and 8b. 9
Recorded above.

Similarly, the operation of the reproducing system will be described with reference to FIG. The two-channel reproduction signal reproduced from the magnetic tape 9 via the rotary heads 8a and 8b is supplied to the head amplifier 10a, and
After being amplified by 10b, it is converted into digital data by the data detection circuits 11a and 11b, and the jitter (time axis error) of the reproduced signal is absorbed. Then, it is digitally demodulated by the digital demodulation circuits 12a and 12b, converted into a reproduced digital signal, and input to the error correction decoding circuit 13.
The error correction decoding circuit 13 corrects or detects an error generated in the reproduced signal based on the check added in advance at the time of recording. The reproduced signal that has been subjected to error correction or detection in the error correction decoding circuit 13 is subjected to processing such as variable length decoding and inverse DCT conversion in the high efficiency decoding circuit 14, and then the original luminance signal Y and The two color signals CB and CR are restored. Then, it is converted into analog data by the D / A converters 15a to 15c and output from the output terminals 16a to 16c.

Next, the operation of the high efficiency coding circuit 3 will be described with reference to FIG. The input luminance signal Y and the two color signals CR and CB are delayed by a predetermined amount by the field memories 17a and 17b to be blocked. Blocking is
First, each input signal is divided into blocks of 8 pixels × 8 lines. The blocked luminance signal Y and the two color signals CR and CB are time-division multiplexed and D
It is input to the CT circuit 18. The DCT circuit 18 performs DCT on the outputs of the field memories 17a and 17b that have been divided into blocks. That is, each pixel data of the block is X (i, j) (i = 0, 1, ..., 7; j = 0,
When expressed as 1 ..., 7), the DCT circuit 18 first has a horizontal 8-point DCT, that is,

[0011]

[Equation 1]

Then, this converted data f is calculated.
(M, j) (m = 0, ..., 7; j = 0, ...,
For 7), perform 8-point DCT in the vertical direction,

[0013]

[Equation 2]

Then, the conversion coefficient F (m, n) (m =
0, ..., 7; n = 0, ..., 7) is output. The conversion coefficient F (m, n) thus obtained has a smaller value of m, n as a coefficient value for determining the basic image quality, and is a low-order component including DC. Further, the larger the values of m and n are, the higher order components are, and the image quality is a coefficient value representing high definition information.

Each transform coefficient output from the DCT circuit 18 is quantized by the adaptive quantizer 19. This adaptive quantizer
19 holds a plurality of quantization tables having different quantization steps, and switches the quantization steps according to the transform coefficient of each block and the parameter from the buffer memory 21. For example, the rising portion of high contrast is quantized coarsely, and the detail portion of small amplitude is finely quantized. The output of the adaptive quantizer 19 is variable-length coded by the variable-length encoder 20 and input to the buffer memory 21. Buffer memory 21
The data stored in is read at a fixed rate. The buffer controller 22 detects the data stored in the buffer memory 21, determines the quantization parameter according to the amount of the data, and controls the adaptive quantizer 19. Further, the buffer controller 22 selects a transform coefficient to be encoded by the variable length encoder 20 according to the amount of data stored in the buffer memory 21.

Next, the operation of the high efficiency decoding circuit 14 will be described with reference to FIG. The reproduced digital signal output from the error correction decoding circuit 13 is variable length decoded by the variable length decoder 23 and converted into fixed length data. The buffer memory 24 reads the variable-length decoded fixed-length data at a fixed rate. The fixed-length data read from the buffer memory 24 is inversely quantized by the inverse adaptive quantizer 25, and inverse D
It is input to the CT circuit 26. The inverse DCT circuit 26 subjects the input reproduced digital signal to inverse DCT. The reproduced luminance signal Y subjected to the inverse DCT and the two reproduced color signals CB and CR are temporarily stored in the field memories 27a and 27b, delayed by a predetermined amount, and then the block formation applied at the time of recording is decoded. It is output to the D / A converters 15a to 15c.

FIG. 5 shows a pattern of recording tracks formed on the magnetic tape 9 of a digital VTR adopting the conventional two-channel recording system. In this example, FIG.
It is assumed that 2-channel data is simultaneously recorded on the magnetic tape 9 as shown in FIG. In addition, A, marked in the figure,
B indicates recording tracks formed by rotary heads having different channels. The rotary heads of the respective channels have different azimuth angles.

[0018]

DISCLOSURE OF THE INVENTION Conventional digital VT
R is configured as described above, and when an editing operation is performed using a digital VTR having such a recording format, the editing operation is performed as shown in FIG. 6 due to problems such as servo accuracy or track bending peculiar to the VTR. At the cut-in point (or cut-out point), the track of one channel recorded in advance may be overwritten and destroyed. As described above, when the reproduction is performed with the track of one channel being crushed, there is a problem that about half of the image data of one field is not reproduced and a good reproduced image cannot be obtained.

Therefore, as a method of producing a reproduced image to some extent even when one track is completely crushed as described above, there is a method of using an interleave format represented by a digital audio tape recorder. This is a method of recording even-numbered sample data on the track of one channel and recording odd-numbered sample data on the track of the other channel. For example, when the information of the track of channel A is not reproduced ( Even when overwritten and crushed), the information recorded in the channel A is restored using the information of the track of the channel B by using the interpolation process.

However, the digital VTR shown in this prior art example
In this case, since band compression (high-efficiency coding) is performed by DCT conversion, variable-length coding, or the like, if the above-mentioned conversion coefficients are alternately divided into two channels, the data of one channel is If it has not been reproduced, it is difficult to obtain all conversion coefficients by interpolation processing,
There is a problem that a good reproduced image cannot be obtained at the joint of editing. Further, if each data is simply written twice on each track, there is a problem that the redundancy of the recorded data is increased.

The present invention has been made in view of the above circumstances, and an object of the present invention is to effectively increase the redundancy of data that has been band-compressed (highly efficient coded). It is to provide a data division device that can be divided into.
Another object of the present invention is to provide a data division device capable of reproducing a reproduced image without disturbing even a joint of editing such as a cut-in point (or a cut-out point).

[0022]

A first data division device of the present invention (claims 1 and 2 ) performs an operation on input digital data in accordance with a predetermined method, and two main codes and a sub code. It is configured to be divided into and. Specifically, the input digital data X is converted into X = 2 ^n-1 ×
Main code Y calculated by the method of (Y1 + Y2) + Z
1, Y2 and subcode Z. However, Y1,
For Y2 and Z, the values calculated according to the following method are used (claim 1 ). Y1 = INT (X / ²ⁿ ) Y2 = INT (X / ^2n-1 ) -INT (X / ²ⁿ ) Z = X mod ^2n-1 where INT (A / B): A divided by B Quotient A mod B: remainder when A is divided by B

Alternatively, the input digital data X is divided into two main codes Y1 and Y2 (having the same value) calculated by the method of 2 ⁿ × Y1 (or Y2) + Z, and a sub code Z. However, Y1 (or Y2) and Z use the values calculated according to the following method (claim)
2 ). Y1 (or Y2) = INT (X / 2 ⁿ ) Z = X mod 2 ⁿ where INT (A / B): quotient when A is divided by B A mod B: remainder when A is divided by B

A second data dividing device of the present invention is as follows.
3 , 4 , 5 ), where D is the input digital data and X ₀ , X ₁ , ..., X _n-1 are the converted n output codes, D, X ₀ , X ₁ ..., X The relationship of _n-1 is D = K ₀ X
₀ + K ₁ X ₁ + ... + K _n-1 X _n-1 (K ₀ , K ₁ , ..., K
_n-1 is a real number) based on the rule that the input digital data D is converted into output codes X ₀ , X ₁ , ..., X _n-1 and n output codes are combined into two channels. Channel combining means.

In the second data division device, the input digital data D is converted into two output codes X and Y (claim 4 ), and the relationship between D, X and Y is D = 2X + Y or D = 3X + Y (claims
5 ).

A third data dividing device of the present invention is as follows.
6 , 7 ), a conversion means for converting the input digital data into n output codes based on the following rules and outputting the output code, and a channel combining means for combining the n output codes into two channels. Have. All input digital data is divided into a set including at most t (t is an integer) different input digital data, and each digital data in one set is an output code having m ₀ different values. Output code X with X ₀ and m ₁ different values
₁ ... uniquely expressed by the combination of the output data X _n-1 with m _n-1 pieces of different values _{(m 0, m 1, ...} , m n-1 is an integer, m ₀ × m ₁ × ... × m _n-1 ≧ n), output codes X ₀ , X ₁ , representing digital data in a certain set,
The combination of the values of X _n-1 is not a combination that represents other digital data.

Further, the conversion means in the third data division device converts all the input digital data for converting the input digital data based on the following rules into a set in which one set includes four different input digital data. Divide,
Each digital data in one set can be uniquely expressed by combining an output code X having two different values and an output code Y having two different values, and digital data in a certain set can be represented. The combination of the values of the output codes X and Y to be represented should not be the combination to represent other digital data (claim 7 ).

A fourth data division device of the present invention is as follows.
8 ) The input data is divided into a plurality of pieces of data that satisfy the following conditions so that the pieces of data can be distributed and recorded on a plurality of tracks. The condition is that D = c × X ^a holds for at least one post-division data X and input data D, and D = b × Y holds for at least one post-division data Y and input data D. . (However, a, b, c: constant)

A fifth data dividing device of the present invention is as follows.
In the fourth data division device, the input data D is divided into two pieces of data D1 and D2 satisfying the following relational expression, and divided into two tracks so as to be recorded. Relation 1 D = X ^a + b × Y + Z Relation 2 D1 = c × X ^a , D2 = b × Y + Z or D1 = c × X ^a + Z, D2 = b × Y where a, b, c: constants

A sixth data dividing device of the present invention is as follows.
11, 12 ), in the fifth data division device, a data failure in a recording / transmission medium such as that found in a specific recording track which is damaged at a cut-in point or a cut-out point during editing. When the data is output to the recording / transmission device whose occurrence probability is not uniform at that position, the data D1 is output to the position where the failure occurrence probability is low, and the data D2 is output to the position where the failure occurrence probability is high. Constitute.

A seventh data division device of the present invention is as follows.
13 ) In the fifth data division device, for example, the division operation is performed only on the DCT low-order data portion that determines the basic image quality, and the division operation is performed only on a part of the input data.

[0032]

In the first to third and fifth data division devices of the present invention,
Since the original digital value can be almost restored by only one main code or one divided data at the time of reproduction, band compression (high efficiency encoding) is performed by DCT conversion or the like like the digital VTR shown in the conventional example. The data can be effectively divided into two, and the track of one channel that was recorded in advance was overwritten at the cut-in point (or cut-out point) when the editing operation was performed, and the data was crushed. Even if
At the time of reproduction, since the original digital value can be almost restored by the one main code or the one divided data, the reproduced image can be reproduced without disturbing the edit joint such as the cut-in point (or cut-out point). It becomes possible.

Further, since each data is not simply written twice on the written track, it is possible to suppress an increase in the redundancy of the recorded data. In addition, even in the case of dropout, scratches on the magnetic tape, or clogging of the rotary head, if the main code of one of the above can be reproduced, the original digital value can be almost restored, so band compression (high efficiency encoding) is performed. Even if such a digital image is present, interpolation processing at the time of dropout and the like can be performed, and a good reproduced image can be obtained.

In the fourth data dividing apparatus of the present invention, one piece of data can be divided into a plurality of pieces, and the total amount of divided data can minimize the increment of the recorded data (increase in redundancy). It is possible to recover the pre-division data from at least one post-division data among the post-division data, and the error becomes smaller as the number of obtained post-division data increases, and it can be completely restored when all the data are obtained. Therefore, for example, it is possible to obtain a reproduced image according to the ratio of the tracks that have been successfully reproduced in all the reproduced tracks. In an extreme example, even if there is a defective reproduction head due to clogging or the like among a plurality of recording heads, it is possible to output reproduced images according to the number of remaining normally reproducible heads.

In the sixth data dividing apparatus of the present invention, the data D2 is assigned to the data D2 after the division when the trouble occurrence position is known in advance in the recording medium or where the trouble occurrence probability is particularly high. By increasing the normal reproduction rate on the D1 side, it is possible to improve the restoration accuracy from one data as a whole. In the seventh data division device of the present invention, the restoration operation at the time of occurrence of a failure can be performed, and the data amount can be suppressed to the minimum necessary amount.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. FIG. 7 shows a block diagram of a recording system of a digital VTR equipped with the data dividing device of the present invention.
7 are the same as those shown in FIG. 1 and the description thereof is omitted. 30 is a high efficiency encoding circuit of the present invention.

FIG. 8 shows a data splitting device 2 according to the present invention.
FIG. 3 is a block diagram of a reproduction system of a digital VTR equipped with a data division decoding device for decoding a divided reproduction digital signal. In FIG. 8, the parts given the same numbers as in FIG. 2 are the same as those shown in FIG.
40 is a high efficiency decoding circuit of the present invention.

First Embodiment FIG. 9 shows a block diagram of a high efficiency coding circuit 30 according to the first embodiment of the present invention. In FIG. 9, 17a, 17b, 18 and 19 are the same as those shown in FIG. 31
Is a data division coding circuit that divides the input digital data into two, 32a and 32b are variable length encoders, and 33a and 33b are subcodes (details will be described later) output from the data division coding circuit 31 and variable. Adders that mix with the main code output from the long encoders 32a and 32b (similar to subcodes, details will be described later), and 34a and 34b output the outputs of the adders 33a and 33b at a fixed rate. Buffer memory,
Reference numerals 35a and 35b are buffer controllers that switch the quantization parameter of the adaptive quantizer 19 and select the components to be encoded by the variable length encoders 32a and 32b so that the buffer memories 34a and 34b do not overflow. As described above, the field memories 17a and 17b, the DCT circuit 18, the adaptive quantizer 19, the data division encoding circuit circuit 31, the variable length encoders 32a and 32b,
The high efficiency coding circuit 30 is configured by the adders 33a and 33b, the buffer memories 34a and 34b, and the fabber controllers 35a and 35b.

FIG. 10 shows a block diagram of the data division coding circuit 31 of the first embodiment of the present invention. In this embodiment, 11-bit input data is converted into 5-bit main code 2
First, the case of dividing into 5-bit subcodes will be described. In FIG. 10, 36 is an 11-bit data latch circuit, 37 is an adder, and 38a to 38c are data latch circuits. A data division encoding circuit 31 is configured by the data latch circuits 36, 38a to 38c and the adder 37.

FIG. 11 is a block diagram of the high efficiency decoding circuit 40 according to the first embodiment of the present invention. In the figure 25, 26, 27
Since a and 27b are the same as those shown in FIG. 4, description thereof will be omitted. 41a and 41b are variable-length decoders that convert the variable-length coded main code data to the original fixed-length data, and 42a and 42b are outputs of the variable-length decoders 41a and 41b at a fixed rate. , 43a, 43b delay the subcode data by a predetermined amount and match it with the output timing of the main code, and 44 shows the original digital signal from the reproduction signal divided into the main code and the subcode. It is a data division decoding circuit for restoration. Variable length decoders 41a, 41b, buffer memories 42a, 42b, 43a, 43b, data division decoding circuit 44, inverse adaptive quantizer 25, inverse DCT circuit
26 and high efficiency decoding circuit with field memories 27a and 27b
40 is made up.

FIG. 12 shows a block diagram of the data division decoding circuit 44 of the first embodiment of the present invention. This embodiment is shown in FIG.
3 is a configuration example of a circuit for restoring digital data divided into two main codes and sub codes by a data division encoding circuit 31 shown in FIG. 45a to 45c are data latch circuits, 46a and 46b are selectors, 47 is an adder, 48 is a selector, and 49 is a data latch circuit. Data latch circuit 45
The data division decoding circuit 44 is composed of a to 45c, 49, selectors 46a, 46b, 48, and an adder 47.

Next, the operation of the recording system will be described with reference to FIG. Luminance signal Y input from the input terminals 1a to 1c,
And the two color signals CR and CB are A / D converters 2a to 2c
The data is D / D converted and input to the high efficiency encoding circuit 30. The high-efficiency encoding circuit 30 divides the input digital data into two, reduces the recording bit rate, and outputs it. The detailed operation of the high efficiency encoding circuit 30 will be described later. The data whose recording bit rate has been reduced by the high-efficiency encoding circuit 30 is added to the recording signal by the error-correcting encoding circuit 4 for producing an error-correcting code for correcting and detecting an error occurring during reproduction. The low-frequency component of the recorded digital signal checked by the error correction coding circuit 4 is suppressed by the digital modulation circuits 5a and 5b according to a predetermined modulation rule. The recorded digital data subjected to digital modulation is added with a synchronizing signal and an ID signal by synchronizing signal adding circuits 6a and 6b, amplified by recording amplifiers 7a and 7b, and then the rotary head.
It is recorded on the magnetic tape 9 via 8a and 8b.

Similarly, the operation of the reproducing system will be described with reference to FIG. The 2-channel reproduction signal reproduced from the magnetic tape 9 through the rotary heads 8a and 8b is amplified by the head amplifiers 10a and 10b, and then converted into digital data by the data detection circuits 11a and 11b. The jitter it has is absorbed. Then, it is digitally demodulated by the digital demodulation circuits 12a and 12b, converted into a reproduced digital signal, and input to the error correction decoding circuit 13. The error correction decoding circuit 13 corrects or detects an error generated in the reproduced signal based on the check added in advance during recording.

The reproduced signal which has been error-corrected or detected by the error correction decoding circuit 13 is subjected to variable length decoding of reproduced digital data of each channel by the high-efficiency decoding circuit 40, and by the data division encoding circuit 31 at the time of recording. The original luminance signal Y and the two color signals CB and CR are restored by performing processing such as synthesis of data divided into two main codes and sub codes and inverse DCT conversion. High-efficiency decoding circuit
The detailed operation of 40 will be described later together with the decoding of the divided data. Then, it is converted into analog data by the D / A converters 15a to 15c and output from the output terminals 16a to 16c.

Next, the operation of the high efficiency coding circuit 30 will be described with reference to FIG. The input luminance signal Y and the two color signals CR and CB are delayed by a predetermined amount by the field memories 17a and 17b to be blocked. In the block formation, each input signal is first divided into blocks of 8 pixels × 8 lines.

Then, the luminance signal Y which has been divided into blocks
And the two color signals CR and CB are time-division multiplexed and input to the DCT circuit 18. The DCT circuit 18 performs DCT on the outputs of the field memories 17a and 17b that have been divided into blocks. Each transform coefficient output from the DCT circuit 18 is quantized by the adaptive quantizer 19. The adaptive quantizer 19 holds a plurality of quantization tables having different quantization steps, and switches the quantization steps according to the transform coefficient of each block and the parameters from the buffer memories 34a and 34b. The output of the adaptive quantizer 19 is input to the data division coding circuit 31.

Hereinafter, the data division coding circuit 31 of this embodiment will be described.
The detailed operation of will be described. Now, data division coding circuit
Assuming that the value of the digital data input to 31 is X, the data division coding circuit 31 divides the data into two according to the following method.

The digital data X input to the data division circuit 31 is divided into main codes Y1 and Y2 and a subcode Z calculated by the method of X = 2 ^n-1 × (Y1 + Y2) + Z. However, Y1, Y2, and Z shall use the value calculated according to the following method. Y1 = INT (X / ²ⁿ ) (1) Y2 = INT (X / ^2n-1 ) -INT (X / ²ⁿ ) (2) Z = X mod ^2n-1 (3) However, INT (A / B) is the quotient when A is divided by B, and A mod B is the remainder when A is divided by B.

The above division rule will be described using specific numerical values. For example, assume that data having a digital value of 395 is input to the data division encoding circuit 31. In addition,
In this embodiment, n = 6. The input digital data is converted into the two main codes Y1 and Y2 and the sub code Z according to the above-mentioned formula (1), formula (2) and formula (3). That is, the ^{Y1 = INT (395/2 6} ) = 6 Y2 = INT (395/2 5) -INT (395/2 6) = 6 Z = 395 mod 2 5 = 11. The original digital value X is X = 2 ⁵ ×
(6 + 6) + 11 = 395, which means that it can be completely restored.

Further, according to this division method, the input digital value X can be almost restored from the main code Y1 or Y2 according to the following formula. Now, if the restoration value is X ', then X' = Y1 (or Y2) × 2 ⁿ (4). In the case of this example, X ′ = 6 × 2 ⁶ = 384 is obtained according to the equation (4), and it can be seen that the input digital value X can be almost restored only by the main code Y1 or Y2.

Further, according to this division method, the conventional method 2
The amount of data to be transmitted is greater than that in the case of multiple writing and transmission.
When the number of bits of the digital data input to the data division encoding circuit 31 is m bits, the number of transmission bits is (m−n) bits for the main codes Y1 and Y2 and the sub code when the present system is adopted. Z becomes (n-1 bits. Therefore, when the input digital data is 11 bits, the total number of transmission bits is 15 bits after being divided by 2. Note that n is 6. Therefore, the conventional 2 The transmission bit rate is reduced compared to the overwriting.

Next, FIG. 10 shows an embodiment in which the above division rule is made into a circuit. In this embodiment, 11-bit input digital data is divided into a 5-bit main code and a 5-bit sub-code according to the above division rule.

The operation of the data division coding circuit 31 will be described below. The input 11-bit digital data X is latched by the data latch circuit 36 and input to the adder 37 and the data latch circuit 38a. The data latch circuit 38a executes INT (X / 2 ⁶ ) shown in Expression (1). In this embodiment, which deals with binary numbers (binary data), when executing the equation (1), the input data may be shifted to the right by n bits and the fractional part may be truncated. For example, if the above-mentioned 395 is represented by binary data, it becomes 00110001011. Therefore, in the case of this binary representation, the operation result of INT (375/2 ⁶ ) is 00110 because the data may be shifted to the right by 6 bits and the fractional part is discarded, so that 5 bits are selected from MSB.

Similarly, in the adder 37, INT (X
/ 2 ^6-1 ) -INT (X / 2 ⁶ ) is executed. (Although explanation is omitted, the result of INT (X / 2 ⁶ ) shows ⁶ from MSB.
A similar operation result can be obtained by adding the bit data. ) Specifically, the operation of adding 00000 to 00110 is performed and the operation result of 00110 is obtained.

Similarly, since (X mod 2 ⁵ ) in the equation (3) is the remainder when X is divided by 2 ⁵ , 5 bits may be output from the LSB. Therefore, (395 mod ²⁵ )
The calculation result of is 01011. The sub-code data division method is to collect one or a plurality of sub-codes and divide them into 1 channel or 2 channels in units of a plurality of bits. (For example, each bit is alternately divided into two channels and divided.)

2 divided by the data division encoding circuit 31
The main code of the channel is variable length coded by the variable length encoders 32a and 32b and input to the adders 33a and 33b. In the adders 33a and 33b, the main code data subjected to the variable length coding and the subcode divided into two by the data division coding circuit 31 are mixed to generate two-channel recording data. The buffer memories 34a and 34b temporarily store the data output from the adders 33a and 33b and read it at a fixed rate. The buffer controller 35a, 35b is a buffer memory
The data stored in 34a and 34b is detected, the quantization parameter is determined by the amount of the data, and the adaptive quantizer 19 is controlled. The buffer controllers 35a and 35b also select transform coefficients to be encoded by the variable length encoders 32a and 32b according to the amount of data stored in the buffer memories 34a and 34b.

Similarly, the operation of the high efficiency decoding circuit 40 will be described with reference to FIG. 2 output from the error correction decoding circuit 13
After the main code and the sub code are separated from the reproduced digital signal of the channel, the main code is input to the variable length decoders 41a and 41b, and the sub code is input to the buffer memories 43a and 43b. The main code input to the variable length decoders 41a and 41b is subjected to variable length decoding and converted into a fixed length main code. In the buffer memories 42a and 42b, the variable-length decoded fixed-length main code is read at a fixed rate. On the other hand, the subcodes input to the buffer memories 43a and 43b are output to the data division decoding circuit 44 in time with the fixed rate main code read from the buffer memories 42a and 42b.

Hereinafter, the data division decoding circuit 44 of this embodiment will be described.
The operation will be described in detail with reference to FIG. The data input to the data division decoding circuit 44 is restored by the following method. When the restoration value is X, it is restored to the value calculated by X = 2 ⁵ × (Y1 + Y2) + Z (5) or X = 2 ⁶ × Y1 (or Y2) (6). This is, for example, the respective code data (Y1, Y2,
And Z) are all reproduced, the data is output according to the method of equation (5).

However, when the data of one channel is not reproduced at the discontinuity point of the track pattern such as the cut-in point (or cut-out point) at the time of editing explained in the conventional example, the method of equation (6) is followed. Output the data. In the case of selecting the equation (6) is, Y1 or Y2 is assumed to use the data of those who have decent play. Further, in the present embodiment, the switching between the equations (5) and (6) uses the error detection flag output from the error correction decoding circuit 13.

First, the main code and sub code reproduced from each channel are temporarily latched by the data latch circuits 45a to 45c. Then, the data latch circuits 45a and 45b
The two-channel main codes Y1 and Y2 output from the two channels are input to both the selector 46a and the adder 47, respectively. The adder 47 adds both the input 5-bit main codes and outputs as 6-bit digital data. (Execute Y1 + Y2.) The 6-bit digital data output from the adder 47 is input to the selector 48. On the other hand, the main code Y input to the selector 46a
The output data of 1 and Y2 are switched by the error detection flag output from the error correction decoding circuit 13. (Select the one that has no mistakes.)

Outputs from the adder 47 and the selector 46a (note that the output from the selector 46a is added to the least significant bit "0" and 6-bit data (2 × Y1 (or Y2) is executed) is sent to the selector 48. Is output), when an error is detected in the reproduced digital signal by the selector 48, the output of the selector 46a is selected, and when the error is not detected, the output of the adder 47 is selected. Similarly, the selector 46b is configured to select 00000 when an error is detected in the reproduced digital signal and select a subcode when no error is detected. The outputs of the selector 48 and the selector 46a are mixed by the latch circuit 49 (2
⁵ * (Y1 + Y2) + Z, or 2 * ⁵ * 2 * Y1 (or Y2) is executed) and the restored reproduction digital data is output.

The restored reproduced digital data output from the data division decoding circuit 44 is inversely quantized by the inverse adaptive quantizer 25 and input to the inverse DCT circuit 26. Inverse DCT circuit
At 26, inverse DCT is applied to the input reproduced digital signal. The reproduction luminance signal Y subjected to the inverse DCT and the two reproduction color signals CB and CR are stored in the field memories 27a and 27b.
Is temporarily stored in the D / A converters 15a to 15c after being delayed by a predetermined amount.
Is output to.

FIG. 13 shows a recording track pattern formed on the magnetic tape 9 of the digital VTR adopting the two-channel recording system of this embodiment. AX, AY, BX, and BY described in the figure are each divided into two by the data division encoding circuit 31 (in this embodiment, A is AX and A is A).
Y represents the recording position of the two-divided data (assuming that B is divided into BX and BY). The rotary heads of the respective channels have different azimuth angles.

Here, the digital VTR shown in this embodiment is
A case where the editing operation is performed using is described. Similarly to the conventional example, when the editing operation is performed, it is pre-recorded at the cut-in point (or cut-out point) of the editing as shown in FIG. 14 due to the problem of servo accuracy or track bending peculiar to the VTR. In some cases, the track of one channel may be overwritten and crushed. The operation in the case where the track of one channel is reproduced in such a collapsed state will be briefly described.

Even when one track is completely crushed in this way, the digital VTR of the present embodiment which adopts the interleave format shown in FIG. 13 has the main code (AX) in one of the tracks as described above. (Or AY), and BX (or BY))
If it can be reproduced, the original digital value A ′ = 2 ⁶ × AX (or AY) B ′ = 2 ⁶ × BX (or BY) can be almost restored by using the equation (6). For example, if a digital value of 395 is input and both channels can be played,
2 ⁵ × (6 + 6) + 11 = 395 can be restored according to the method of formula (5), and when an error occurs in the reproduced signal and only the main code Y1 is reproduced, 2 ⁶ according to the method of formula (6). The digital value of x6 = 384 is restored.

Accordingly, the band compression is performed by dividing the input digital data into two in accordance with a certain calculation rule (for example, the calculation is performed according to the formulas (1) to (3) above) as in the present method. Data that has been subjected to high-efficiency coding can be effectively divided into two parts. For example, even if the data of one channel is completely overwritten and crushed during editing, it will be reproduced from the other track during reproduction. Since the digital value of the data at the time of recording can be almost restored by the main code, it is possible to obtain a good reproduced image without disturbing the reproduced image.

Further, as compared with the case where each data is simply written twice on each track, the data transmission amount in this embodiment is 15/22 before input to the variable length encoders 32a and 32b and recorded. The data redundancy is about 70% of the amount of information when written twice.

As described above, the data dividing apparatus according to the present embodiment is configured to divide the input digital data into two main codes and sub codes by performing a calculation according to a predetermined method. Since the original digital value can be restored by the two main codes and the sub-code and the original digital value can be almost restored by only one of the main codes, the band can be restored by the DCT conversion or the like like the digital VTR shown in this embodiment. Data can be effectively divided into two even for data that has been compressed (high efficiency coding).

Therefore, even if the track of one channel that has been recorded in advance is overwritten at the cut-in point (or cut-out point) when the editing operation is performed, the above-mentioned one Since the original digital value can be almost restored by the main code, the reproduced image can be reproduced without disturbing the edit joint such as the cut-in point (or cut-out point).

Further, since each data is not simply written twice on each track, it is possible to suppress an increase in redundancy of recorded data. Also, in the case of dropout, scratches on the magnetic tape, or clogging of the rotary head, if one of the above main codes can be reproduced, the original digital value can be almost restored, so band compression (high efficiency coding)
Even for a digital image which has been subjected to the above-mentioned processing, interpolation processing at the time of dropout and the like can be performed, and a good reproduced image can be obtained.

Although detailed description is omitted in high speed reproduction and slow reproduction, the number of bits for recording one code word (main code) becomes short, so that the number of code words reproduced by one scan of the rotary head increases. Good variable speed reproduction can be realized. Similarly, since the same image data is recorded at two places, the probability that the image information at a specific position will be rewritten during variable speed reproduction is doubled, and good variable speed reproduction can be realized.

Second Embodiment A block diagram of a digital VTR equipped with a data division device of a second embodiment of the present invention is the same as FIG. 7 and FIG. 8 shown in the above-mentioned embodiment. Further, the block diagrams of the high efficiency encoding circuit 30 and the high efficiency decoding circuit 40 are also shown in FIG.
The same as shown in FIG.

FIG. 15 shows a block diagram of the data division coding circuit 31 in the second embodiment. In FIG. 15, reference numeral 50 is a data latch circuit, and 51a to 51c are data latch circuits. The data division encoding circuit 31 is constituted by the data latch circuits 50, 51a to 51c.

Similarly, FIG. 16 shows a block diagram of the data division decoding circuit 44 in the second embodiment. In the figure
52a to 52c are data latch circuits, 53 and 54 are selectors, 55
Is a data latch circuit. Data latch circuits 52a to 52
The data division decoding circuit 44 is configured by c, 55 and selectors 53, 54.

Next, the operation of the second embodiment will be described. Second
The basic operation of the embodiment is the same as that of the first embodiment, and the data division coding circuit 31 and the data division decoding circuit 44 are used.
However, the description of the basic operation of the second embodiment will be omitted, and each data division encoding circuit 3 will be omitted.
1, only the operation of the data division decoding circuit 44 will be described in detail.

First, the data division coding circuit 31 of the present embodiment.
The detailed operation of will be described. Now, data division coding circuit
Assuming that the value of the digital data input to 31 is X, the data division coding circuit 31 divides the data into two according to the following method.

The digital data X input to the data division encoding circuit 31 is X = 2 ⁿ × Y1 (or Y2) +
It is divided into main codes Y1 and Y2 and sub-code Z calculated by the method of Z. However, Y1, Y2, and Z shall use the value calculated according to the following method. Y1 (or Y2) = INT (X / ²ⁿ ) (7) Z = X mod ²ⁿ (8) where INT (A / B) is the quotient when A is divided by B, and A mod B is The remainder when A is divided by B is shown.

The above division rule will be described using specific numerical values. For example, assume that data having a digital value of 395 is input to the data division encoding circuit 31. In this embodiment, n = 6. The input digital data is converted into the two main codes Y1 and Y2 and the sub code Z according to the above equations (7) and (8). That is, Y1 (or Y2) = INT (395/2 ⁶ ) = 6 Z = 395 mod 2 ⁶ = 11. The original digital value X is X = 2 ⁶ × 6
It becomes + 11 = 395 and can be completely restored.

Further, according to this division method, the input digital value X can be almost restored from the main code Y1 or Y2 according to the following formula. Now, if the restoration value is X ', then X' = Y1 (or Y2) x ²ⁿ (9). In the case of this example, X ′ = 6 × 2 ⁶ = 384 according to the equation (9), and it can be seen that the input digital value X can be almost restored only by the main code Y1 or Y2.

Further, according to this division method, the conventional method 2
The amount of data to be transmitted is greater than that in the case of multiple writing and transmission.
When the number of bits of the digital data input to the data division encoding circuit 31 is m bits, the number of transmission bits is (m−n) bits for the main codes Y1 and Y2 and the sub code when the present system is adopted. Z makes n bits. Therefore, when the input digital data is 11 bits, the total number of transmission bits is 16 bits after being divided into two. Note that n is 6. Therefore, the transmission bit rate is reduced as compared with the conventional double writing.

Next, FIG. 15 shows an embodiment in which the above division rule is made into a circuit. In this embodiment, 11-bit input digital data is divided into two 5-bit main codes and 6-bit sub-codes according to the above division rule.

The operation of the data division coding circuit 31 will be described below. The input 11-bit digital data X is latched by the data latch circuit 50 and then the data latch circuit
Input to 51a to 51c. The data latch circuits 51a and 51b execute INT (X / 2 ⁶ ) shown in Expression (7). In What is per To perform equation (7) in this embodiment to deal with binary (binary data), and n-bit shift input data to the right may be Kirisutere decimals. For example, the above 395
Is expressed as binary data, it becomes 00110001011. Therefore, in the case of the above binary representation, the operation result of INT (375/2 ⁶ ) is 00110 because the data may be shifted to the right by 6 bits and the fractional part is discarded.

Similarly, since (X mod 2 ⁶ ) in the equation (8) is the remainder when X is divided by 2 ⁶ , 6 bits may be output from the LSB. Therefore, (395 mod ²⁶ )
The calculation result of is 001011. The sub-code data division method is such that one or more sub-codes are collected and divided into two channels in 1-bit units. (For example, each bit is alternately divided into two channels and divided.)

The data division decoding circuit 44 of this embodiment will be described below.
The operation will be described in detail with reference to FIG. The data input to the data division decoding circuit 44 is restored by the following method. When the restoration value is X, it is restored to the value calculated by X = 2 ⁶ × Y1 (or Y2) + Z (10) or X = 2 ⁶ × Y1 (or Y2) (11). In this case, for example, when both code data divided into each channel are reproduced, the data is output according to the formula (10).

However, when one channel data is not reproduced at the discontinuity point of the track pattern such as the cut-in point (or cut-out point) at the time of editing explained in the conventional example, Y1 or Y2 is reproduced properly. We shall use the data of those who have been. Further, in the present embodiment, the switching of the above equations (10) and (11) uses the error detection flag output from the error correction decoding circuit 13.

First, the main code and sub code reproduced from each channel are temporarily latched by the data latch circuits 52a to 52c. Then, the data latch circuits 52a, 52b
The two-channel main codes Y1 and Y2 output by the output are input to the selector 53. Output data of the main codes Y1 and Y2 input to the selector 53 is switched by an error detection flag output from the error correction decoding circuit 13. Similarly, the selector 54 selects 000000 when an error is detected in the reproduced digital signal (subcode signal), and selects the subcode when no error is detected. To configure. The outputs of the selectors 53 and 54 are mixed (2 ⁶ × Y1 (or Y2) + Z, or 2 ⁶ × Y1 (or Y2) is executed) by the data latch circuit 55, and the restored reproduced digital data is output. .

FIG. 13 shows a pattern of recording tracks formed on the magnetic tape 9 of the digital VTR adopting the two-channel recording system in the second embodiment. AX, AY, BX, and BY described in the figure are each divided into two by the data division encoding circuit 31 (in the present embodiment, A is AX,
And AY indicate the recording positions of the two-divided data (assuming that B is divided into BX and BY). The rotary heads of the respective channels have different azimuth angles.

Here, the digital VT shown in the second embodiment is
A case where an editing operation is performed using R will be described. Similar to the first embodiment, when the editing operation is performed again, the cut-in point (or cut-out point) of the editing is previously set as shown in FIG. 14 due to the problem of servo accuracy or track bending peculiar to the VTR. The recorded track of one channel may be overwritten and destroyed. The operation when the track of one channel is reproduced in such a collapsed state will be briefly described.

Even when one track is completely crushed in this way, the digital VTR shown in this embodiment which adopts the interleave format shown in FIG. 13 has the main data (AX) in one of the tracks as described above. (Or AY), and BX (or BY))
If can be reproduced, the original digital value can be almost restored from the main code. For example, if a digital value of 395 is input and both channels can be played back, 2 ⁶ × 6 + 11 = 395 can be restored according to the formula (10), and an error will occur in the playback signal, causing a main error. When only the code Y1 is reproduced, a digital value of 2 ⁶ × 6 = 384 is restored according to the method of the equation (11).

Therefore, the band compression is performed by dividing the input digital data into two in accordance with a certain operation rule (for example, the operation is performed according to the formulas (7) and (8) above) as in this method. Data that has been subjected to (high-efficiency coding) can be effectively divided into two parts. For example, even if the data of one channel is completely overwritten and crushed during editing, it will be reproduced from the other track during reproduction. Since the digital value of the data at the time of recording can be almost restored by the main code, it is possible to obtain a good reproduced image without disturbing the reproduced image.

Further, in comparison with the case where each data is simply written twice on each track, the data transmission amount in this embodiment is 16/22 before the variable length encoders 32a and 32b are input and recorded. The redundancy of data is about 73% of the amount of information when written twice.

According to a simulation when the present embodiment is actually applied to an image (this simulation is performed when 11-bit input data is divided into a 9-bit main code and a 2-bit sub code by the above-mentioned division method). The result is that the amount of data transmission after splitting is about 62.5% compared to the case of writing twice. This is because the transmission efficiency is increased because the run length of 0 of the AC component of the transform coefficient main code data obtained by the DCT transform is increased.

As described above, also in the second embodiment, as in the first embodiment, the input digital data is operated according to a predetermined method and divided into two main codes and sub codes. Has been played, and when playing, 2
The original digital value can be restored by one main code and the sub-code, and the original digital value can be almost restored by only one main code. Therefore, like the digital VTR shown in the present embodiment, band compression (such as DCT conversion) is performed. It is possible to effectively divide data into two even for data that has been subjected to high efficiency coding.

Therefore, even if the track of one channel previously recorded is overwritten at the cut-in point (or cut-out point) when the editing operation is performed and the track is crushed, the above-mentioned one Since the original digital value can be almost restored by the main code, the reproduced image can be reproduced without disturbing the edit joint such as the cut-in point (or cut-out point).

Further, since each data is not simply written twice on each track, it is possible to suppress an increase in redundancy of recorded data. Also, in the case of dropout, scratches on the magnetic tape, or clogging of the rotary head, if one of the above main codes can be reproduced, the original digital value can be almost restored, so band compression (high efficiency coding)
Even for a digital image which has been subjected to the above-mentioned processing, interpolation processing at the time of dropout and the like can be performed, and a good reproduced image can be obtained.

Further, although detailed description is omitted in high speed reproduction and slow reproduction, the number of bits for recording one code word (main code) becomes short, so that the number of code words reproduced by one scanning of the rotary head increases. Good variable speed reproduction can be realized. Similarly, since the same image data is recorded at two places, the probability that the image information at a specific position will be rewritten during variable speed reproduction is doubled, and good variable speed reproduction can be realized.

Since the same information is recorded in the main codes Y1 and Y2 in the first and second embodiments, the data division is performed after the variable length coding to reduce the circuit scale. It goes without saying that it has an effect. Further, in the first and second embodiments, since the main codes Y1 and Y2 are the same information, it goes without saying that the same effect can be obtained even if variable length decoding is performed by the variable length decoder of one system. Further, in the first and second embodiments, since the main codes Y1 and Y2 are transmitted with the same data, error detection (check whether the data match) may be performed using these data. .

Third Embodiment In the first and second embodiments, the data division coding circuit and the data division decoding circuit are configured as shown in FIGS. 10, 15, 12, and 16, but this is not the only option. Microcomputer, not RO
It goes without saying that the same effect can be obtained even when assembled with M or a dedicated arithmetic IC.

Fourth Embodiment Further, in the first and second embodiments, the error detection signal of the error correction decoding circuit 13 is used as the data select signal in the data division decoding circuit, but the present invention is not limited to this. Needless to say, the output level of can be used.

Fifth Embodiment Further, in the first and second embodiments, when an error is detected in the data of one channel, the data is restored by only one main code, but the sub-code in which no error is detected is restored. Even if it is restored by using it, the same effect can be obtained.

Sixth Embodiment Further, in the first and second embodiments, the data inputted according to the formulas (1) to (3) and the formulas (7) and (8) are divided into two. Needless to say, the same effect can be obtained if the input digital data is divided into two main codes and sub codes based on a predetermined operation rule. When the data is divided, the original digital value can be restored if the above two main codes and subcode can be reproduced, and the original digital value can be almost restored only by the main code.

Seventh Embodiment Further, in the first and second embodiments, all the conversion coefficients are divided into two and recorded, but the present invention is not limited to this and, for example, D
In the case of CT conversion, the same effect can be obtained by dividing only the DC component or only the low-frequency component in which the power is concentrated and transmitting the variable length coding without dividing the other data.
(The two-dimensional DCT simulation results also show that when performing zigzag scanning, almost all reproduced images can be excellently restored simply by transmitting the 10th to 20th transform coefficients from DC.)

Eighth Embodiment The same effect can be obtained by switching the first and second embodiments to another method (not described in this embodiment) depending on the distribution of the band-compressed conversion coefficient. Not to mention playing. (That is, this method is suitable for dividing the input digital data such as Gaussian distribution into two, and D is used for DCT conversion.
It has been confirmed by simulation that the C component is very effective. ).

Ninth Embodiment In the first and second embodiments, the subcode is divided into two and then mixed and transmitted as it is to the main code. However, the same applies when the run length coding or the like is performed. Produce an effect.

Tenth Embodiment In addition, in the first and second embodiments, the above-described two divided data is shown in FIG.
Recording was performed by interleaving in the recording format as shown in FIG. 13, but the recording format is not limited to this, and the same effect can be obtained even with the interleaved recording format as shown in FIGS. 17 (a) and 17 (b). Play.

Eleventh Embodiment The basic structure of the digital VTR in the eleventh embodiment is the first
Same as the embodiment (FIGS. 7 and 8), but with high efficiency coding circuit
30, the configuration of the high efficiency decoding circuit 40 is different. Figure 18
FIG. 19 is a block configuration diagram of the high efficiency encoding circuit 30 in the eleventh embodiment, and FIG. 19 is a block configuration diagram of the high efficiency decoding circuit 40. In FIG. 18, reference numeral 61 is a dividing circuit for converting the quantized coefficient into two digital codes X and Y, and 62a and 62b.
Is a variable length encoder for variable length encoding the digital codes X and Y obtained by the dividing circuit 61, and 63a and 63b are buffers for converting the outputs of the variable length encoders 62a and 62b into fixed rate outputs. The memory 64 is a channelizing circuit for mixing the output codes X and Y divided by the dividing circuit 61 and converting them into two-channel outputs.

In FIG. 19, reference numeral 65 is a channel converter for converting a signal reproduced by the rotary heads 8a and 8b into a channel having only the output code X and a channel having only the output code Y, and 66a and 66b are variable-length coded. Variable-length decoder that converts the converted data to the original fixed-length data, 67a and 67b are buffer memories that output the output of variable-length decoders 66a and 66b at a fixed rate, and 68 is two output codes It is an inverse division circuit that performs inverse conversion on one digital code using only X, Y, or output code X, or only output code Y. In FIGS. 18 and 19, the parts having the same numbers as in FIGS. 9 and 11 are exactly the same as the conventional example.

FIG. 20 is a diagram showing the structure of the division circuit 61 of FIG. Here, 69 is an input terminal to which the adaptively quantized transform coefficient is input, 70a is a ROM that transforms the transform coefficient into a digital code X, 70b is a ROM that transforms the transform coefficient into a digital code Y, and 71a and 71b are digital. It is an output terminal for outputting the codes X and Y to the variable length encoders 62a and 62b.

Next, the operation will be described with reference to FIG. Luminance signals Y input from the input terminals 1a to 1c, and 2
The two color signals CR and CB are recorded on the magnetic tape 9 by the same operation as that of the conventional example except for the operation in the high efficiency encoding circuit 30.

The operation of the high efficiency coding circuit 30 will be described with reference to FIG. Input luminance signal Y and two color signals CR
And CB are divided into blocks of 8 pixels × 8 lines by the field memories 17a and 17b in the same manner as in the conventional example. This block is subjected to two-dimensional DCT by the DCT circuit 18, and each transform coefficient is output. This transform coefficient is quantized by the adaptive quantizer 19 by switching the quantization step according to the transform coefficient of each block and the parameters from the buffer memories 63a and 63b.

Assume that the adaptively quantized transform coefficient is D, and the two output codes to be output are X and Y. Input D and output code are made such that the values of a plurality of consecutive inputs D are associated with one output code X, and the values of the next plurality of consecutive inputs D are associated with an output code X that is increased by one. Correlate X. The output code Y is obtained from the input D and the output code X so as to have a relationship of D = 2X + Y. A conversion table is created in advance from the correspondence relationship between the input D and the output codes X and Y. This conversion table is shown in FIG. This input D
Based on the correspondence between the output code X and the output code X, the output code X is written in the ROM 70a at the address indicated by the input D, and the conversion table for the output code X is created.

Similarly, the ROM 70b also creates a conversion table for the output code Y based on the correspondence between the input D and the output code Y. The division circuit 61 divides the adaptively quantized transform coefficient into two output codes X and Y using this transform table. The specific operation at this time is shown in Fig. 22.
Will be explained. FIG. 22 (a) shows the conversion coefficient of one block after adaptive quantization, and this conversion coefficient D is inputted as an address to the ROMs 70a and 70b having the conversion table as shown in FIG. 21, and two output codes X and Get Y. The digital code of one block of X and Y at this time is shown in FIG.
Shown in (b) and (c).

The output codes X and Y converted by the dividing circuit 61 are variable-length coded by the variable-length encoders 62a and 62b, respectively, and input to the buffer memories 63a and 63b. The data stored in the buffer memories 63a and 63b are read at a fixed rate. The buffer controller 22 is
The adaptive quantizer 19 and the variable length encoders 62a and 62b are controlled by the amount of data stored in the buffer memories 63a and 63b in the same manner as in the conventional example.

The output code X read from the buffer memory 63a and the output code Y read from the buffer memory 63b are combined by the channelizing circuit 64, and the output code X and the output code Y are recorded on different tracks. It is distributed to the respective rotary heads 8a and 8b so as to be recorded. The pattern of the recording track at this time is shown in FIG.
Here, A and B described in the figure are A described in the conventional example.
And B, which is the same information as in the conventional example. Also,
X and Y correspond to the output code X and the output code Y.

Next, the operation of the reproducing system will be described. The reproduced signal is digitally demodulated and error-corrected in the same manner as the conventional example, and then the output code X is output by the channel converter 65.
And the output code Y are converted into the corresponding channels. The channel corresponding to the output code X is variable-length decoded by the variable length decoder 66a, and the channel corresponding to the output code Y is variable-length decoded by the variable length encoder 66b and converted into fixed-length data. , Buffer memories 67a and 67b are temporarily stored. The buffer memories 67a and 67b read the variable-length decoded fixed-length data at a fixed rate. In the reverse division circuit 68, buffer memories 67a and 67b
Using the output codes X and Y read from, the operation reverse to that at the time of recording, that is, 2X + Y is calculated and obtained, and this is output. Hereinafter, in the same way as the conventional example, inverse quantization,
Inverse DCT and inverse blocking are performed to obtain a reproduction luminance signal Y and two reproduction color signals CB and CR.

High-efficiency coding circuit constructed in this way
When the editing operation is performed by the digital VTR using the 30 and the high-efficiency decoding circuit 40, the cut-in point (or cut-out point) of the editing similar to the case of the conventional example is performed.
Then, there is a case where the track of one channel recorded in advance is crushed (see FIG. 23). Even in such a case, although the reproduction signal from the other remaining track is deteriorated to some extent, all the image data of one field can be reproduced.

The operation at this time will be described below.
The reproduced signals from the rotary heads 8a and 8b are shown in FIG.
Detecting that the rotary heads 8a, 8b played back a track that has been crushed by an editing operation, from the fact that the size of the playback envelope has become smaller than a predetermined amount and the number of errors in the playback signal has become larger than a predetermined amount. The detection signal shown in FIG. 24 (c) is output. The reproduced signal of each channel is converted by the channel converter 65 into a channel having only the output code X and a channel having only the output code Y (see FIG. 24).
(See (b)), each of which is variable-length decoded by the variable-length decoders 66a and 66b, and then input to the inverse division circuit 68.
In the reverse division circuit 68, based on the detection signal, when one track is not crushed by an editing operation or the like, 2X + Y
The reproduced digital data is obtained by the following calculation, and when one track is crushed, the use of the reproduced signal from that track is prohibited, and only the reproduced signal (output code X in the case of FIG. 24) from the other track is displayed. Converting with a code table such as 25, one-field image is constructed.

As described above, the DCT and the coefficient after adaptive quantization are divided into two, and the two outputs are recorded on different tracks, respectively, and when reproduced, either or both of the divided outputs depending on the state of each track. Since the reproduction signal is configured by using only one, even if one of the tracks is crushed by an editing operation or the like, the screen can be reproduced with a reasonable image quality.

Twelfth Embodiment In the eleventh embodiment, the transform coefficient D after DCT and adaptive quantization is 2
When divided into two output codes X and Y, D = 2X + Y
An example has been described in which the conversion coefficient is converted into two outputs so that the relation of Besides this example, D
= 3X + Y to obtain a conversion table in advance (the conversion table at this time is shown in FIG. 26). Based on this conversion table, the contents to be written in the ROMs 70a, 70b are determined, and the conversion coefficient D is used as an address in the ROM 70a, Enter 70b and get the two corresponding output codes and record this. Even with this structure, the same effect as that of the 11th embodiment can be obtained.

Further, there is a relation of D = AX + BY (A and B are real numbers) between the input D and the two output codes X and Y, such as D = X + Y or D = X + 2Y or D = X + 3Y. Any pattern may be used as long as it converts one input code into two output codes, and the same effect as the 11th embodiment can be obtained.

Thirteenth Embodiment In the eleventh embodiment, an example of using the code table to obtain the output codes X and Y from the input code D has been described. However, a code table for obtaining the output code X from the input code D is created in advance. The output code X may be obtained using this code table, and Y may be obtained from D and X by the calculation Y = (D-AX) / B.

Fourteenth Embodiment In addition, in the eleventh to thirteenth embodiments, the input D is converted into two output codes X.
Although an example in which the input D is converted to Y and recorded is described, other than this example, the input D may be converted into three or more digital codes, combined into two channels, and recorded. Such an embodiment will be described. FIG. 27 is a block configuration diagram of the high efficiency encoding circuit 30 in the fourteenth embodiment, and FIG. 28 is
FIG. 3 shows a block diagram of a high efficiency decoding circuit 40.

In FIG. 27, reference numeral 72 is a dividing circuit for converting the quantized transform coefficient into four digital codes X ₀ , X ₁ , X ₂ and X ₃ , and 73 is a combination of the four digital codes into two channels. Channel synthesis circuit, 74a, 74b
Is a variable length encoder for variable length encoding the digital code after being combined into two channels, 75a, 75b
Is a buffer memory for converting the outputs of the variable length encoders 74a and 74b into fixed-rate outputs.

Further, in FIG. 28, reference numerals 76a and 76b denote variable length decoders for converting variable length encoded data into original fixed length data, and 77a and 77b denote variable length decoders 76a and 76b. 76b
, A buffer memory that outputs the output of a fixed rate, 78 is a channel division circuit that divides the reproduced signals of two channels into four digital codes, and 79 is a conversion method depending on the reproduction state of the obtained four digital codes. Change
It is an inverse division circuit that performs inverse conversion on one digital code. 27 and 28, the parts having the same numbers as those in FIGS. 9 and 11 are exactly the same as those in the conventional example.

FIG. 29 is a diagram showing the structure of the division circuit 72 of FIG. Here, 80 is an input terminal to which the adaptively quantized transform coefficient is input, 81a is a ROM for transforming the transform coefficient into a digital code X ₀ , 81b is a ROM for similarly transforming into a digital code X ₁ , 81c is also a digital code. ROM to convert to X _2, 81d is ROM for converting same to a digital code X _3, 82a ~82d denotes an output terminal for outputting to the channel synthesis circuit 73.

Next, the operation will be described with reference to FIG. Similar to the conventional example or the eleventh embodiment, the input signal is subjected to DCT conversion and adaptive quantization, and is input to the dividing circuit 72. Here, the conversion rule in the dividing circuit 72 is defined as follows. When the adaptively quantized transform coefficient is D and the codes transformed into two codes are D ₀ and D ₁ , respectively, there is a relationship of D = 2D ₀ + D ₁ between D, D ₀ and D _1. , D ₀ , D ₁ as in the eleventh embodiment.
And D is associated with D ₀ and D ₁ . If the four output codes that are output are X ₀ , X ₁ , X ₂ and X ₃ ,
As in Example 11, X ₀ and X ₂ are determined and D ₀ = 2X
_{From the} relation of ₀ + X ₁ , D ₁ = 2X ₂ + X ₃ , X ₁ , X ₃
Ask for.

In this way, the input D and the outputs X _{0 to} X _{3 are}
To have a relation of D = 4X ₀ + 2X ₁ + 2X ₂ + X ₃ . A conversion table based on this conversion rule is created in advance and written in the ROMs 81a to 81d. This conversion table is shown in FIG. The division circuit 72 uses this conversion table (contents written in the ROMs 81a to 81d) to divide into four output codes X _{0 to} X ₃ . Of the four output codes, the channel synthesizing circuit 73 synthesizes one channel with X ₀ and X ₁ , and synthesizes another channel with X ₂ and X ₃ . Variable length encoder for each channel 74
Variable length coding is performed with a and 74b and recorded.

Next, the operation of the reproducing system will be described with reference to FIG. In the same way as the conventional example or the eleventh embodiment, the reproduced signals of the respective channels are subjected to digital demodulation, error correction and variable length decoding, and a channel division circuit is provided.
Input to 78. The channel dividing circuit 78 operates in the opposite manner to that at the time of recording and divides the reproduced signal of 2 channels into 4 digital codes. Similarly to the eleventh embodiment, when the reverse division circuit 79 detects that a track which has been crushed by an editing operation is reproduced, the reproduction digital code from the crushed track is not used and the remaining code is used. To restore the original digital value. When all the tracks have been reproduced, the original digital value is restored using four digital codes.

In this way, during recording, the DCT and the transform coefficient after adaptive quantization are divided into four digital codes, which are combined and recorded in two channels, and during reproduction, four digital codes of the four digital codes are recorded depending on the state of the reproduced track. Since some of the codes are used to restore the original digital value, the same effect as the 11th embodiment can be obtained.

In the above embodiment, when the transform coefficient D after the DCT and the adaptive quantization is divided into four output codes X _{0 to} X ₃ , the transform coefficient D is such that D = 4X ₀ + 2X ₁ + 2X ₂ + X _3. 4 digital codes X _{0 to} X ₃
The example in which the conversion is performed has been described. In addition to this example, a conversion table is obtained in advance so as to have a relationship of D = 6X ₀ + 3X ₁ + 2X ₂ + X ₃ , divided into 4 digital codes using this conversion table, and combined into 2 channels for recording. If it is configured to
The same effect as the embodiment can be obtained.

The number of digital codes to be divided is four.
The number is not limited to one, and may be any number as long as it is divided into three or more digital codes.
Further, between the input D and the n digital codes X _{0 to} X _n-1 , D = K ₀ X ₀ + K ₁ X ₁ + ... + K _n-1 X _n-1 (K
Any pattern may be used as long as it converts one input code D into n digital codes so that _{0 to} K _n-1 are real numbers. Similar effects are obtained.

Fifteenth Embodiment The fifteenth embodiment uses the same configuration as the eleventh embodiment and changes the rules for creating the conversion table, and the same effects as the eleventh embodiment can be obtained. Using the configuration shown in FIGS. 18 to 20,
If a code table is created in advance based on the rules as shown below and the code table is used to convert the output codes X and Y from the input code,
The same effect as the 11th embodiment is obtained.

One set of all input digital codes D is 4
Are divided into groups including different input digital codes, and the digital codes in one group are uniquely represented by a combination of an output code X having two different values and an output code Y having two different values. , A combination of output code X and Y values representing a digital code in a particular set is not a combination representing another digital code.

FIG. 31 shows a code table based on this rule.
Shown in. Based on this code table, ROM70a, 7
Create by writing the conversion table to 0b. A specific operation at this time will be described with reference to FIG. FIG. 32 (a) shows the transform coefficient of one block after adaptive quantization. The transform coefficient of this one block is inputted as an address to the ROMs 70a and 70b as shown in FIG. 20, and two output codes X and Y are output. obtain. The values of the output codes X and Y at this time are shown in FIGS. 32 (b) and 32 (c).

Next, the operation of the reproducing system will be described. Similarly to the eleventh embodiment, when it is detected that a track that has been crushed by an editing operation or the like is reproduced, conversion is performed using a code table corresponding to the obtained code in the code table as shown in FIG. 33, If not, inverse transform using both output codes X and Y.

Sixteenth Embodiment In the fifteenth embodiment, an example of conversion based on the conversion rule shown in FIG. 31 has been described. In addition to this example, the input digital code D is divided into a set including six different input digital codes, and the digital code in one set is divided into an output code X having three different values and two output codes X. Can be uniquely expressed in combination with output code Y that has a different value,
A code table is created in advance based on the rule that the combination of the values of the output codes X and Y representing the digital code in a specific set is not the combination representing the other digital code, and this code table is used. If divided into two outputs, the same effect as that of the fifteenth embodiment can be obtained. The code table at this time is shown in FIG.

In addition to the code table shown in the fifteenth and sixteenth embodiments, a code table is created in advance based on the rule described in claim 6 , and this code table is used to divide into two output codes X and Y. With this structure, the same effects as those of the 15th and 16th embodiments can be obtained.

Seventeenth Embodiment In the fifteenth and sixteenth embodiments, an example in which two output codes X and Y are divided has been described. However, in addition to this example, FIGS.
The same effect can be obtained by converting the input digital code D into three or more digital codes by using the configuration shown in and combining them into two channels.

This embodiment will be described below. The rules for conversion at this time are defined as follows. All the input digital codes are divided into groups each including eight different input digital codes, and the input digital codes in one set are four kinds of digital codes X _{0 to} X ₃ having two different digital codes. Can be uniquely expressed by a combination of
The combination of the values of the digital codes X _{0 to} X ₃ representing the input digital code in a particular set should not be the combination representing the other input digital codes.
This conversion table is shown in FIG.

Eighteenth Embodiment In the eleventh embodiment, an example in which the size of the reproduction envelope or the number of errors is used to detect a track which has been crushed by an editing operation has been described, but a plurality of tracks constituting one field are described. If the configuration is such that the size of the reproduction envelope is compared and the detection signal is output when only the reproduction envelope of one track is significantly smaller than the other tracks, the detection accuracy will be further enhanced. The same effect can be obtained by comparing the number of errors and outputting the detection signal when many errors occur in a specific track.

FIG. 36 shows an increase in the amount of information when the above-mentioned eleventh, twelfth, fourteenth, fifteenth, and seventeenth embodiments are actually applied to band-compressed (high-efficiency coding) data. As is clear from FIG. 36, the increase in the amount of information is smaller than that in the case where the data is written twice. As described above, in the eleventh to seventeenth embodiments, even when there is a track that has been crushed by an editing operation, the remaining track can be used to reproduce with a certain reproduction image quality, and the amount of data increases due to division. Can be suppressed.

Nineteenth Embodiment The configurations of the high-efficiency coding circuit 30 and the high-efficiency decoding circuit 40 in the nineteenth embodiment are the same as those in the eleventh embodiment (see FIGS. 18 and 19), and the high-efficiency coding is performed. The configuration of the dividing circuit 61 of the digitizing circuit 30 is the same as that of the eleventh embodiment (see FIG. 20).

Next, the operation will be described with reference to FIGS. The basic operation in the entire system is similar to that in the eleventh embodiment, but the relationship between the adaptively quantized transform coefficient D and the two output codes X and Y to be output is different from that in the eleventh embodiment. In the nineteenth embodiment, the output code X and the output code Y with respect to the value of the input D are determined so as to satisfy the following equation. D = x ^1.5608 + 2 × y + z X = x Y = 2 × y + z

A conversion table is created in advance from the above correspondence between the input D and the output codes X and Y. Input D range is 0
37 and 38 show the conversion tables in the case of 11 bit width notation ~ 2047 (± 1023 when considering signs). Also, a graph showing the division characteristics is shown in FIG. Based on the correspondence between the input D and the output code X, the output code X is written in the ROM 70a at the address indicated by the input D, and the output code X is output.
Create a conversion table for.

Similarly, the ROM 70b also creates a conversion table for the output code Y based on the correspondence between the input D and the output code Y. The dividing circuit 61 divides the adaptively quantized transform coefficient into two output codes X and Y using this transform table. The specific operation at this time will be described with reference to FIG. Figure 40 (a) shows 1 after adaptive quantization.
The conversion coefficient of the block is shown, and this conversion coefficient D is shown in FIG.
By inputting as addresses into the ROMs 70a and 70b having conversion tables as shown in 38, two output codes X and Y are obtained. Digital codes of one block of X and Y at this time are shown in FIGS. 40 (b) and 40 (c).

Next, the operation of the reproducing system will be described. The basic operation in the reproducing system is the same as in the eleventh embodiment,
The arithmetic expression in the inverse division circuit 68 is different. That is, the reverse division circuit
In 68, using the output codes X and Y read from the buffer memories 67a and 67b, the operation opposite to that at the time of recording, that is, D = X ^1.5608 + Y is calculated and obtained, and D is output.

In the nineteenth embodiment as well, as in the eleventh embodiment, there is a case in which the track of one channel recorded in advance is destroyed at the cut-in point (or cut-out point) of editing (see FIG. 23). Even in such a case, although the reproduction signal from the other remaining track is deteriorated to some extent, all the image data of one field can be reproduced.

A signal diagram in the nineteenth embodiment corresponding to FIG. 24 is shown in FIG. In the nineteenth embodiment, based on the detection signal in the reverse division circuit 68, when one track is not crushed due to an editing operation or the like, reproduced digital data is obtained by the calculation of X ^1.5608 + Y, and one track is crushed. In this case, use of the reproduction signal from that track is prohibited, and only the reproduction signal (output code X in the case of FIG. 41) from the other track is converted by the code table as shown in FIG. Constitute.

Here, the operation of restoring the original data from one of the two pieces of divided data will be slightly described. In the present embodiment, 11 bits of the original data D are divided into 2-divided data X and Y into 7 bits each. (In the division formula, x is 7 bits, y is 6 bits, z is 1 bit, x is assigned to X, y is assigned to Y, and z is assigned to Y.) When only X data is obtained here When estimating the original data D, the values of the original data D that can be obtained from the division operation are as shown in FIGS. 43 to 46.

43 to 46, possible D for X
The maximum value, the minimum value, the difference (range) thereof, the number of Ds that can be taken, and the average value of Ds that can be taken are shown. Similarly Y
When D is estimated only in the middle y part (that is, 6 bits),
The case of estimating D as Y (that is, 7 bits) is shown in FIGS. 47, 48, and 49 to 52, respectively. Figures 53 to 57 show graphs of each figure. Note that the figure
53 is an overall graph, and FIGS. 54 and 55 are partially enlarged views.

From the above figure, it can be understood that the estimation of D from X data can be estimated more accurately than the estimation from Y data. Therefore, as seen in the present embodiment, it is understood that the image quality can be improved by performing the editing point on the Y side track during the editing operation represented by the joint shooting operation.

Of course, it is possible to estimate the original data to some extent only with the Y data, but if the place where the damage such as editing is damaged is known in advance or if there is a place with a high probability, If the Y data is stored there, the X data can be reproduced better even if it is damaged and lost.

In this way, the DCT and the coefficient after adaptive quantization are divided into two, and the two outputs are recorded on different tracks, and when reproduced, both of the divided outputs depending on the state of each track, or both. Since the reproduction signal is configured using only one side, even if one of the tracks is crushed by an editing operation or the like, the screen can be reproduced without significant image quality deterioration.

Twentieth Embodiment In the nineteenth embodiment, the DCT and the adaptively quantized transform coefficient D are 2
An example has been described in which the conversion coefficient is converted into two outputs so that the output coefficient is divided into two output codes X and Y: D = x ^1.5608 + 2 × y + z X = x Y = 2 × y + z. In addition to this example, generally, the coefficients a and b are determined so as to satisfy the relationship of D = x ^a + b × y + z, and D →
An X, Y conversion table is obtained, the contents to be written in the ROMs 70a, 70b are determined based on this conversion table, the conversion coefficient D is input to the ROMs 70a, 70b as an address, two corresponding output codes are obtained, and this is recorded. Even with this structure, the same effect as that of the nineteenth embodiment can be obtained.

An example of creating the conversion table will be described below. In the conversion formula D = x ^a + b × y + z, it is assumed that the conversion conditions are as follows, for example. (1) Let sx be the number of allocated bits of x. (2) Let sy be the number of allocated bits of y. (3) Let sz be the number of bits allocated to z. (4) Let the number of allocated bits of D be sD. First, for b, since an integer value less than the numerical value b is assigned to z, b = 2 ^sz . This can also be explained from the fact that it is the difference between the sum of the numerical values of x and y terms and D (that is, the remainder component).

Then, suppose that D = x ^a + b × y, and 2 ^sD −1 = (2 ^sx −1) ^a + b × (2 ^sy −1) ∴ a = It ^suffices to determine a as [log {(2 ^sD −1) −b × (2 ^sy −1)}] / {log (2 ^sx −1)}.

In this way, after the respective coefficients are determined, if the set of variables x, y, z corresponding to the input data D is obtained in accordance with the procedure shown in FIG. 58, for example, the above relational expression D = x ^a + b × y + z It is possible to obtain an x, y, z set value that satisfies

According to the above technique example, when D is divided with sx = sy = 7 sz = 1 sD = 11, it can be expressed by a relational expression D = x ^1.5465 + 2 × y + z.

The relationship between the input D and the divided data x and y in this case is shown in FIGS. 59 to 61 as in the nineteenth embodiment. From this figure, it can be understood that the estimation error value of the original data D from only the y data is obviously reduced by the addition of 1 bit for y from the nineteenth embodiment, and more accurate estimation is possible.

The actual divided data X, Y may be X = x, Y = 2y + z or X = cx + z, Y = y (a, b, c are real constants), similar to the nineteenth embodiment. The effect is obtained. As for the data increment, the total number of original data bits is 200% at the time of double writing, and 14/11 = 127 in the 19th embodiment.
%, And 15/11 = 136% in the twentieth embodiment, and it can be seen that the value is extremely low.

Further, not only by the method of deriving the divisional relational expression described above, X = x, Y = b × y + z for the relational expression D = x ^a + b × y + z between the input D and the two output codes X and Y. Alternatively, if one input code having a relationship of X = c × x + z and Y = y (a, b, and c are real constants) is converted into two output codes, what kind of pattern is it? However, it is obvious that the same effect as the nineteenth embodiment can be obtained.

Twenty-first Embodiment In the nineteenth embodiment, an example of using the code table to obtain the output codes X and Y from the input code D has been described. However, a code table for obtaining the output code X from the input code D is prepared in advance. The output code X may be obtained using this code table, and Y may be obtained from D and X, for example, by the operation Y = (D−X ^a ) / B, and the reverse configuration is also possible.

Twenty-second Embodiment In the nineteenth embodiment, an example in which the size of the reproduction envelope or the number of errors is used to detect a track which has been crushed by an editing operation has been described, but a plurality of tracks constituting one field are described. If the configuration is such that the size of the reproduction envelope is compared and the detection signal is output when only the reproduction envelope of one track is significantly smaller than the other tracks, the detection accuracy will be further enhanced. The same effect can be obtained by comparing the number of errors and outputting the detection signal when many errors occur in a specific track.

Twenty-third Embodiment In the nineteenth embodiment, as a rule for converting the input code D from the output codes X and Y, the input D and the two output codes X and Y are used.
Between the relational expressions D = x ^a + b × y + z X = x, Y = b × y + z or X = c × x + z, Y = y (a, b, c are real constants) An example in which the input code is converted into two output codes is shown.

Besides this example, for example, it is easily possible to replace the divided data X or Y with the input D again, perform the above division again, and finally divide into three or more divisions. In this case, it is possible to easily record each of the multi-divided data on three or more tracks as it is, or to re-synthesize again into two-divided data X and Y by performing an operation such as linear addition. In either case, if a code table is created and the input code is used to convert a plurality of output codes,
The same effect as that of the 19th embodiment can be obtained.

Twenty-fourth Embodiment In the above embodiments, the description has been made on the premise that the division is performed on all input data. For example, only the portion of the input data relating to the basic image quality is divided into the recording medium. It may be recorded in multiple places. In this case, if the data increment associated with the division operation is performed in the division of the nineteenth embodiment, it is assumed that only 1/4 of all the input data is divided and recorded, and (1/4) × {(14-11) / 11} = 0.068 Which is an increase of 6.8%. By performing the partial division in this way, it becomes possible to further reduce the redundancy as compared with the case of performing all the data.

In the case of a digital VTR or the like, since the operations such as DCT and adaptive quantization are performed in advance, the amount of information that contributes to the image quality of data is not necessarily uniform, and data relating to the basic image quality (low-frequency coefficient of DCT) Is applicable) and data related to high definition image quality (corresponding to the high frequency coefficient of DCT), and the like, so that it is easily feasible to perform the partial division only on data related to basic image quality. FIG. 62 shows a configuration example of partial division according to the present embodiment.

FIG. 62 shows a part of the internal structure of the high-efficiency coding circuit 30. The difference from FIGS. 18 and 20 is that the input direct output terminal is added and the input data Two
That is, the determination unit 91 for determining whether the divided data output is valid or the direct output is valid is provided. Along with this, a direct output variable length encoder 62c is added, and an input terminal of the buffer memory 63 is added.

Then, the judgment result from the judging device 91 is output to the output line.
It is input to the variable length encoders 62a, 62b, 62c and the buffer memory 63 via 92. The judging device 91 counts, for example, the number of input data, and determines whether the basic image quality determination data is obtained from the input sequence position of the current input data.
(M, n <3, etc. of (m, n)), other data is judged and the output line 92 is used to output the divided data or direct output data to the variable length encoder, buffer memory, etc. in the subsequent stage. It is possible to record whether or not to process the data, and as a result, only the data that determines the basic image quality in the input data can be divided and recorded.

By this operation, the tracks are crushed during editing,
Even if data loss such as partial non-reproduction occurs due to damage to the recording medium, it is not possible to display a considerable portion of the image, and it is possible to output the image by reproducing from one of the divided basic image quality data. Therefore, it is possible to easily realize a fault repairing operation that is visually natural, and at the same time, it is possible to realize with minimum redundancy.

Although the judging device 91 in the above-mentioned embodiment performs the judging operation by counting the input data,
It is obvious that the same effect can be obtained even if the T circuit 18 or the adaptive quantizer 19 is provided with the function and the direct selection output is performed. Although the discrete cosine transform (DCT transform) is used as the band compression scheme (high efficiency coding scheme) in each embodiment, the invention is not limited to this , and the orthogonal transform represented by the DCT transform (one-dimensional or It is needless to say that the same effect can be obtained even when the data is band-compressed by transform coefficients such as three-dimensional orthogonal transform), predictive coding, motion compensation, KL transform, or a combination of these transforms.

Further, in each embodiment, the digital VTR adopting the 2-channel recording method has been described, but the same applies to the VTR adopting the 1-channel recording method, the multi-channel recording method, the multi-segment recording method, the multi-channel multi-segment recording method and the like. Produce the effect of.

[0173]

As described above, in the data dividing apparatus of the present invention, the track of one channel previously recorded is overwritten at the cut-in point (or cut-out point) when the editing operation is performed. , Even if it has been crushed, the cut-in point (or cut-out point) mentioned above is used by using the remaining track.
It can be reproduced with a certain reproduction image quality at the joint of editing, etc., and band compression (high efficiency encoding) is performed by DCT conversion or the like like the digital VTR shown in this embodiment.
The data can be effectively divided even for the data that has been subjected to.

Further, since each data is not simply written twice on each track, it is possible to suppress an increase in redundancy of recording data. In addition, it is possible to significantly improve the reconstructing ability against various factors such as dropout, scratches on the magnetic tape, clogging of the rotary head, and the like, and a good reproduced image can be obtained.

Further, as described in the embodiment as the data dividing device, according to the present invention, it is possible to realize the above effect with the minimum necessary data increase amount.

[Brief description of drawings]

FIG. 1 is a block diagram of a recording system of a conventional digital VTR.

FIG. 2 is a block configuration diagram of a reproduction system of a conventional digital VTR.

FIG. 3 is a block diagram of a conventional high efficiency encoding circuit.

FIG. 4 is a block diagram of a conventional high efficiency decoding circuit.

FIG. 5 is a recording format diagram of a conventional digital VTR.

FIG. 6 is a track pattern diagram on a magnetic tape for explaining the problems of the conventional digital VTR.

FIG. 7 is a block configuration diagram of a recording system of a digital VTR equipped with the data division device of the present invention.

FIG. 8 is a block configuration diagram of a reproduction system of a digital VTR equipped with the data division device of the present invention.

FIG. 9 is a block diagram of a high efficiency encoding circuit according to the present invention.

10 is a block configuration diagram of a data division encoding circuit in FIG. 9.

FIG. 11 is a block diagram of a high efficiency decoding circuit of the present invention.

12 is a block configuration diagram of a data division decoding circuit in FIG. 11. FIG.

FIG. 13 is a recording format diagram of a digital VTR.

FIG. 14 is a track pattern diagram on a magnetic tape.

FIG. 15 is a block configuration diagram of another data division encoding circuit in FIG. 9.

16 is a block configuration diagram of another data division decoding circuit in FIG. 11. FIG.

FIG. 17 is another recording format diagram of the digital VTR.

FIG. 18 is a block configuration diagram of another high efficiency encoding circuit of the present invention.

FIG. 19 is a block diagram of another high efficiency decoding circuit of the present invention.

20 is a block configuration diagram of a division circuit in FIG.

FIG. 21 is a diagram showing a code table for conversion.

FIG. 22 is a diagram for explaining the operation of the present invention.

FIG. 23 is a diagram for explaining the operation of the present invention.

FIG. 24 is a diagram for explaining the operation of the present invention.

FIG. 25 is a diagram showing a code table for reverse conversion.

FIG. 26 is a diagram showing a conversion code table.

FIG. 27 is a block configuration diagram of still another high efficiency encoding circuit of the present invention.

FIG. 28 is a block diagram of still another high efficiency decoding circuit of the present invention.

29 is a block configuration diagram of the division circuit in FIG. 27. FIG.

FIG. 30 is a diagram showing a conversion code table.

FIG. 31 is a diagram showing a conversion code table.

FIG. 32 is a diagram for explaining the operation of the present invention.

FIG. 33 is a diagram showing a code table for reverse conversion.

FIG. 34 is a diagram showing a conversion code table.

FIG. 35 is a diagram showing a conversion code table.

FIG. 36 is a table showing a comparison of information amounts.

FIG. 37 is a diagram showing a conversion code table.

FIG. 38 is a diagram showing a conversion code table.

FIG. 39 is a graph showing division characteristics of a code table.

FIG. 40 is a diagram for explaining the operation of the present invention.

FIG. 41 is a diagram for explaining the operation of the present invention.

FIG. 42 is a diagram showing a code table for reverse conversion.

FIG. 43 is a diagram showing an inverse conversion characteristic of an x value.

FIG. 44 is a diagram showing an inverse conversion characteristic of an x value.

FIG. 45 is a diagram showing an inverse conversion characteristic of an x value.

FIG. 46 is a diagram showing an inverse conversion characteristic of an x value.

FIG. 47 is a diagram showing an inverse conversion characteristic of y value.

FIG. 48 is a diagram showing an inverse conversion characteristic of y value.

FIG. 49 is a diagram showing an inverse conversion characteristic of a Y value.

FIG. 50 is a diagram showing an inverse conversion characteristic of a Y value.

FIG. 51 is a diagram showing an inverse conversion characteristic of a Y value.

FIG. 52 is a diagram showing an inverse conversion characteristic of a Y value.

FIG. 53 is a graph showing an inverse conversion characteristic of x value.

FIG. 54 is a graph showing an inverse conversion characteristic of x value.

FIG. 55 is a graph showing an inverse conversion characteristic of x value.

FIG. 56 is a graph showing an inverse conversion characteristic of y value.

FIG. 57 is a graph showing an inverse conversion characteristic of Y value.

FIG. 58 is a diagram showing a procedure for creating a code table.

FIG. 59 is a graph showing division characteristics.

FIG. 60 is a graph showing an inverse conversion characteristic of x value.

FIG. 61 is a graph showing an inverse conversion characteristic of y value.

FIG. 62 is a block configuration diagram of still another high efficiency encoding circuit of the present invention.

[Explanation of symbols]

31 Data division coding circuit 44 Data division decoding circuit 61 division circuit 72 division circuit 73-channel synthesis circuit 70a, 70b ROM 81a, 81b, 81c, 81d ROM 91 Judgment device

Front page continuation (72) Inventor Junko Ishimoto No. 1 Baba Institute, Nagaokakyo, Kyoto Prefecture Mitsubishi Electric Corporation Electronic Product Development Laboratory (72) Inventor Ken Onishi No. 1 Baba Institute, Nagaokakyo Kyoto Prefecture Mitsubishi Electric Corporation Company Electronic Product Development Laboratory (56) Reference JP-A-3-224176 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 20/12 G11B 20/18 H03M 7/30 H04N 5/92

Claims (13)

(57) [Claims] 1. A data dividing device for 2 divides digital data input, the de Ijitarudeta X advance
Calculated in accordance-determined law, a calculating means for dividing into two main code Y1 and Y2 and the subcode Z, and 2 divides the subcode Z at one or more collected bits, output from the arithmetic means And a data generating means for generating two-channel data in combination with the divided main code .
^{X = 2 n-1 × (} Y1 + Y2) + at Z law defined data dividing apparatus according to claim Rukoto. However, Y1, Y2 and Z are calculated according to the following method.
It Y1 = INT (X / ²ⁿ ) Y2 = INT (X / ^2n-1 ) -INT (X / ²ⁿ ) Z = X mod ^2n-1 INT (A / B) divides A by B The quotient when
A mod B is the remainder when A is divided by B.
You 2. The input digital data is divided into two.
In the data dividing device, the digital data X is previously
Operates according to the determined law and uses two main codes Y1 and
And Y2 and a sub-code Z, and an arithmetic means for
Collect one or more bucode Z and divide into two in bit units
The divided main code output from the computing means.
A data source that combines with a channel to generate 2-channel data
And a method for defining the arithmetic means,
X = 2 ⁿ × Y +, characterized in that it is defined by the Z law and to Lud <br/> over data dividing device. However, Y and Z are calculated according to the following method. Y = INT (X / ²ⁿ ) Z = X mod ²ⁿ INT (A / B) is the quotient when A is divided by B,
A mod B is the remainder when A is divided by B.
Then, Y = Y1 = Y2. 3. A plurality of input digital data are output.
Input data in a data dividing device that converts and outputs
Convert the digital data D according to the following rules
Then, n (n is an integer of 2 or more) output codes X ₀ ,
A conversion means for dividing into X ₁ , ..., X _n-1 and n output
At least two channels X ₀ , X ₁ , ..., X _n-1
Features and to Lud over data dividing device further comprising a channel combining means for combining the channel. Rule: Input _n output codes X ₀ , X ₁ , ..., X _n-1
The relationship with the digital data D is D = K ₀ X ₀ + K ₁ X
₁ + ... + K _n-1 X _n-1 (K ₀ , K ₁ , ..., K _n-1 are real
Expressed as number), the output code X _0, X _1, ..., from X _n-1
Input digital data so that input D can be uniquely obtained.
Output from the data D code X _0, X _1, to convert ..., the X _n-1
It 4. An input digital data D is output to two output units.
It is characterized in that it is configured to be divided into a mode X and a mode Y.
The data division device according to claim 3 . 5. The input digital data D and the two
Output code X, Y is D = 2X + Y or D =
5. The data division device according to claim 4, wherein the data division ratio is 3X + Y. 6. A plurality of input digital data are output.
Input data in a data dividing device that converts and outputs
Convert the digital data D according to the following rules
Then, n (n is an integer of 2 or more) output codes X ₀ ,
A conversion means for dividing into X ₁ , ..., X _n-1 and n output
At least two channels X ₀ , X ₁ , ..., X _n-1
Features and to Lud over data dividing device further comprising a channel combining means for combining the channel. Rule: One set of all input digital data is at most t
Input digital data (t is an integer)
Divided into sets including each digital data in one set
Output code X ₀ and m ₁ pieces of different with the m ₀ or different values
An output code X ₁ with the value that will ... m _n-1 pieces of different values
Express uniquely by the combination of the output code X _n-1 that you have (m
₀ , m ₁ , ..., M _n-1 are integers, and m ₀ × m ₁ × ... × m
_n-1 ≧ n), representing digital data in a particular set
Output code X ₀ , X ₁ , ..., X _n-1 value combinations
Is not a combination that represents other digital data
I will 7. The rules defining the conversion means are as follows:
7. The data dividing device according to claim 6, wherein the data dividing device is defined as follows . Rule: One set of all input digital data is at most 4
Into sets containing different input digital data.
Output code X with two different values and two different
There is an output code Y with a value, each in the set
Digital data of the combination of the output codes X and Y
Can be uniquely represented by a digital data
The combination of the output code X and Y values that represent the data
Avoid combinations that represent digital data
It 8. The input digital data is converted into a plurality of data.
At least 1 in the data dividing device for dividing the data into
The relational expression D = c × X ^a is established for one divided data X and the input data D, and at least one divided data Y is input.
For the data D, equation D = b × Y features and to Lud over data dividing device that holds. However, a, b and c are constants. 9. The input digital data D is divided into two
9. The data dividing device according to claim 8, wherein the data dividing device is configured to divide the data into D1 and D2 . 10. The data division device according to claim 9, wherein the following relational expressions 1 and 2 are satisfied . Relational expression 1 D = X ^a + b × Y + Z Relational expression 2 D1 = c × X ^a , D2 = b × Y + Z or D1 = c × X ^a + Z, D2 = b × Y However, a, b and c are constants. is there. 11. Occurrence of data failure in a recording / transmission medium
If the probability is not uniform for that position, the
The data dividing device according to claim 10, wherein the data dividing device is configured to output the data. 12. Data is stored particularly at a position where the probability of failure occurrence is low.
11. The data division device according to claim 10 , wherein D1 is output and the data D2 is output to a position where the probability of failure occurrence is high . 13. The input digital data as it is
Means for outputting the input digital data
Split data into two so that relations 1 and 2 are satisfied,
Based on the input digital data.
Enable direct output of input data or input
Equipped with means to determine whether to enable divided output of data
Data dividing apparatus according to claim 10, wherein the obtaining.