JP3441049B2 - High frequency module - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency module, and more particularly to a high-frequency module applied to a mobile communication module and a broadcast receiving module (tuner) such as a TV or VTR. About. 2. Description of the Related Art A conventional high-frequency module (or also called a tuner) has a PLL loop (or PL).
The L phase locked loop is shown in FIG. 7 and will be described. In general, a PLL frequency synthesizer system is generally used in a heterodyne type device such as a transceiver or a communication device in order to generate a local oscillation signal frequency corresponding to each channel. In FIG. 7, a PLL phase locked loop 50 using a conventional PLL frequency synthesizer system adds a reference oscillator 51 to an IC 52 for PLL tuning, and on the other hand,
After the oscillation signal output of V CO 54 is that is power distribution, PL
The output is directly input to the L tuning IC 52, and the output forms a loop returning to the V CO 54 via the loop filter 53. The reference oscillator 51 is an oscillator that outputs a signal frequency serving as a clock for digitally operating the PLL,
VCO54 is Voltage Controlled O
The abbreviation for “scillator” or “voltage controlled oscillator”. The loop filter 53 is a low-pass filter (LPF: Low PassFi) that plays a role of removing a noise component of the output signal of the phase comparator inside the PLL tuning IC 52.
lter). [0005] However, the conventional method has the following problems. For example, as shown in FIG.
If the CO signal is 950 MHz and the response frequency of the PLL tuning IC 56 is 500 MHz or less, the response frequency band does not match.
There is a problem that it cannot be combined and does not operate. Also,
Such a loop circuit is called a PLL phase locked loop. In order to solve the above problem, for example, as shown in FIG.
Assuming that the O signal is 950 MHz and the response frequency of the PLL tuning IC 57 is 1000 MHz,
Although the VCO signal can be directly coupled to the PLL tuning IC 58, the operation characteristics (phase noise characteristics, C / N characteristics, S / N characteristics) may be caused by interference with the VCO and the PLL loop itself due to load fluctuation on the VCO output side. ) Is deteriorated or reduced. As another method, there is a method of adding a frequency multiplying circuit 60 as shown in FIG. For example, if the required VCO frequency is 950 MHz, half of 475 MHz is oscillated by the VCO 61 and PL
A PLL phase-locked loop is formed as an input to the L tuning IC 62, and a circuit for doubling the frequency, that is, a frequency multiplication circuit 60 is provided to obtain an output of 950 MHz. Will use the one of 500 MHz. However, in this case, there is no problem with the above-mentioned load fluctuation, but as described later, a slightly complicated problem may occur in some cases. FIG. 1 illustrates the problem of this conventional example.
11 and FIG. 11. FIG. 11 is a diagram illustrating the flow of frequencies, including the internal circuit of the PLL tuning IC 62, and FIG. 10 is an overall block diagram thereof. In FIG. 11, reference numeral 66 denotes a prescaler (Prescaler,
Frequency divider), 70 is a 1/2 prescaler, 63 is a power divider, and 60 is a frequency multiplier (× 2). The required VCO frequency f _TX is 930.125 MHZ, which is the frequency applied to the RF module for European cordless telephones. At this time, "/ N" 69 is usually called a programmable divider, and "/ R" 67 is usually called a reference divider, and the signal f _{VCO of the VCO} 61, respectively.
And the reference oscillator 51 (21.25 MHz) are frequency-divided to have the same comparison frequency (here, 3.125 KHz).
At 74, the phase is detected by the phase comparator 68. When these frequencies are expressed by equations, f _TX = 93 for one channel
0.0125MH _Z f _VCO = 465.00625MH _Z 4
65.00655 × 10 ⁶ = (3.125 × 10 ³ ) × 2
× N _{1 For} N ₁ = 744012 ch, f _TX = 93
0.0375MH _Z f _VCO = 465.01875MH _Z 4
65.01875 × 10 ⁶ = (3.125 × 10 ³ ) × 2
× N ₂ N ₂ = 74403 Thus, “N” and “R”
Is an integer (in this conventional example, N ₁ = 74401, or N ₂ =
74403, R = 3400), the comparison frequency f is f ₁ = 3.125 KHz, or f ₂ = 1.5625 KHz or less, or f ₃ = 0.7812.
Limited to a specific frequency, such as 5 KHz. However, for example, in a voice communication device, all of these frequencies fall within the voice band, so that interference occurs, and there is a considerable problem in voice quality. In FIG. 10, reference numeral 62 denotes a PLL tuning I
C and 51 are reference oscillators, 61 is a VCO, 63 is a power divider, 60 is a frequency multiplier (× 2), and 53 is a loop filter. In the case of FIG. 11, the comparison frequency is set to 3.1.
Although the frequency was set to 25 KHz, the comparison frequency was doubled to 3.KHz.
FIG. 1 shows a case where 125 kHz × 2 = 6.250 kHz.
3 is a 及 beauty 12, 13 described, including an internal circuit of IC76 for PLL tuning is a diagram illustrating a flow of frequency, FIG. 12 is a block diagram of a whole. In FIG. 13, reference numeral 76 denotes a PLL tuning I
C and 65 are reference oscillators, 66 is a prescaler, 77 is “/ R” (reference divider), 68 is a phase comparator, 69 is “/ N” (programmable divider), and 70 is a prescaler. In addition, V CO 7
1 of frequency f _VCO is 465.01875MH _Z, it is multiplied twice by the frequency multiplier circuit 73, the required VC
930.0125MH _Z next to O frequency f _TX, together with the output of the prescaler 70, via the power divider 72, is output. When these frequencies are represented by the formula, 1ch
Against, f _TX = 930.0125MH _Z 930.01
25 × 10 ⁶ = (6.250 × 10 ³ ) × 2 × N ₁ N ₁ =
For 744012 channels, f _TX = 930.0375
^{_{MH Z 930.0375 × 10 6 = (}} 6.250 × 1
0 ³ ) × 2 × N ₂ N ₂ = 74403 The comparison frequency is 6.25.
By setting the frequency as high as 0 KHz, the voice band can be set near the limit of the voice band, so that the problem of voice quality due to interference can be reduced. In FIG. 12, reference numeral 64 denotes a PLL tuning I
C and 65 are reference oscillators, 71 is a VCO, 72 is a power divider, 73 is a frequency multiplier (× 2), and 75 is a loop filter. The problems to be solved by the invention can be summarized as follows: (1) A circuit including a loss such as a power divider is represented by P
It is necessary to arrange in a feedback loop to the LL tuning IC. For example, if the power divider has a loss of 5 dB, the signal is lost by that much. (2) If a circuit (buffer circuit) such as a power divider is arranged in the feedback loop to the PLL tuning IC after the frequency multiplier, V
Although it is possible to solve the characteristic deterioration due to interference with CO ,
The interference to the PLL tuning IC circuit is improved only by 5 dB, for example, if the power divider has a loss of 5 dB. [0012] RF module according to the first aspect of the present invention, in order to solve the problems] includes a voltage controlled oscillator (VCO) having an IC and a frequency multiplier for the reference oscillator and PLL tuning, high Bandpass filter (HPF) or bandpass filter (B
PF) through the filter circuit.
A signal is input to the station IC, and the voltage-controlled oscillation circuit (VC
O) A leakage signal of an oscillating component from a collector pattern of a transistor of the Colpitts oscillator is input to the filter circuit. FIG . 1 is a block diagram showing a configuration of a high-frequency module according to a reference example for explaining an embodiment of the present invention. In FIG. 1, the present invention provides a P
A high-frequency module having a PLL phase-locked loop (PLL loop) based on the LL frequency synthesizer method (also known as
High-frequency module 1
0 adds the reference oscillator 11 to the PLL tuning IC 12;
On the other hand, the oscillation signal output of V CO 14 is after being power distribution is input to a PLL tuning for IC 12, its output through a loop filter 13, forming a loop back to V CO 14. The filter circuit 17 has an HPF (High Pa).
ss Filter, high-pass filter or BPF (Ban
d Pass Filter, band-limited filter). The VCO signal is 950 MHz and the PL
The response frequency of the L tuning IC 12 is 1000 MHz, and 19 indicates a high-frequency grounding point (GND point) of the VCO 14. The reference oscillator 11 is an oscillator that outputs a signal frequency serving as a clock for digitally operating the PLL, and the VCO 14 is a voltage control.
d Oscillator, abbreviation for voltage controlled oscillator. Further, the loop filter 13 is a noise removal filter in the line of V CO control voltage, the filter circuit 17 removes high frequency and Purisuasu of V CO, a high frequency filter for inputting the IC for PLL tuning And the loop filter 13 and the filter circuit 17
Are completely different in function and configuration. [0015] In the configuration of the high-frequency module as a reference example for the present invention, instead of feeding back the signal after frequency multiplication in PLL channel selection for IC64 as in the conventional example of FIG. 12, No original oscillation of the VCO The signal is taken out (route 16 in FIG. 1) and its output is passed through a high- pass filter (HP
F) or bandwidth limit filter (through a filter circuit 17 of the BPF) or the like, and inputs the PLL for tuning IC 12 (binding). Finally, for example, a high-pass filter (HPF) and / or a band-limited filter (B
PF), the same operation (using the same N, the same R, the same comparison frequency, for example, the VCO frequency f _TX as 930.0
_{125MHZ, N 1 = 74401, N} 2 = 74403,
R = 3400 or R = 1700, comparison frequency f 6.25
KHz, etc.). That is, by using the filter circuit 17 as an input to the PLL tuning IC 12, a signal equivalent to the signal after the multiplication is actually fed back despite being picked up from the original oscillation circuit (VCO 14). Then, the circuits are combined. The high- pass filter (HP) of the filter circuit 17
F) A band limiting filter (BPF) is usually used for removing a high frequency or the like and operating a PLL tuning IC with a regular frequency signal. The low pass filter (LPF)
This is a filter that passes low frequency components below a predetermined frequency and attenuates high frequency components above a predetermined frequency. On the other hand, a high-pass filter (HPF) is a filter that attenuates low-frequency components below a predetermined frequency and passes high-frequency components above a predetermined frequency. The band-limited filter (BPF) is a filter that passes only a predetermined frequency band and attenuates both a frequency component lower than the predetermined band and a frequency component higher than the predetermined band. Band-limited filter (B
PF) is a low-pass filter (LPF) or a high-pass filter (HP
Since the circuit scale becomes large and expensive compared to F), when the high frequency (harmonic) component is sufficiently suppressed, the purpose can be achieved by using a high-pass filter (HPF). . For example, a 465 MHz signal is
In order to input a 930 MHz signal without entering the tuning IC, use a high-pass filter (HPF) or a band-limited filter (BPF) to remove the 465 MHz signal, and convert the 930 MHz signal. Perform hollowing out with these filters. [0017] FIG. 2 is a block diagram showing a configuration of an RF module consisting an embodiment of the present invention.
The main difference between FIG . 2 and the reference example shown in FIG.
The output of the CO 14 is directly input (coupled) to the filter circuit 17 without passing through the power divider. (2) The high-frequency ground point 21 is connected to the output of the VCO 14
Is provided on a route 22 for inputting (coupling) the data. In FIG. 2, the high-frequency module 20 comprises:
In addition the reference oscillator 11 to the PLL tuning for IC 12, after the other hand, V CO 14 oscillation signal output arranged minute, PLL
The output is directly input to the tuning IC 12, and the output forms a loop returning to the VCO 14 via the loop filter 13. The output is passed through the loop filter 13 to the VCO
14, the output of the VCO 14 is distributed, and part of the output is applied to a double frequency multiplier 18, and part of the output of the VCO 14 is directly routed using a leak signal at a high frequency installed 21.
Is added to the filter circuit 17. The filter circuit 17 is a high pass filter (HPF).
High Pass Filter or BPF (Band Pass Filt)
er, band-limited filter). VCO
The signal is 950 MHz, the response frequency of the PLL tuning IC 12 is 1000 MHz, and 21 is a high-frequency grounding point (GND point) of the VCO oscillation circuit 14. [0019] Figure 3 is a first round <br/> circuit diagram example corresponding to the above reference example, an excerpt view of a circuit diagram of a cordless telephone frequency module of the European specifications. Transistor Tr1
Is an oscillation transistor of the VCO oscillation circuit 14,
The transistor Tr2 is a circuit transistor of the frequency multiplier 18. 11 is a reference oscillator. Also,
Loop filter 13, VCO circuit 14, filter circuit 17, power distributor 15, and frequency multiplier 18
Are shown in dotted lines. The terminal 30 of the PLL tuning IC 12 is connected to V C
O and filter circuit 17 ( BPF or HPF) and P
Feedback loop 32 connecting to LL tuning IC 12
The terminal 31 of the PLL tuning IC 12 is a loop 33 connecting the phase comparator of the PLL tuning IC, the loop filter 13 and the VCO . [0021] FIG. 4 is a second round <br/> circuit diagram example corresponding to the above reference example, the signal after the frequency multiplication circuit filter circuit 17 (B PF, or HPF) was filtered with 1 is a circuit diagram example of a tuner (high-frequency module) of a type that feeds back to a PLL tuning IC. FIG. The transistor Tr1 is an oscillation transistor of the VCO oscillation circuit 14, and the transistor Tr2 is a circuit transistor of the frequency multiplication circuit 18. 11 is a reference oscillator. Further, the loop filter 13, the VCO circuit 14, the power distributor 15, the filter circuit 17, and the frequency multiplying circuit 18 are shown by dotted lines. The terminal 34 of the PLL tuning IC 12 is a PLL.
Phase comparator and the loop filter 13 of the IC for channel selection and V C
A loop 36 connecting the O 14 and the PLL tuning IC 1
2 terminal 35 is a frequency multiplying circuit 18 and a PLL tuning IC.
12 is a feedback loop connecting the filter 12 and the filter circuit 17 ( BPF or HPF).
5 is connected. [0023] Figure 5 is a practical circuit diagram example of the form of the above you facilities. The filter circuit 17 is an HPF (high-pass filter)
Is shown. The transistor Tr1 is an oscillation transistor of the VCO oscillation circuit 14, and the transistor Tr2 is a circuit transistor of the frequency multiplication circuit 18. 11 is a reference oscillator. Further, the loop filter 13, the VCO circuit 14, the filter circuit 17, and the frequency multiplying circuit 18 are shown by dotted lines. The terminal 23 of the PLL tuning IC 12 is a PLL.
Phase comparator and the loop filter 13 of the IC for channel selection and V C
A 25 connecting the O 14, terminal 24 of the PLL for tuning IC12 is a feedback loop 22 connecting the V CO 14 and the filter circuit 17 (B PF, or HPF) and a PLL tuning IC12. The capacitor 28 is a high-frequency grounding capacitance component of the VCO 14, and a point 27 where there is no signal.
Of the Colpitts-type oscillator, and picks up a leakage signal of an oscillating component from the collector pattern of the transistor Tr1. I have. FIG. 6 shows an example of the printed circuit board pattern layout diagram of FIG. 5, FIG. 6 (a) is an overall printed circuit board pattern layout diagram, and FIG.
FIG. 3A is a partially enlarged view of FIG.
FIG. 3 is a partially enlarged view centering on r2, PLL tuning IC 12, capacitor 28, and point 27 where there is no signal originally. The capacitor 28 is a high-frequency grounding capacitance component of the VCO 14 and picks up a leak signal from the collector pattern of the transistor Tr1 of the Colpitts oscillator at the point 27 where there is no signal, and selects the PLL through the filter circuit 17. The input is made to the IC 12 for use. The examples of the high-frequency module according to the embodiment shown in FIGS. 3 to 6 are all examples applied to an RF block (high-frequency module) for a cordless telephone for European specifications, but are applied to other applications. For example,
Naturally, the present invention can be applied to a high-frequency module for mobile communication, a high-frequency module for broadcast reception such as a TV or VTR, and a high-frequency module such as a high-frequency module for satellite broadcast in the same manner. As described above, according to the high-frequency module according to the first aspect of the present invention, the voltage-controlled oscillator (VC) having the reference oscillator, the PLL tuning IC, and the frequency multiplier is provided.
O) and a high-pass filter (HPF) or band-limited filter
Through a filter circuit having a filter (BPF).
A signal is input to an LL tuning IC, and a leakage signal of an oscillation component from a collector pattern of a transistor of a Colpitts oscillator of the voltage controlled oscillator (VCO) is input to the filter circuit. . Therefore, originally, the present invention is based on the signal of the original oscillation (for example, 465 MHz).
z) is fed back to the PLL tuning IC, but by using a T-type HPF, harmonics (for example, 93
0 MHz) as if it were a frequency-multiplied signal.
By feeding back to the LL tuning IC, a PLL loop can be formed. Further, since it is not necessary to use a power divider, there is no power loss, the PLL can be fed back, and a PLL loop can be formed with a required 930 MHz signal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a high-frequency module according to a reference example of the present invention. Is a block diagram showing a configuration of an RF module consisting an embodiment of the present invention; FIG. FIG. 3 is an example of an actual circuit diagram of a high-frequency module according to a reference example of the present invention. FIG. 4 is another example of an actual circuit diagram of the high-frequency module according to the reference example of the present invention. 5 is a practical circuit diagram example of the high-frequency module consisting form of implementation of the present invention. 6 are the actual printed circuit board pattern layout of the high-frequency module consisting form of implementation of the present invention,
(A) is a layout diagram of the entire printed circuit board pattern, and (b) is a transistor Tr1, Tr2, (a) of (a).
FIG. 2 is a partially enlarged view centering on a PLL tuning IC 12, a capacitor 28, and a point 27 where there is no signal originally. FIG. 7 is a block diagram of a conventional high-frequency module. FIG. 8 is a block diagram of another conventional high-frequency module. FIG. 9 is a block diagram of another conventional high-frequency module. FIG. 10 is a block diagram of another conventional high-frequency module. FIG. 11 shows a PLL tuning channel I of a conventional high-frequency module.
It is a figure explaining the flow of the frequency described including the internal circuit of C64 (comparison frequency: 3.125 KHz). FIG. 12 is an overall block diagram of a conventional high-frequency module, which is related to FIG. 10; FIG. 13 shows a PLL tuning channel I of a conventional high-frequency module.
FIG. 3 is a diagram (comparison frequency: 6.250 KHz) for explaining the flow of frequencies described including the internal circuit of C64.
Related to 2. [Description of Signs] 10 High-frequency module 11 Reference oscillator 12 PLL tuning IC 13 Loop filter 14 VCO (voltage controlled oscillator) 15 Power divider 16 Route 17 Filter circuit (high- pass filter (HPF) or band-limited filtering) vessel containing (BPF), etc.) 18 RF grounding point of the frequency multiplier circuit 19 VCO 14 (the GND point) 20 high-frequency RF grounding point of the module 21 VCO oscillator circuit 14 (GND point) for 22 V CO 14 and PLL channel selection IC12 Feedback loop 23 to be connected 23 Terminal of IC 12 for selecting a PLL Terminal 25 of IC 12 for selecting a PLL Loop 27 connecting the phase comparator of the IC for selecting a PLL, the loop filter 13 and the VCO 14 Indicates a point where there is no signal originally. The collector pattern of the transistor Tr1 of Colpitts oscillator A phase comparator in the feedback loop 33 IC for PLL tuning connecting the terminals 32 V CO and PLL for tuning IC12 terminal 31 PLL for tuning IC12 point 28 condenser 30 for PLL tuning IC12 for picking up the leakage signal A loop 34 connecting the loop filter 13 and the VCO 14 A terminal 36 of the PLL tuning IC 12 A phase comparator of the PLL tuning IC 12 and a feed loop 37 connecting the loop filter 13 and the VCO 14 A terminal of the PLL tuning IC 12 35 transistor circuit of V CO 14 and the oscillation transistor transistor Tr2 frequency multiplier 18 of the feedback loop transistors Tr1 VCO oscillation circuit 14 connecting the PLL for tuning IC12

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04B 1/26 H03L ⁷ /06-7/23

Claims (1)

(57) [Claims] 1. High-frequency module for mobile communication, TV or V
A high-frequency module such as a high-frequency module for broadcast reception such as a TR and a high-frequency module for a satellite broadcast includes a voltage controlled oscillation circuit (VCO) having a reference oscillator, a PLL tuning IC, and a frequency multiplication circuit . (HP
F) or a filter having a band-limited filter (BPF)
Inputting a signal to the PLL tuning IC via a circuit, and inputting a leakage signal of an oscillating component from a collector pattern of a transistor of the Colpitts oscillator of the voltage controlled oscillator (VCO) to the filter circuit. High-frequency module featuring.