JP3435629B2 - Thermal infrared detector - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an infrared detecting device, and more particularly to a thermal infrared detecting device having amplification means and scanning means inside.

[0002]

2. Description of the Related Art In a thermal infrared detector that does not need to be cooled to an extremely low temperature, if the ambient temperature changes during measurement, the offset of the amplification system, including the sensitivity of the detection element, changes greatly. For this reason, it is desirable to perform offset compensation at any time, and conventionally, thermal-type infrared detectors have been provided with means for correcting offset, sensitivity unevenness, and the like.

As a method of compensating for the sensitivity unevenness of such a thermal infrared detector and the offset voltage of its amplifier circuit, there is, for example, the one disclosed in Japanese Patent Laid-Open No. 9-218090. In the above-mentioned thermal infrared detection device, although the electrical characteristics are the same as the detection element, a correction element configured so that the output signal does not change due to the incidence of infrared rays due to low thermal sensitivity is provided near the detection element. It is provided so as to correct sensitivity unevenness and offset of the detection element based on the output of the correction element.

That is, in the thermal infrared detecting device as described above, there is adopted a structure in which the constituent parts of the detecting element are thermally separated from the substrate in order to improve the sensitivity of the detecting element.
Alternatively, an infrared absorbing film may be formed to efficiently absorb incident infrared rays, or both may be provided. The correction element has a structure in which one or both of these are not applied, and therefore the output signal value of the correction element does not change even when infrared rays are incident, and outputs a constant signal value determined by the substrate temperature and the like. . Since the electrical characteristics of such a correction element are similar to those of the detection element, it is considered that the DC output fluctuation due to the substrate temperature and the DC output fluctuation due to deterioration over time are substantially the same. Therefore, when the signal of the correction element is input to the amplification circuit, a combined value such as the DC output fluctuation of the detection element and the offset voltage of the amplification circuit can be obtained. This is sample-held in the hold capacitor,
The hold value is used to add or subtract from the output value of the detection element to obtain a measured value in which the DC output fluctuation of the detection element and the offset voltage of the amplifier circuit are corrected. Further, by sequentially measuring a plurality of detection elements and sample-holding for each cycle, it is possible to immediately correct the output variation of the detection elements due to environmental changes such as temperature changes.

[0005]

However, in such a conventional thermal type infrared detection device, in the structure provided with a plurality of detection elements, the offset voltage measurement and the sample are performed once for each cycle of measurement of each detection element. Since it is necessary to hold, when the number of detection elements is large, the holding time of the hold capacitor becomes long, and the hold value as the reference potential for correction fluctuates due to the leak current. Therefore, there is a problem that the longer the holding time of the hold capacitor, the more inaccurate the voltage value after offset correction. In particular, thermal infrared detectors have low sensitivity, so S / N
If the measurement frequency is lowered so as to improve, the holding time of the hold capacitor becomes longer and the voltage value after offset correction becomes inaccurate.

On the other hand, in order to minimize the influence of the fluctuation of the hold value of the hold capacitor and improve the accuracy, if the offset voltage measurement and the sample hold are performed before the measurement of each detection element, the offset voltage measurement and the sample hold are performed. During the operation, the output of the amplifier circuit becomes zero, so
The output blank time will increase. Further, along with this, a new problem arises that the measurement time of one cycle (the cycle of signal output of the entire detection element) becomes long.

The present invention has been made in order to solve the problems of the prior art as described above. Even when the number of detecting elements is large, the offset can be corrected accurately and the output blank time can be reduced. It is an object of the present invention to provide a thermal infrared detector that does not occur.

[0008]

In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the invention described in claim 1, a detection element having a predetermined electric characteristic and infrared sensitivity and an infrared ray which is arranged close to the detection element and has the same electric characteristic as the detection element A correction element that has different sensitivities and whose output value does not change even when infrared rays enter,
Switching means for sequentially switching and outputting the signal of the detection element and the signal of the correction element; storage means for storing a value corresponding to the signal of the correction element as an offset correction value each time the signal of the correction element is given; Each time a signal from the detection element is given, a circuit that consists of a unit that corrects and outputs the signal using the correction value is provided as one block, and a plurality of blocks are provided. At the time when the memory is stored, the signal of the detection element is corrected and output in the other one block, and the state is controlled so as to sequentially circulate in each block,
It is configured to include.

As described above, the entire detection element is divided into a plurality of blocks, and the correction element is provided in each block.
At the time when the correction value is stored in one block, the signal of the detection element of another block is corrected and output,
Since it is configured to circulate in sequence, the correction value is updated every time the signal of one detection element is detected, so that the holding time of the storage means (hold capacitor) is maintained even if the number of detection elements increases. It can be the shortest. Therefore, the hold value fluctuation due to leakage current can be ignored,
A highly accurate offset correction value can be obtained. Further, at the time when the correction value is updated in one block, the signal of the detection element is corrected and output in the other blocks, so there is no blank time such that the output voltage of the output terminal becomes zero. Therefore, the blank time does not cause the measurement time of one cycle (the cycle of the signal output of the entire detection element) to become long.

According to the second aspect of the invention,
It has n (n> 2) blocks, and at the time when the correction value is stored in the i (1 ≦ i ≦ n) th block, the signal of the detection element is corrected in the i−1th block. Since i is sequentially moved from 1 to n and is circulated, the signal of the detection element of the block immediately after updating the correction value is corrected and output. It is possible to reduce the fluctuation of the hold value due to the leak current.

Further, in the invention described in claim 3,
Each block is provided with n (n> 2) blocks having m (m> 2) detection elements, and signals of n × m detection elements can be sequentially corrected and output.

[0012]

According to the present invention, since the value corresponding to the signal of the correction element is stored as the offset correction value every time the signal of one detection element is detected, the number of detection elements is reduced. Since the holding time of the storage means (hold capacitor) can be minimized even if it increases, the hold value fluctuation due to the leak current can be ignored, and an effect that a highly accurate offset correction value is obtained can be obtained. Further, at the time when the value corresponding to the signal of the correction element is stored as the correction value in one block, the signal of the detection element is corrected and output in the other block, so that the output voltage of the output terminal is zero. There is no blank time to become. For this reason,
There is an advantage that the blanking time does not lengthen the cycle of signal output of all the detection elements.

[0013]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention. The circuit shown in FIG. 1 is composed of two blocks (A) and (B) (portions encircled by broken lines), and for portions having the same name and function, A or B is added to the same number. The following mainly describes the block (A).

The detection elements 1A, 2A, 3A, 4A and the correction element 5A are closely arranged in a line. Each detection element is, for example, a microstructured element formed on a semiconductor substrate, and is configured by alternately connecting a P-type thermopile and an N-type thermopile with a hot junction and a cold junction, and the hot junction has a substrate. Is thermally separated (for example, provided on the cavity of the substrate), and A is provided on the hot junction.
An infrared absorbing film such as a u black film is provided. Therefore, when infrared rays enter, a temperature difference occurs between the hot junction and the cold junction, and an output corresponding to the temperature difference is transmitted. On the other hand, the correction element is the same as the detection element in that the hot junction and the cold junction form a P-type thermopile and an N-type thermopile, but the hot junction is not thermally separated from the substrate (on the substrate. Direct installation),
Moreover, no infrared absorption film is provided on the hot junction. Therefore, since there is no temperature difference between the hot junction and the cold junction, the output corresponding to infrared rays is not produced. The details of the structures of the detection element and the correction element are described in the above-mentioned conventional example (JP-A-9-218090).

The positive side outputs of the detection elements and the correction elements are respectively connected to the switching transistors 11A and 12A.
A, 13A, 14A, 41A, 42A, 43A, 44
It is connected to the plus bus line 32A through A and 61A. The negative output of each detection element and correction element is connected to the negative bus line 33A.
This 33A is a reference potential. The plus bus line 32A and the minus bus line 33A are connected to an amplifier circuit 7A (a portion surrounded by a broken line), and the amplifier circuit 7A amplifies and outputs a signal on the plus bus line 32A. This amplifier circuit 7A
The output of is connected to the offset correction circuit 8A.

The offset correction circuit 8A (the portion surrounded by a broken line) is basically a non-inverting amplifier composed of an operational amplifier 81A and resistors 82A and 83A, and is composed of a sample transistor 84A and a hold capacitor 85A. The output line 34A of the amplifier circuit 7A is used as one comparison input of the operational amplifier 81A, and the sample transistor 8
It is applied to the hold capacitor 85A via 4A.
The terminal voltage of the hold capacitor 85A is the resistance 82A.
Is used as the other comparison input of the operational amplifier 81A.
The output line 35A of the offset correction circuit 8A is connected to the output terminal 110 via the switching transistor 91A.

The signal line 101 of the block scanning circuit 100
41A, 42A, 43A, 44 of the (A) block
The gates of the transistors A, 91A and 61B, 84B of the (B) block are connected. Similarly, signal line 1
02 is 41B, 42B, 43B, 44 of the (B) block
B, 91B and 61A, 84A of the (A) block are connected to the gates of the transistors. That is,
In the (A) block and the (B) block, the signal line 101
And 102 are connected to opposite element groups. The signal line 101 of the block scanning circuit 100 is also connected to the input of the detection element address scanning circuit 6.

Output terminal 2 of detection element address scanning circuit 6
1, 22, 23, and 24 are 11A of the (A) block,
11 of 12A, 13A, 14A and (B) block
B, 12B, 13B, and 14B are sequentially connected to the gates of the transistors.

Next, FIG. 2 is a timing chart showing signal waveforms in each part of the circuit of FIG. The operation of the configuration shown in FIG. 1 will be described below with reference to FIG.

In FIG. 2, (a) and (b) respectively show waveforms from the output terminals 101 and 102 of the block scanning circuit 100, and (c), (d), (e) and (f) are detected respectively. Output terminals 21, 22, 2 of the element address scanning circuit 6
Waveforms from 3 and 24 are shown, (g) and (h) show signals on the plus bus lines 32A and 32B, and (i) shows an output from the output terminal 110.

Output terminal 101 of block scanning circuit 100
As shown in (a) and (b), the signal waveforms of and 102 are sequentially output with "H" and "L" alternately and in opposite phases to each other. The signals at the output terminal 101 are the switching transistors 41A, 42A, 43A, 4A of the (A) block.
4A, 91A and (B) are sent to the gates of 61B and 84B of the block, and the signal at the output terminal 102 is (B).
Block switching transistors 41B, 42B,
43B, 44B, 91B and 61 of the (A) block
A, sent to the gate of 84A. Therefore, each switching transistor is turned on when the signal is "H".
The output terminal 2 of the detection element address scanning circuit 6 is synchronized with the signal of the output terminal 101 of the block scanning circuit 100.
1, 22, 23, and 24 are (c), (d), (e),
As shown in (f), "H" signals are sequentially output. This signal is the switching transistor 11 of the (A) block.
A, 12A, 13A, 14A and (B) block 1
It is sent to the gates of 1B, 12B, 13B, 14B in sequence,
The corresponding switching transistors sequentially turn on.

Hereinafter, description will be made in order of time. First, time t =
In TE, the signal at the output terminal 102 shown in (b) is “H”.
Therefore, the switching transistor 61A is turned on (at this time, 101 is “L”, so the transistor 41A
44A is turned off), and the output of the correction element 5A is input to the offset correction circuit 8A via the amplifier circuit 7A. Since the sample transistor 84A is also turned on at this time, the output of the correction element 5A, that is, the offset voltage is input to the hold capacitor 85A. Next, when the signal at the output terminal 102 becomes "L", the sample transistor 84A is turned off, and the above offset voltage is stored in the hold capacitor 85A. This offset voltage is connected to the negative side input of the operational amplifier 81B.

Next, at time t = TA, the signal of the output terminal 101 shown in (a) and the output terminal 21 shown in (c).
Since both signals become "H", the switching transistors 11A and 41A are turned on, and the output of the detection element 1A as shown in G1 of (g) is sent to the plus bus line 32A, which is passed through the amplifier circuit 7A. Offset correction circuit 8
Enter in A. At this time, the output terminal 1 shown in (b)
Since the signal of 02 is "L" and the sample transistor 84A is off, the output of the detection element 1A is the hold capacitor 8
Do not enter in 5A.

Operational amplifier 81 of offset correction circuit 8A
A outputs a voltage that is the difference between the input output (G1) of the detection element 1A and the offset voltage stored in the hold capacitor 85A. As a result, the offset voltage is removed from the output (G1) of the detection element 1A, and the accurate output signal I1 shown at (i) at time t = TA is output from the output terminal 110 to the outside.

On the other hand, (B) at the above time t = TA
In the block, the output terminal 10 of the block scanning circuit 100
Since the "H" signal of (a) is output from 1 (a), the switching transistor 61B is turned on, and the output of the correction element 5B is sent to the plus bus line 32B as shown by the signal H1 of (h). This signal is amplified by the amplifier circuit 7B and then appears as an offset voltage on the signal line 34B.
This offset voltage is input to the offset correction circuit 8B. At this time, since the sample transistor 84B is turned on, a voltage corresponding to the offset voltage is generated in the hold capacitor 85B. Next, when the signal (a) from the output terminal 101 changes from the "H" signal to the "L" signal, the switching transistor 61B and the sample transistor 84B are turned off, the voltage of the hold capacitor 85B is fixed, and the above offset voltage becomes Saved.

Next, at time t = TB, (b) and (c)
Signal becomes "H", the output signal of the detection element 1B is amplified by the amplifier circuit 7B to become the H2 signal, the offset voltage is corrected by the offset correction circuit 8B, and the output terminal 1 is output.
It is output as I2 signal from 10. At this time, in the block (A), the output of the correction element 5A is read into the hold capacitor 85A as an offset voltage as described above,
Retained.

As described above, the output terminal 10 shown in FIG.
Every time the output of 1 and the output of the output terminal 102 shown in (b) are switched to “H” and “L” alternately, the offset voltage of the correction element is changed in the (A) block and the (B) block. Reading and saving and signal detection of the detection element are alternately performed. Further, every time the signal at each output terminal 21, 22, 23, 24 of the detection element address scanning circuit 6 becomes “H”, the signal of the corresponding detection element is read out, and the offset correction circuit performs the same operation as described above. The offset voltage is removed, and an accurate output signal is output from the output terminal 110 to the outside.

As described above, since the offset voltage is detected and held by the correction element every time one detection element is measured, the holding time of the hold capacitor can be minimized even if the number of detection elements increases. . for that reason,
The hold value variation due to the leak current can be reduced to a negligible level, and a highly accurate offset correction value can be obtained.

Further, since two or more blocks having the same function are provided, and while the detection element is being measured in one block, the offset voltage is detected and held in the next block, the output voltage at the output terminal is There is no blank time that is zero. Therefore, the blank time does not cause a problem that the cycle of signal output of all the detection elements, that is, the measurement time of one cycle becomes long.

In the embodiment shown in FIG. 1, the whole detecting element is divided into two blocks (A) and (B) and these blocks are switched alternately.
It may be configured to have three or more blocks and switch them sequentially. In that case, for example, two signal lines are provided from the block scanning circuit 100 to give a signal for ON / OFF controlling the signal of the detection element and a signal for ON / OFF control of the signal of the correction element for each block. Set the former signal to "H" in the block that reads the signal,
For the block in which the offset voltage is read and stored by the correction element, the latter signal may be set to “H”, all other signals may be set to “L”, and the state may be sequentially moved for each block. For example, in the case of n blocks, at the time when the offset voltage is read and stored in the i (1 ≦ i ≦ n) th block, the signal of the detection element is read in the i−1th block, i is 1
If the configuration is such that it is sequentially moved from 1 to n and is circulated, the signal of the detection element is always read immediately after updating the offset voltage, so that the fluctuation of the hold value due to the leak current can be made particularly small. A highly accurate offset correction value can be obtained.

Further, in the case of having n × m detection elements as a whole, it is divided into n (n> 2) blocks each having m (m> 2) detection elements, and i (1 ≦ i) When the signal of one detection element is corrected and output in the (n) th block, it moves to the (i + 1) th block, i is sequentially moved from 1 to n, and it is circulated, and within each block. The signal of the k-th (1 ≦ k ≦ m) -th detection element is corrected and output, k is sequentially moved from 1 to m every time the block is in order, and this is circulated, so that n × m The signal of the detection element can be sequentially corrected and output. In this case, the timing of reading and storing the signal of the correction element and the detection of the signal of the detection element are the same as those described above. The same applies to the fact that no blank time is generated.

Further, in the circuit of FIG. 1, since the block scanning circuit 100 is provided and the switching timing of the detection element is controlled by the signal of the block scanning circuit, it is necessary to provide the element address scanning circuit for each block. However, the circuit scale becomes smaller. Also regarding the layout, since one switching transistor for one detection element and one signal wiring for each block are added, the increase in the detection element arrangement interval is small.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing signal waveforms in various parts of the circuit of FIG.

[Explanation of symbols]

1A to 4A ... Detection element 1B to 4B ... Detection element 5A, 5B ... Correction element 6 ... Detection element address scanning circuit 7A, 7B ... Amplifier circuit 8A, 8B ... Offset correction circuit 11A-14A ... Switching transistor 11B-14B ... Switching transistor 21-24 ... Output terminals 32A, 32B of detection element address scanning circuit ... Positive bus lines 33A, 33B ... Minus bus lines 34A, 34B ... Output lines 35A, 35B of amplifier circuit ... Output lines 41A-44A of offset correction circuit ... Switching Transistors 41B to 44B ... Switching transistors 61A, 61B ... Switching transistors 81A, 81B ... Operational amplifiers 82A, 83A
... resistors 82B, 83B ... resistors 84A, 84B
... Sample transistors 85A and 85B ... Hold capacitors 91A and 91B ... Switching transistors 10
0 ... Block scanning circuit 101, 102 ... Output terminal of block scanning circuit 11
0 ... Output terminal

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01J 5/00-5/62 G01J 1/00-1/60 H04N 5/33 JISST file (JOIS)

Claims (3)

(57) [Claims] 1. A detection element having predetermined electric characteristics and infrared sensitivity, and a detection element which is disposed close to the detection element and has the same electric characteristics as the detection element but different infrared sensitivity. A correction element whose output value does not change even when incident, a switching means for sequentially switching and outputting the signal of the detection element and the signal of the correction element, and a value corresponding to each time the signal of the correction element is given Is stored as a correction value of the offset, and means for correcting and outputting the signal of the detection element each time the signal of the detection element is given, is output as one block, At the time when the correction value is stored in one block, the signal of the detection element is corrected and output in the other block, and the state is in order. Means for controlling so as to circulate the respective blocks, the thermal type infrared sensing device characterized by comprising a. 2. Having n (n> 2) blocks, i (1
At the time when the correction value is stored in the ≦ i ≦ n) th block, the signal of the detection element is corrected and output in the i−1th block, and i is sequentially moved from 1 to n. The signal of the detection element of the block immediately after updating the offset correction value is always output by circulating the offset correction value.
The thermal infrared detection device described in. 3. An n (n> 2) block having m (m> 2) detector elements for each block, and i (1 ≦ i)
When the signal of one detection element is corrected and output in the (n) th block, the block moves to the (i + 1) th block.
Sequentially move from 1 to n, circulate it, and
Within each block, the signal of the k-th (1 ≦ k ≦ m) -th detection element is corrected and output, and k is set to 1 every time the block makes a turn.
From m to m, and by circulating it,
The thermal infrared detection device according to claim 1 or 2, wherein the signals of nxm detection elements are sequentially corrected and output.