JP3425430B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.
In particular, the present invention relates to a device having an internal power supply step-down circuit. 2. Description of the Related Art In semiconductor integrated circuits, miniaturization of elements
5V is applied as the external power supply voltage Vcc as
Gate oxide film is destroyed, hot carriers, etc.
For example, the reliability may decrease. Therefore,
Miniaturized elements, especially transformers in semiconductor storage devices
Reduces voltage stress to ensure transistor reliability
To reduce the external power supply voltage inside the chip
It is necessary to provide a source step-down circuit. Also,
Power consumption is reduced by lowering the power supply voltage inside the
It can also be done. As a result, portable personal computers
Battery backup time for electronic devices such as computers
Can be extended. FIG. 21 shows a configuration of a conventional internal power supply step-down circuit.
Show. This circuit includes a reference potential generation circuit 121 and an internal power supply.
A P-channel transistor P103 for driving the
Controls switching of P-channel transistor P103
-Channel transistors P101 and P10
2, composed of N-channel transistors N101 to N103
Current mirror type differential amplifying section 122 and a resistor R101
And R102. [0004] The reference potential generating circuit 121 is connected to an external power supply voltage.
Vcc is supplied to generate a reference potential Vref. Also,
The internal power output from P-channel transistor P103
The difference between the source voltage Vint and the ground voltage Vss is the resistance R101 and
The potential is divided by R102 to generate a potential VA. The difference between the reference potential Vref and the potential VA is the differential.
N channel transistors N101 and N of amplifying section 122
It is input to each of the gates 102. External power supply voltage V
Considering the case where cc is low, the potential VA is equal to the differential reference potential Vre.
lower than f. At this time, the output voltage of the differential amplifier 122 is
The voltage VB goes low, and the P-channel transistor P
103 turns on. Here, the P-channel transistor P
The resistance value of the resistor 103 is sufficient for the resistors R101 and R102.
By setting the dimensions so that
Internal power supply voltage Vint equal to the internal power supply voltage Vcc.
You. On the contrary, when the external power supply voltage Vcc is high,
The potential VA becomes higher than the reference potential Vref. At this time
The output voltage VB of the differential amplifier 122 becomes high level,
P-channel transistor P103 turns off. This
The level of the internal power supply voltage Vint is determined by the resistances R101 and R101.
It decreases because of discharging through 102. Where
When the potential VA becomes lower than the reference potential Vref, the P-channel
Since the transistor P103 is turned on again, the internal power supply
The pressure Vint is kept at a constant level. As a result, the potential V
At the point where A becomes equal to the reference potential Vref, the internal power supply voltage Vref
int will be kept constant. As described above, external power supply voltage Vcc is low.
In this case, the reference voltage Vref> potential VA, and almost
An internal power supply voltage Vint equal to the source voltage Vcc is obtained. When the external power supply voltage Vcc is high,
When the voltage Vref becomes equal to the potential VA, the internal power supply voltage Vint becomes one.
Is kept constant. Next, a specific example of the reference potential generation circuit 121 will be described.
FIG. 22 shows the circuit configuration. Also, the internal
External power supply voltage Vcc between power supply voltage Vint and reference voltage Vref
FIG. 23 shows the characteristics with respect to. The reference voltage generation circuit 121
1 and a circuit 132. The circuit 131 is outside
Reference voltage when the unit power supply voltage Vcc is in the range of 0 to Vcur.
This determines the characteristics of the position Vref. Here, the voltage V
cur is the voltage of the reference voltage Vref in the circuit 132 described later.
Equivalent to the external power supply voltage Vcc when the voltage becomes equal to VE
Things. Further, the circuit 132 is configured such that the power supply voltage Vcc is the voltage V
The characteristic of the reference potential Vref when it is larger than CUR
To decide. In the circuit 131, the external power supply voltage Vcc and
The resistors R103 and R104 are connected in series with the ground voltage Vss.
P-channel transistor P104 is connected,
The voltage V is applied from the node connecting the resistors R103 and R104.
c occurs. Here, the resistance value of the resistor R103 is
The resistance value is set sufficiently higher than the resistance value of the reference numeral 104. This
Therefore, the voltage Vc almost depends on the external power supply voltage Vcc.
To a certain level. The voltage Vc is a P-channel transistor
P105 and P106, N-channel transistor N10
4 to N106.
You. Further, between the external power supply voltage Vcc and the ground voltage Vss,
A P-channel transistor P107, a resistor R105,
R106 and R106 are connected in series.
The voltage VD is output from the node between the node and the node 106. this
The voltages VD and Vc are input to the differential amplifier 141. This
In the circuit 131 of FIG.
Similarly, when the external power supply voltage Vcc is high, the P-channel
A node connecting the transistor P107 and the resistor R105
The reference voltage Vref output from the switch is kept constant.
You. However, in the circuit in FIG.
The resistance value of the star P103 is higher than that of the resistors R101 and R102.
Although set to be sufficiently small, the circuit 131
By setting the resistance value of the channel transistor P107 large
I have. This is because the P-channel transistor P107 and the resistor
The voltage is divided by resistance division by the anti-R105 and the resistance R106.
This is so that VD can be set. The circuit 132 includes resistors R107 and R108
And a differential amplifier 142 and a P-channel as a driving transistor.
An N-channel transistor P108 is provided. Differential amplifier 1
42 has an external power supply voltage V through resistors R107 and R108.
The potential VE obtained by dividing cc and the reference potential Vref are input.
Be compared. The external power supply voltage Vcc is in the range of 0 to Vcur.
The reference potential Vref is higher than the potential VE.
You. In this case, the output voltage VG of the differential amplifier 142 is
Becomes high level and the P-channel transistor P108
Turn off. As a result, the level of the reference potential Vref is
131 only. The external power supply voltage Vcc is higher than the voltage Vcur.
Then, the reference voltage Vref becomes lower than the potential VE.
You. The output voltage VG of the differential amplifier 142 becomes low level.
As a result, the P-channel transistor P108 turns on. P
When the channel transistor P108 is turned on, the circuit 131
Voltage VD rises. Thereby, the differential of the circuit 131
The output voltage VF of the amplifier 141 becomes high level,
The channel transistor P107 turns off. As a result,
The level of the reference voltage Vref is determined by the circuit 132.
Will be. When the external power supply voltage Vcc further increases,
The reference voltage Vref also increases. In FIG. 23, the external power supply voltage Vcc is
In the range higher than the voltage Vcur, the internal power supply voltage Vint rises.
It is rising. This is because the external power supply voltage Vcc is 5V.
The voltage usage range of the product is 4.5V to 5.5V.
This is because the burn-in test is performed at a higher voltage. [0017] Conventionally, as described above,
Circuit to reduce the voltage to generate the internal power supply voltage.
Was. By the way, in recent years, portable electronic devices have reduced power consumption.
And in DRAMs as well as CPUs,
The demand for power supply voltage has increased. Therefore, in the same circuit, the external power supply voltage Vcc is
For example, it can be used for 5V products and 3.3V products
Has been desired. In this case, the external power supply voltage Vcc
Is 5V, the internal power supply step-down circuit
A path is required, but is unnecessary at 3.3V. When
However, conventionally, even when the external power supply voltage Vcc is 3.3 V,
Since the internal power supply step-down circuit was operated, current consumption was reduced.
There was a problem that it could not be reduced. In FIG. 21, the internal power supply voltage Vin
t is generated by the P-channel transistor P103.
Therefore, setting the dimensions of the transistor is important. Outside
When the power supply voltage Vcc is 3.3 V, a P-channel transistor
The size of the star P103 must be as large as possible.
This is because the voltage drops when the size of this transistor is small
The internal power supply voltage Vint lower than 3.3 V
Because you can't get it. Conversely, when the external power supply voltage Vcc is high,
Smaller transistor size leads to lower operating margin
Is less affected. Rather, in this case the P-channel traffic
The size of transistor P103 is set small and switching
The noise needs to be low. As described above, when the external power supply voltage Vcc is low
The optimal dimensions of the driving transistor are different between
However, in the past, it was not possible to respond. Further, another device having an internal power supply step-down circuit is provided.
As an example of the device, there is one provided with an output buffer circuit.
The output transistor in the output buffer circuit is
When the source voltage Vcc is low, the conductance is low and the current
Driving capacity decreases. Driving capacity of this output transistor
Lowers the access speed. This phenomenon
In order to prevent this, increase the size of the output transistor.
There is a need to. However, when the external power supply voltage Vcc is high
Increases the switching noise of the transistor,
Low margin for high level and low level of force signal
The disadvantage is that it falls. In addition, in a device having an internal power supply step-down circuit,
Some have a sense amplifier circuit. Here,
The sense amplifier circuit includes a P-channel transistor
From channel sense amplifier and N-channel transistor
Of N-channel sense amplifiers
No. When reading data stored in a memory cell,
A common source for operating the P-channel sense amplifier
The node is charged using the external power supply voltage Vcc, and this potential is
When the internal power supply voltage Vint is reached, charging may stop.
Done. When charging the common source node,
The reference voltage VRSAP of the constant current circuit used for charging is
If the switching noise is large when the voltage Vcc is high
It is necessary to set it low so that it does not occur. However, outside
When the external power supply voltage Vcc is high when the power supply voltage Vcc is low
It takes longer to charge if the same reference voltage VRSAP is used
take time. As a result, the bit line
There was a problem that the tore could not be performed sufficiently. The present invention has been made in view of the above circumstances.
The same circuit configuration can be used even when the external power supply voltage is different.
Can be used to reduce power consumption and prevent a decrease in operating margin.
Aim to provide a semiconductor device capable of achieving
Target. According to the present invention, there is provided a semiconductor device comprising:
A control input terminal connected to the bonding pad;
Discharging means for discharging a control input terminal; and the control input terminal
Two inverters connected in series between the
And the bonding pad is a power supply voltage terminal.
A first control signal from the control output terminal when connected to
Is output, and the bonding pad is connected to the power supply voltage terminal.
The power supply voltage is not supplied to the control terminal and the discharge
When discharged by the stage, a second control signal is applied to the control output.
A control circuit output from the input terminal; and
When outputting the first control signal, outputting the first reference voltage
A first reference voltage generating circuit, and the control circuit
Output the second reference voltage when outputting the second control signal.
A second reference voltage generating circuit, and the first and second reference voltages.
A pressure generating circuit connected to the first and second control signals.
And the control circuit controls the first control signal
When the first reference voltage is supplied,
And when the control circuit outputs the second control signal
Switch for receiving and outputting the second reference voltage
And a circuit. Alternatively, the semiconductor device of the present invention
The fuse connected between the source voltage terminal and the node
Discharging means for discharging the node, the node and a control output
And an inverter connected between the terminal and the terminal.
In the first case where the fuse is not blown, the control output terminal
Output a first control signal, and the fuse is blown.
In the second case, the node is discharged by the discharging means.
Control output of a second control signal from the control output terminal.
A control circuit, and the control circuit outputs the first control signal.
Generates a first reference voltage when the first reference voltage is generated.
Circuit and the control circuit output the second control signal
When the second reference voltage generation circuit outputs the second reference voltage
And the first and second reference voltage generating circuits,
Controlled by one of the first and second control signals,
When the control circuit outputs the first control signal,
1 and outputs the reference voltage.
When the second control signal is output, the second reference voltage is
And a switch circuit for receiving and outputting. The semiconductor device of the present invention has a bonding package.
A control input terminal connected to the
Charging means for charging, the control input terminal and the control output terminal
And an inverter connected between the
Pad is not connected to the ground terminal and the control input terminal is
In the first case of charging by the charging means, the control
Outputting a first control signal from an output terminal;
In the second case where the pad is connected to the ground terminal,
A control circuit for outputting a second control signal from a control output terminal;
When the control circuit outputs the first control signal,
A first reference voltage generating circuit for outputting a first reference voltage;
When the control circuit outputs the second control signal, the second
A second reference voltage generating circuit that outputs a reference voltage of
Connected to first and second reference voltage generating circuits;
Controlled by one of the second control signals, wherein the control circuit
When the first control signal is output, the first reference voltage is output.
And the control circuit outputs the second control signal.
When the signal is output, the second reference voltage is given.
And a switch circuit for outputting. The semiconductor device according to the present invention has a bonding package.
Release the control input terminal connected to the
Discharging means for charging, the control input terminal and the control output terminal
And an inverter connected between the
In the first case where the pad is connected to the supply voltage terminal,
Outputting a first control signal from the control output terminal,
Pad is not connected to the power supply voltage terminal,
In a second case where the terminal is discharged by said discharging means,
A control circuit for outputting a second control signal from the control output terminal;
And the control circuit has output the first control signal.
A first substrate voltage generating circuit for outputting a first substrate voltage
And the control circuit has output the second control signal.
A second substrate voltage generating circuit for outputting a second substrate voltage
Connected to the first and second substrate voltage generating circuits,
Control by one of the first and second control signals;
When the control circuit outputs the first control signal, the first control signal
And outputs the substrate voltage.
When the second control signal is output, the second substrate voltage is applied.
And a switch circuit that outputs the signal.
I do. The semiconductor device of the present invention has a power supply voltage terminal
Discharge the fuse connected between the
Between the node and the control output terminal.
Connected to the inverter, wherein the fuse is blown.
The first control signal from the control output terminal
In the second case where the fuse is blown,
The node is discharged by the discharging means, and the control output
A control circuit for outputting a second control signal from a force terminal;
When the control circuit outputs the first control signal, the first
A first substrate voltage generating circuit for outputting a substrate voltage;
When the control circuit outputs the second control signal, the second base signal is output.
A second substrate voltage generating circuit for outputting a plate voltage;
1, connected to the second substrate voltage generation circuit,
2 is controlled by one of the two control signals,
When the first control signal is output, the first substrate voltage
And the control circuit outputs the second control signal.
Signal is output, the second substrate voltage is given.
And a switch circuit for inputting power. The semiconductor device according to the present invention has a bonding package.
A control input terminal connected to the
Charging means for charging, the control input terminal and the control output terminal
And an inverter connected between the
Pad is not connected to the ground terminal and the control input terminal is
In the first case of charging by the charging means, the control
Outputting a first control signal from an output terminal;
In the second case where the pad is connected to the ground terminal,
A control circuit for outputting a second control signal from a control output terminal;
When the control circuit outputs the first control signal,
A first substrate voltage generating circuit for outputting one substrate voltage;
When the control circuit outputs the second control signal, the second
A second substrate voltage generation circuit that outputs a substrate voltage of
Connected to first and second substrate voltage generating circuits;
Controlled by one of the second control signals, wherein the control circuit
When the first control signal is output, the first substrate
And the control circuit outputs the second control signal.
When the signal is output, the second substrate voltage is given.
And a switch circuit for outputting. Further, the semiconductor device according to the present invention is characterized in that
A control input terminal connected to the pad, and the control input terminal
Discharging means for discharging the control input terminal and the control output terminal
And an inverter connected between the
Case where the pad is connected to the power supply voltage terminal
Output a first control signal from the control output terminal,
The bonding pad is not connected to the power supply voltage terminal.
A second field in which the control terminal is discharged by the discharging means.
Output a second control signal from the control output terminal.
A control circuit, wherein the control circuit outputs the first control signal
A first booster circuit that outputs a first boosted voltage
And the control circuit has output the second control signal.
A second booster circuit for outputting a second boosted voltage;
A first booster circuit connected to the first and second booster circuits;
And the control circuit is controlled by one of the control signals.
When the control signal is output, the first boosted voltage is applied.
And the control circuit outputs the second control signal.
Output, receiving the second boosted voltage
And a switch circuit. The semiconductor device of the present invention has a power supply voltage terminal
Discharge the fuse connected between the
Between the node and the control output terminal.
Connected to the inverter, wherein the fuse is blown.
The first control signal from the control output terminal
In the second case where the fuse is blown,
The node is discharged by the discharging means, and the control output
A control circuit for outputting a second control signal from a force terminal;
When the control circuit outputs the first control signal, the first
A first booster circuit for outputting a boosted voltage, and the control circuit
When the second control signal is output, the second boosted voltage is
A second booster circuit for outputting, and the first and second booster circuits
And controlled by one of the first and second control signals.
And the control circuit outputs the first control signal.
When the first boosted voltage is given and output,
When the control circuit outputs the second control signal, the second
And a switch circuit for receiving the boosted voltage and outputting the same.
It is characterized by having. Further, the semiconductor device of the present invention can
A control input terminal connected to the pad, and the control input terminal
Charging means for charging the control input terminal and the control output terminal
And an inverter connected between the
Is not connected to the ground terminal and the control input terminal
In a first case where the child is charged by the charging means,
Outputting a first control signal from a control output terminal;
In the second case where the pad is connected to the ground terminal,
A control circuit for outputting a second control signal from the control output terminal
And the control circuit has output the first control signal.
A first booster circuit for outputting a first boosted voltage,
When the control circuit outputs the second control signal, the second
A second booster circuit for outputting a boosted voltage, the first and second booster circuits;
Of the first and second control signals.
And the control circuit controls the first control signal
Is output, receiving the first boosted voltage and outputting
And the control circuit outputs the second control signal.
And a switch for receiving and outputting the second boosted voltage
And a circuit. The control circuit is
The first control when the connecting pad is connected to the power supply voltage terminal.
The bonding pad is connected to the power supply voltage terminal
Power supply is not supplied to the control terminal,
When the battery is more discharged, a second control signal is output and the first control signal is output.
A reference voltage generation circuit configured to generate a first reference voltage according to a first control signal;
And a second reference voltage generating circuit outputs a second control signal.
Output a second reference voltage according to
Is provided with a first reference voltage according to a first control signal.
And outputs the second reference voltage according to the second control signal.
Power. The control circuit replaces the bonding pad with a
The first field where the fuse is not blown.
The first and second criteria, depending on the second case that has been blown
A voltage is output. Control circuit charges instead of discharging means
If the bonding pad has a
In the first case that is not connected and the second case that is connected,
First and second reference voltages are output, respectively. 1st, 2nd
Output the first and second substrate voltages instead of the reference voltage
In the case of outputting the first and second boosted voltages,
Operate. Embodiments of the present invention will be described below.
This will be described with reference to the drawings. The semiconductor device according to the first embodiment of the present invention
The configuration of the device is shown in FIG. This device is shown in FIG.
Like the device, the external power supply voltage Vcc is supplied to
A reference potential generating circuit 11 for generating Vref, and an internal power supply
Operating P-channel transistor P13, resistor R11 and
Controls the operation of R12 and P-channel transistor P13
And a differential amplifying unit 10. In this embodiment,
Is a control circuit 1 for controlling the operation state of the differential amplifier 10.
2. Bonding pad supplied with external power supply voltage Vcc
13. A bonding pad for outputting the internal power supply voltage Vint
And a bonding pad 15 grounded.
The feature is that it is. The control circuit 12 includes a bonding pad 12
a, the bonding pad 12a and the ground voltage Vss end.
External power supply voltage Vcc is supplied to the gate.
N-channel transistor N13 and a bonding
P-channel transformer whose gate is commonly connected to
The transistor P14 and the N-channel transistor N14.
Inverter and a gate at the output terminal of this inverter
Commonly connected P-channel transistors P15 and N
An inverter composed of a channel transistor N15
The output terminal of the differential amplifier 10 is an N-channel transformer.
And an inverter connected to the source of the transistor N12.
ing. Here, the dimensions of the N-channel transistor N13
Is set smaller than other transistors,
N-channel transistor N15 is set large.
You. First, assume that the external power supply voltage Vcc is, for example, 5V.
If the value is equal to or greater than the predetermined value,
You. In this case, the control circuit 12 is in a state similar to FIG.
Yes, the bonding pad 12a is moved by another worker depending on the operator.
Not connected to the bonding pad. The N-channel transistor N13 has a gate
The external power supply voltage Vcc is input to the
Drain of pad 12a and N-channel transistor N13
The node connecting the terminal is maintained at the ground level. P
Channel transistor P14 and N-channel transistor
This low-level potential is input to the gate of N14.
The inverted high-level potential is a P-channel transistor
Input to the gates of P15 and N-channel transistor N15
Is forced. This P-channel transistor P15 and N channel
Inverted by an inverter consisting of a flannel transistor N15
And the potential VSSG output from this inverter is grounded.
The level becomes equal to the potential Vss. As a result, the N-channel transistor of the differential amplifier 10
The source of the transistor N12 is grounded.
It operates similarly to the circuit shown at 21. That is, the reference potential
The reference potential Vref generated by the generation circuit 11 and the potential difference
Vcc-Vss is a P-channel transistor P13 and a resistor R
11 and the potential VA divided by the resistor R12 increase differentially.
Input to the width section 10 and the P-channel according to the relative potential difference.
The on / off of the transistor P13 is controlled,
The constant internal power supply voltage Vint is output. Next, when the external power supply voltage Vcc is, for example, 3.3 V
If the value is lower than the specified value,
You. The bonding pad 12a of the control circuit 12 and an external
A bonding pad 13 to which a power supply voltage Vcc is supplied;
Bonding pad 14 that outputs internal power supply voltage Vint
Are connected by the bonding wire by the worker
Is short-circuited. As a result, the bonding
The potentials of the pads 12a, 13 and 14 are all equal to the external power supply voltage V
The same level as cc. In the control circuit 12, the bonding package
Whether the level of the node 12a is equal to the external power supply potential Vcc
The P-channel transistor P15 and the N-channel transistor
The output potential VSSG of the inverter comprising the transistor N15 is
It goes to the level of the external power supply voltage Vcc. This increases the differential
The source of the N-channel transistor N12 of the width portion 10
An external power supply voltage Vcc is supplied, and the differential amplifier 10
The device enters an operation state and no current consumption flows. Also, the standard
Consumption flowing through the potential generation circuit 11 and the resistors R11 and R12
There is no current. Here, the N-channel transistor N1
3 is in the on state, but as described above, this transistor
The dimensions of the data are small and the current consumption can be ignored.
Small enough. As described above, according to the first embodiment, the outside
When the power supply voltage Vcc is high, the control circuit 12
The dynamic amplifier 10 is not operated, and the current consumption of this part is reduced.
Is FIG. 6 shows the external power supply voltage Vcc and the standby state.
Shows the relationship with the current consumption ICC. Conventionally, external power supply voltage
Even if Vcc is as low as 3.3V, the differential amplifier
10 and the P-channel transistor P13 are operated.
Was. Therefore, as shown by line L1,
The current consumption was large. In contrast, in the present embodiment,
When the external power supply voltage Vcc is low, the differential amplifier 10 and P
Since the channel transistor P13 is not operated, the line L
As shown by 2, the standby current Icc is greatly reduced
Is done. Therefore, battery barriers in portable electronic devices
The backup time can be made longer than before. Conventionally, when the external power supply voltage Vcc is low,
In this case, due to the resistance of the P-channel transistor P13,
The internal power supply voltage Vint is lower than the internal power supply voltage Vcc.
Was output. In the present embodiment, the bonding
Since the external power supply voltage Vcc is supplied to the pad 14,
Voltage Vcc of the internal power supply voltage Vint
And output. Therefore, delays in access time and operation
It is possible to prevent adverse effects such as a decrease in resin. Further, a P-channel transformer for driving the internal power supply is provided.
The transistor P13 operates only when the external power supply voltage Vcc is high.
In this case, it is necessary to set the optimal size
Can suppress the generation of switching noise.
You. Next, the control circuit according to the first embodiment
FIG. 2 shows a twelfth modification. External power supply voltage Vcc terminal and ground voltage Vss terminal
Between the fuse F1 and the N-channel transistor N1.
6 are connected in series. This N-channel transistor
The external power supply voltage Vcc is supplied to the gate of the star N16.
You. Fuse F1 and N-channel transistor N16
P-channel transistor at the node connecting to the rain
Inverter composed of P16 and N-channel transistor N17
Is connected to the input terminal of the
G is output. When the external power supply voltage Vcc is high, FIG.
Used as indicated. Fuse F1 and N channel
The voltage of the node connecting the drain of the transistor N16
The level VEXTFU is at a high level. This potential VEXTFU
Are the P-channel transistor P16 and the N-channel transistor.
Inverted by the inverter composed of
The bell potential VSSG is output. This allows differential amplification
The unit 10 operates and outputs the reduced internal power supply voltage Vint.
Is done. When the external power supply voltage Vcc is low,
Fuse F1 is blown. The potential VEXTFU is at low level
And the potential VSSG becomes high level. Therefore, the differential
The amplifier 10 enters a non-operating state. FIG. 3 shows that when the external power supply voltage Vcc is low,
When the fuse is blown by the operator, the external power
An example of a circuit that outputs the voltage Vcc as the internal power supply voltage Vint
Show. Between external power supply voltage Vcc terminal and ground voltage Vss terminal
Fuse F2 and N-channel transistor N18
Connected to the column, and a P channel is connected to the node connecting the two.
Transistor P17 and N-channel transistor N19
And a P-channel transistor P18
And an inverter comprising N-channel transistor N20
Are connected in two stages. P-channel transistor P1
8 and N-channel transistor N20
Is connected to the gate of a P-channel transistor P19.
Connected and its drain connected to the external power supply voltage Vcc terminal
The source is connected to the terminal that outputs the internal power supply voltage Vint
Have been. In this circuit, when the external power supply voltage Vcc is high,
In this case, the fuse F2 is not blown by the operator and is shown in FIG.
It operates in the state where it was done. The potential VEXTFU becomes high level.
After passing through a two-stage inverter, a P-channel transistor
A high-level output is applied to the gate of the
I do. This allows the external power supply voltage Vcc terminal and the internal power supply
The terminal for outputting the pressure Vint is cut off. When the external power supply voltage Vcc is low,
Thus, the fuse F2 is blown. The potential VEXTFU is low
And the gate of the P-channel transistor P19
Is turned on in response to a low-level output. As a result,
Outputs external power supply voltage Vcc terminal and internal power supply voltage Vint
The terminal is connected. P-channel transistor P19
By increasing the dimensions as much as possible, the external power supply voltage Vcc
Output the same level of internal power supply voltage Vint as
it can. The N-channel transistor N18 is turned off.
Is in the state of
The current can be suppressed to a negligible level. The circuit shown in FIG. 2 and the circuit shown in FIG.
When the external power supply voltage Vcc is low,
The fuses F1 and F2 to blow,
The current consumption of unit 10 and P-channel transistor P13
While cutting, the external power supply voltage Vcc almost drops.
It can be output as the internal power supply voltage Vint without lowering
Wear. FIG. 4 shows a modification of the control circuit 12 in FIG.
Here is an example. The control circuit 12 in FIG. 1 operates at the level of the potential VSSG.
, The operation of the differential amplifier 10 is controlled. This
In contrast, the control circuit shown in FIG. 4 outputs the potential VSSG.
Connected between the input terminal and the ground voltage Vss terminal.
The operation of the differential amplifier 10 is controlled by controlling the conduction of the transistor.
They differ in that they control the work. The bonding pad 16 and the ground voltage terminal V
ss, an N-channel transistor N21 is connected,
The bonding pad 16 has a P-channel transistor.
A transistor P20 and an N-channel transistor N22.
The input terminal of the inverter is connected. This inverter
Output terminal is a terminal whose drain outputs the potential VSSG.
N-channel transistor N connected and grounded at the source
23 gates. When the external power supply voltage Vcc is high,
The bonding pad 16 is connected to another bonding pad.
Not in. The level of the voltage VEXTBG is N-channel transistor
Is turned to low level by turning on the
The high level output is inverted by the inverter and the N channel
The signal is input to the gate of the transistor N23. This allows
The N-channel transistor N23 turns on, and the voltage VSSG becomes
It becomes the same level as the ground voltage Vss, and the differential amplifier 10 operates.
I do. When the external power supply voltage Vcc is low,
The bonding pad 16 corresponds to the bonding pad 13 in FIG.
And 14 are short-circuited by the bonding wire,
A source voltage Vcc is supplied. Voltage VEXTBG goes to high level
And the low level output is inverted
It is supplied to the gate of the channel transistor N23 and turned off.
You. As a result, the N-channel transistor of the differential amplifier 10 in FIG.
The source of transistor N12 is no longer grounded and is inactive.
State. FIG. 5 shows the control circuit 12 of FIG.
Shows another modified example. External power supply voltage Vcc terminal and bondy
P-channel transistor P21 between
Is connected. The bonding pad 17 is
N channel transistor N22 and N channel transistor N2
4 is connected to the input terminal of the inverter consisting of
Output terminal outputs a potential VSSG. When the external power supply voltage Vcc is high, the circuit shown in FIG.
Bonding pad 17 is connected to other pads in the same way
It has not been. The voltage VEXTBG is turned on with the gate grounded
High level by the P-channel transistor P21
This voltage VEXTBG is inverted by the inverter
The low level output is output as the potential VSSG. this
As a result, the differential amplifier 10 in FIG. 1 operates. When the external power supply voltage Vcc is low,
Bonding pad 17 is connected to grounded bonding pad 15.
Short-circuited. As a result, the potential VEXTBG becomes low level.
Is inverted by the inverter and the high-level voltage VSSG
Is output. As a result, the differential amplifier 10 is in a non-operating state.
Be in a state. Next, a half according to the second embodiment of the present invention will be described.
The conductor device will be described. In this second embodiment,
Depending on the level of the external power supply voltage Vcc,
The feature is that the conduction resistance of the transistor is changed. The semiconductor device according to the second embodiment
The configuration is shown in FIG. This semiconductor device has a
Circuit 40 and circuits 20 and 30 having a similar configuration
And The reference potential generation circuit 40 supplies the reference potential Vref
Output. The circuit 20 has an external power supply voltage Vcc
Operates only when the voltage is lower than a predetermined value such as 3.3V.
Detection circuit 21, level shifter 22, differential amplification
Section 23, driving transistor section 24, P for resistance division
Channel transistor P41, resistors R21 and R22
Have. The circuit 30 is connected to the level of the external power supply voltage Vcc.
Regardless, it always operates, and the detection circuit 31 and the level shifter 3
2. Differential amplifier 33, P-channel transistor for driving
P47, P-channel transistor P48 for resistance division,
It has resistors R23 and R24. In the circuit 20, the detection circuit 21 is connected to an external power supply.
Detects the level of source voltage Vcc and outputs detection signal VCCMIN
I do. The level shifter 22 receives the detection signal VCCMIN.
To convert it to the desired level.
Transistors P31 and P32, N-channel transistor N3
1 and N32, P-channel transistor P33 and IN
It has a inverter IN11 and outputs voltages V21 to V23.
Power. The transistor section 24 has an external power supply voltage Vcc
Terminal and the internal power supply voltage Vint terminal are connected in parallel.
P-channel transistors P101 to P10n
(N is an integer of 2 or more). P channel tiger
The transistors P101 to P10n have a voltage V common to the gates.
21 and input the internal power supply voltage Vint from the drain.
Output. A P-channel transistor P41 and a resistor R2
1 and R22 are the internal power supply voltage Vint terminal and the voltage V2
3 is output to the output terminal of the inverter IN11.
They are connected in series. Where the P-channel transistor
P41 responds to the level of the voltage V23 input to the gate.
On / off control. And, the resistance R21 and the resistance
From the node connecting the anti-R22, the internal power supply voltage Vint
A voltage V24 obtained by dividing the voltage V23 by resistance is output. The differential amplifier 23 has a P-channel transistor
P34 and P35 and an N-channel transistor N33
-N36, a current mirror type differential amplifier circuit
You. The differential amplifier 23 operates by receiving the voltage V22.
The operation state is controlled, and the ratio between the reference voltage Vref and the voltage V24 is controlled.
The voltage V21 is compared and the voltage V21 is output.
The operation of the register section 24 is controlled. The circuit 30 is the same as the circuit 20 as described above.
It has a costly circuit configuration. However, the circuit 30 is
It always operates regardless of the level of the source voltage Vcc. others
The detection of the level of the external power supply voltage Vcc
It is not necessary to have the circuit 31 and the level shifter 32,
The differential amplifier 33 always operates, and the reference voltage Vref and the voltage V
31 and a P-channel transistor P4
7 can be used as long as it controls the switching. The operation of the present embodiment having such a configuration is as follows.
The work is as follows. First, the external power supply voltage Vcc
If the bell is low, for example, 3.3V, the circuit
20 and the circuit 30 operate together. In circuit 20, the detection
That the external power supply voltage Vcc is lower than a predetermined value
Is detected, and a control signal VCCMIN indicating this is output.
It is. The level shifter 22 supplies the control signal VCCMIN.
And outputs the voltages V21 to V23. Logical level and
Therefore, the voltages V21 and V23 are at the low level,
22 is a high level. The low-level voltage V is applied to the transistor section 24.
21 is input, and P-channel transistors P101 to P101
10n is turned on and the internal power supply voltage stepped down according to the conduction resistance
The pressure Vint is output. The difference between the voltage Vint and the voltage V23
The potential difference between the P-channel transistor P41 and the resistor R2
1 and R22, and a voltage V24 is output.
You. The differential amplifier 23 has a high level voltage V2
2 is input and it is operating. Reference voltage Vref and voltage
V24 is input and compared, and the voltage V24 is higher.
In the case, the high-level voltage V21 is output and the P-channel
The transistors P101 to P10n are turned off. This
As a result, the level of the internal power supply voltage Vint drops. Voltage V2
4 is lower than the reference voltage Vref.
Is output and the P-channel transistor P1
01 to P10n are turned on, and the internal power supply voltage Vint rises
You. Similarly, the detection circuit 31,
The level shifter 32 and the differential amplifier 33 operate. Detection
The circuit 31 detects the level of the external power supply voltage Vcc and sends a control signal.
The signal Vccmax is output. Here, the differential amplifier 33 is always
Control signal VCCMAX is always high
On the level. External power supply voltage Vcc and control signal VCCMAx
Is inverted by the inverter IN12 to output a low level signal.
Is different between the P-channel transistor P47 and the P-channel transistor.
Resistance with the flannel transistor P48 and resistors R23 and R24
It is divided and output as potential V31. This potential 31
And the reference potential Vref are input to the differential amplifier 33 and
And a P-channel transistor P4
7 is controlled. When the external power supply voltage Vcc is low, the circuit 2
0 P-channel transistors P101 to P10n and circuit
30 P-channel transistors P47 are both turned on,
It will be connected to the column. Therefore, the internal power supply voltage Vin
The size of the driving transistor that generates t increases.
Therefore, the voltage is hardly reduced from the external power supply voltage Vcc.
The internal power supply voltage Vint can be generated. In particular,
In the transistor section 24, a P-channel transistor P
By increasing the number of 101 to P10n,
The external power supply voltage can be
When the Vcc terminal and the internal power supply voltage Vint terminal are almost short-circuited
A state similar to the case can be obtained. The external power supply voltage Vcc is, for example, 5V.
If it is high, it is as follows. In the circuit 20,
The detection circuit 21 determines that the external power supply voltage Vcc is higher than a predetermined value.
Is detected. The control signal VCCMIN at this time is low level.
And the differential amplifier 23 has a low-level potential V22
Is given, and a non-operation state is set. P-channel transistor
The high-level potential V23 is input to the
Off. The output potential V21 from the differential amplifier 23 is high.
And P-channel transistors P101 to P10
n are all turned off. In one circuit 30, external power supply voltage Vcc is
It operates even when it is high, and the P-channel transistor P
47 outputs the internal power supply voltage Vint. like this
When the external power supply voltage Vcc is high,
Only the star P47 is turned on. Therefore, the internal power supply voltage V
Increase the conduction resistance of the driving transistor that outputs int
Can be set to reduce noise during switching.
Thus, the operation margin can be improved. As described above, in the second embodiment, the external
Outputs the internal power supply voltage Vint according to the level of the power supply voltage Vcc.
Changing the conduction resistance of the transistor to be activated. External power supply
When the voltage Vcc is low, the conduction resistance is reduced and the external power supply
Output the internal power supply voltage Vint approximately equal to the
When the voltage Vcc is high, the conduction resistance is increased to switch
To reduce noise at the time of operation and secure a high operation margin
Can be. FIG. 8 shows the inspection according to the second embodiment.
An example of a specific circuit of the knowledge circuit 21 will be described. External power supply voltage V
A P-channel transformer is connected between the cc terminal and the ground voltage Vss terminal.
Consists of a transistor P51 and an N-channel transistor N51
And the N-channel transistor N52
They are connected in series. The input terminal of this inverter
Is the reference potential Vref which is not affected by the external power supply voltage Vcc.
Input to the gate of the N-channel transistor N52.
A high-level signal V25 is input. This inverter
Is connected to the input terminal of the inverter IN13.
The output terminal of the inverter IN31 has a NAND circuit N
RS latch composed of A11 and NAND circuit 12
The set terminal of the circuit is connected. This latch circuit
The reset terminal has a low-level signal V26 during operation.
Is entered. The auxiliary output terminal of the latch circuit has an inverter
The terminal to which the control signal VCCMIN is output via IN14 is
It is connected. According to this detection circuit, the transistor P5
1, the control signal V according to the ratio of the resistances of N51 and N52.
CCMIN level switches. Next, the detection circuit according to the second embodiment
21 shows another example of the circuit. This circuit is a CMOS type
It uses a rent mirror circuit. External power supply voltage V
A P-channel transformer is connected between the cc terminal and the ground voltage Vss terminal.
A transistor P52, resistors R25 to R27, and an N-channel transistor
The transistor N53 is connected in series. Voltage Vcc-Vss
With a P-channel transistor P52 and a resistor R25,
Resistors R26 and R27 and N-channel transistor N53
The potential V27 obtained by dividing the resistances by the resistors R25 and R26
Emitted from the connecting node. P-channel transistors P54 and P55
And N-channel transistors N54 to N56 for differential amplification
The operation is based on the internal power supply voltage Vint terminal.
And the sources of P-channel transistors P54 and P55
Of P-channel transistor P53 connected between
Controlled by state. This P-channel transistor P
ON / OFF of 53 is gated via inverter IN15.
Is controlled by the voltage V25 supplied to. The difference between the potential V27 and the reference potential Vref is
The result is input to the amplifier, and the comparison result is output as the potential V28.
It is. This potential V28 is applied to the inverter trains IN16 and I16.
It is output as a control signal VCCMIN via N17. Ma
A gate is connected between the potential V28 and the ground voltage Vss terminal.
Is the N channel connected to the output terminal of the inverter IN15.
Transistor N57 is connected. The resistance R
26 and the resistor R27 and the ground voltage Vss terminal
Between the resistor R28 and the N-channel transistor N5.
6 are connected in series. This N-channel transistor
Is controlled by a control signal VCCMIN.
You. Even with the detection circuit having such a configuration, external
A voltage V27 obtained by dividing the power supply voltage Vcc by resistance and a reference
By comparing with the potential Vref, the external power supply voltage Vcc is increased.
It is possible to detect low. The detection circuit shown in FIG.
When the power supply voltage Vcc switches from high level to low level
And when switching from low level to high level
And has a so-called hysteresis characteristic.
As a result, manufacturing process conditions fluctuate, and external power
Assuming that the reference level for distinguishing the level of pressure Vcc is slightly shifted
Also, reliable operation is guaranteed. Next, a third embodiment of the present invention will be described.
explain. FIG. 10 shows a semiconductor device according to the present embodiment.
The configuration is shown. This device comprises a bit line pair voltage V41 and
Sense circuit 50 detects relative level of V42
And outputs the result from the output transistor.
Output transistor dimensions to external power supply voltage Vcc level
The feature is that it changes according to. The output transistor is a P-channel transistor.
Stars P61 and P62 and N-channel transistor N6
3 and N64. P-channel transistor
The external power supply P61 and the N-channel transistor N63
Connected in series between the voltage Vcc terminal and the ground voltage Vss terminal.
Have been. P-channel transistor P62 and N-channel
Transistor N64 has an N-channel transistor
Connected to the external power supply voltage Vcc terminal via the
It is connected in series with the ground voltage Vss terminal. P Cha
The gates of the flannel transistors P61 and P62
One output terminal of the circuit 50 is connected via an inverter IN21.
And N-channel transistors N63 and N64
Gate is connected to the other output terminal of the sense circuit 50.
Are connected via the data IN22. Also, N channel
The gates of the transistors N61 and N62
The output terminal of the path 51 is connected and the control signal VCCMIN
Controls its conduction. Output terminal of this semiconductor device
The child is a P-channel transistor P61 and an N-channel transistor.
Transistor N63, N-channel transistors N61 and N6
2 is commonly connected to a node connecting the two. The detection circuit 51 detects the external power supply voltage Vcc.
If the voltage is low and the voltage is low, the control signal VCCMIN is
High level. As a result, the P-channel transistor
Both the transistor P62 and the N-channel transistor N62 turn on.
You. Therefore, as an output transistor, a P-channel transistor
Transistors P61 and P62, N-channel transistor N
63 and N64 are all conducting and consequently conducting
Resistance decreases. Therefore, when the external power supply voltage Vcc is low,
In this case, the size of the final output transistor
As a result, the output level is prevented from lowering. Conversely, when the external power supply voltage Vcc is high,
The control signal VCCMIN goes low. N-channel tiger
Transistors N61 and N62 are turned off and the P-channel
Both the transistor P62 and the N-channel transistor N64 are off.
Off. Output transistor is a P-channel transistor
Only P61 and N-channel transistor N63
And the conduction resistance increases. This allows external power
Suppresses switching noise even when voltage Vcc is high
Can be A semiconductor device according to the fourth embodiment of the present invention
Will be described. This device is used in semiconductor storage devices.
Constant current driving common source node of sense amplifier
The step-down circuit has a configuration as shown in FIG.
is there. The sense amplifier circuit 64 is a P-channel transistor.
P-channel sense amplifiers 71 and 7 composed of transistors
2 and an N-channel composed of N-channel transistors
It has sense amplifiers 73 and 74. Each P
The channel sense amplifiers 71 and 72 are P-channel transistor
Is activated when the common source node SAP of the star is charged
N channel sense amplifiers 73 and 74
The common source node SAN of the flannel transistor is discharged
It is activated by being done. This common source node SAP, bar SAN
Is performed by the control circuit 63. This
The common source node of the P-channel sense amplifiers 71 and 72
The mode SAP is charged by the P-channel transistors P75 to P75.
P77 and N-channel transistors N76 and N77
This is performed by the configured circuit 63a. This circuit 63a includes an N-channel transistor
The reference potential VRSAP input to the gate of the
It operates based on a comparison with the source node SAP. Reference
The potential VRSAP is generated by the reference potential generating circuit 61.
Between the internal power supply voltage Vint terminal and the ground voltage Vss terminal,
Resistors R31 and R32, diode D1, N-channel
A transistor N71 is connected in series, and a resistor R31
And resistor R32, diode D1, N-channel transistor
The reference potential VRSAP is generated by resistance division by the
Is done. The level of the reference potential VRSAP is equal to the reference potential VRSAP.
The switching is performed according to the operation of the control circuit 62. Reference potential control
In the circuit 62, the internal power supply voltage Vint terminal and the voltage VRSAP terminal
P-channel transistors P71 and P72 are between
They are connected in series. P-channel transistor P72
Is turned on and off by the detection circuit 21 shown in FIG.
Control signal VCCMIN is inverted by inverter IN31.
Is controlled by the In addition, the control circuit 63
And the inverter IN32, the N-channel transistor N7
2 is supplied with the enable signal SE.
Corresponds to a second control circuit that outputs a first signal. When the external power supply voltage Vcc is low, the detection signal
VCCMIN is at a high level. This signal VCCMIN
Inverted by the inverter IN31 and the low level potential is
Is applied to the gate of the
You. Thereby, the P-channel transistors P71 and P71
72, the internal power supply voltage Vint terminal and the reference potential VRS
Short circuit with AP terminal. Thereby, the reference potential VRSAP
The level is substantially equal to the internal power supply voltage Vint, for example, 3.3.
V level. Such a reference potential VRSAP is
Into the gate of N-channel transistor N77 on path 63a.
Power, and the speed of charging the common source node SAP is high.
Become. Conversely, when the external power supply voltage Vcc is high, P
The channel transistor P72 turns off. Reference potential VRS
The AP terminal and the internal power supply voltage Vint terminal are not short-circuited.
The level of potential VRSAP is determined by circuit 61. this
The voltage VRSAP at this time is as low as 1.4 V, for example.
Is set. This reference potential VRSAP is the N channel of the circuit 63a.
Input to the gate of the transistor N77
The noise level generated at the time of tuning is reduced. As described above, when the external power supply voltage Vcc is low
The reference potential VRSAP is set to a high value, for example, 3.3 V.
Comb to increase the charging speed of the common source node SAP
This prevents delays in bit line restoration.
Wear. When the external power supply voltage Vcc is high,
The reference potential VRSAP is reduced to, for example, 1.4 V, and
By reducing the charge rate of the signal SAP, this signal line SAP
To suppress power supply noise during charging and prevent malfunctions
Can be. Next, the fifth to seventh embodiments of the present invention will be described.
A semiconductor device according to the present invention will be described. These embodiments
Are used to generate the reference potential Vref.
Switches the voltage according to the level of the external power supply voltage Vcc.
is there. This reference potential Vref is used for comparing the I / O input level.
Voltage and 1 / 2V of bit line in DRAM
Used for the cc precharge voltage generation circuit. FIG. 12 shows a fifth embodiment of the present invention.
And a control circuit 81, a reference potential generation circuit 82,
have. From the control circuit 81, the external power supply voltage Vcc
A control signal corresponding to the level of is output. This control signal
The external power supply voltage Vcc is supplied to the reference voltage generation circuit 82.
When the voltage is high, the reference potential Vref1 is output.
The reference voltage Vref2 is output. The sixth embodiment shown in FIG.
A reference potential generating circuit 84 for generating a reference potential Vref1,
And a reference potential generating circuit 85 for generating the potential Vref2.
Be prepared. Then, reference potential generating circuits 84 and 85
Is supplied to the switching circuit 86,
Either one is selected according to the control signal from the road 83
Output. FIG. 14 shows a seventh embodiment of the present invention.
It is shown. As in the sixth embodiment, the reference potential V
reference potential generating circuit 88 for generating ref1 and Vref2, respectively
And 89, respectively, from the control circuit 87.
The difference is that the operation state is controlled by applying a control signal.
You. When the external power supply voltage Vcc is high,
Only the reference potential generation circuit 88 operates to generate the reference potential Vref1.
Is generated, and the reference potential generating circuit 89 enters a non-operating state. Departure
The generated reference potential Vref1 is input to the switching circuit 90
Is output. If the external power supply voltage Vcc is low,
On the contrary, the reference potential generating circuit 88 becomes inactive,
The reference potential generation circuit 89 operates to generate the reference potential Vref2
Is done. This reference potential Vref2 is supplied to the switching circuit 90.
Input and output to outside. In this seventh embodiment
According to this, only one of the reference potential generating circuits operates.
Therefore, the current consumption is reduced as compared with the sixth embodiment.
Can be made. As described above, the reference potential Vref is set to the external power supply voltage.
When used at low voltage by changing according to Vcc
Is the lower reference potential and the higher reference voltage is the corresponding reference potential.
Position can be generated. FIGS. 15 to 17 show the eighth embodiment of the present invention, respectively.
10 shows a configuration of a semiconductor device according to the tenth to tenth embodiments.
These embodiments are based on the substrate potential VSSB1 or VSSB2.
Either one is output according to the level of the external power supply voltage Vcc.
And the above-described fifth to seventh block configurations
This is the same as that according to the embodiment. In the eighth embodiment shown in FIG. 15,
In response to a control signal from the control circuit 91, the substrate potential generation time
One of the substrate potentials VSSB1 and VSSB2 is output from the path 92.
Is forced. More specifically, VSSB2 is shallower than VSSB1.
(Close to ground potential) and Vcc is low
The control circuit 91 is configured to sometimes output VSSB2. In the ninth embodiment shown in FIG.
The bases respectively generated from the plate potential generating circuits 94 and 95
One of the plate potentials VSSB1 and VSSB2 is controlled by the control circuit 93.
Selected by the switching circuit 96 in accordance with the control of
Is forced. In the tenth embodiment shown in FIG.
Under the control of the control circuit 97, the reference potential generating circuits 98 and 9
9 operates and the reference potential VSSB1 or Vs
SSB2 is generated and output from the switching circuit 100.
You. With such a configuration, according to the power supply voltage,
The substrate potential can be changed. For example, when using at low voltage
When the substrate potential is set shallow (close to the ground potential), M
Back gate bias effect of OS transistor is suppressed
Thus, the threshold can be lowered. This results in low voltage
When used in MOS transistors, use MOS transistors with appropriate thresholds.
It can be used without malfunction. FIGS. 18 to 20 show the first embodiment of the present invention.
The configurations of the first to thirteenth embodiments are respectively shown. these
In the embodiment, the voltage is boosted according to the level of the external power supply voltage Vcc.
The voltage is output by changing the ratio. Each implementation
The block configuration in the form of the fifth to seventh, eighth to tenth
This is the same as each of the embodiments described above. Here it is boosted
Voltage power is boosted by the word line booster circuit of DRAM, for example.
Used as a power supply. The eleventh embodiment shown in FIG.
In response to a control signal from the control circuit 101, the booster circuit 10
2 outputs either the boosted voltage Vb1 or Vb2.
You. In the twelfth embodiment shown in FIG.
Is the boosted voltage V from the booster circuits 104 and 105, respectively.
b1 and Vb2 are generated and controlled by the control circuit 103
Either one is output from the switching circuit 106
You. In the thirteenth embodiment shown in FIG.
One of the booster circuits 108 and 109 is the control circuit 1
In the operation state under the control of 07, the boosted voltages Vb1, Vb2
Is output from the switching circuit 110.
You. As described above, the voltage rises according to the external power supply voltage Vcc.
The voltage-voltage ratio can be changed. External power supply voltage Vcc is low
In the case of a voltage, by increasing the boosted voltage ratio, for example, D
The voltage applied to the word line of the RAM increases,
Transistor in the cell
You. This prevents malfunctions and shortens the access time.
Contracted. Here, in the fifth to thirteenth embodiments,
Control circuits according to the level of the external power supply voltage Vcc.
Control signal. For example, inside the control circuit
The operator, depending on the level of the external power supply voltage Vcc.
The fuse is blown or not blown,
A control signal can be generated. These specific times
The road configuration is the same as that shown in FIGS. Ma
In addition, it has a bonding pad and has a high external power supply voltage Vcc.
The gap between the bonding pads may vary depending on the operator.
Control signal depending on whether the
May be generated. These specific circuit configurations are shown in FIG.
It is equivalent to that shown in FIG. Or, for example,
Such as a MOS transistor having a
Built-in volatile memory cell, high and low external power supply voltage Vcc
May be written in advance. further,
Built-in circuit to detect the level of external power supply voltage Vcc, automatic
To generate a control signal corresponding to the level.
You may. In addition, the control in the fifth to thirteenth embodiments
As described above, the control circuit includes, for example, the first embodiment and
The control circuit 12 shown in FIG.
Can be applied. There
Is a circuit according to the second embodiment shown in FIGS.
A similar configuration may be used. According to the fifth to thirteenth embodiments of the present invention,
In any of the embodiments, one semiconductor device
It can be used for different external power supply voltages Vcc.
For this reason, a high-voltage device and a low-voltage device
It does not need to be manufactured exclusively. This translates into manufacturing costs
Not only reduce
It is possible to supply a corresponding device. Further, in general, a lower voltage is used than a high voltage used.
When used, the operating margin is smaller and
Good and easy. Equipment determined to be defective at low voltage is also high.
Voltage can be used in many cases.
Improve production yield compared to manufacturing as equipment
Can be The above embodiments are merely examples.
It is not intended to limit the invention. For example, as described above
In the embodiment, the external power supply voltage is, for example, 5V or 3.3V.
So, assuming that it corresponds to two types of voltage
However, the present invention is also applicable to the case where three or more voltages are used.
Can be used. In this case, for example,
When the pressure level is the lowest, the
So that the dimensions of the
Should be set to. As described above, the semiconductor device of the present invention
Is used to generate the reference voltage, substrate voltage, and boosted voltage.
Switching the level according to the level of the power supply voltage
This prevents malfunctions in circuits using these voltages.
Can be stopped. Also, for different external power supply voltage
Can be handled by the same semiconductor device.
Can be sorted according to market requirements.
You. In addition, manufactured devices are not
Good, but can be used at high external power supply voltage
Often, manufacture equipment dedicated to low external power supply voltage
Thus, the production yield can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing another circuit configuration of a control circuit in the semiconductor device. FIG. 3 is a circuit diagram showing another circuit configuration of the control circuit in the semiconductor device. FIG. 4 is a circuit diagram showing another circuit configuration of the control circuit in the semiconductor device. FIG. 5 is a circuit diagram showing another circuit configuration of the control circuit in the semiconductor device. FIG. 6 is an explanatory diagram showing a change in a standby current with respect to an external power supply voltage. FIG. 7 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 8 is a circuit diagram showing another circuit configuration of the detection circuit in the semiconductor device. FIG. 9 is a circuit diagram showing another circuit configuration of the detection circuit in the semiconductor device. FIG. 10 is a circuit diagram showing a configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 11 is a circuit diagram showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. FIG. 12 is a circuit diagram showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. FIG. 13 is a circuit diagram showing a configuration of a semiconductor device according to a sixth embodiment of the present invention. FIG. 14 is a circuit diagram illustrating a configuration of a semiconductor device according to a seventh embodiment; FIG. 15 is a circuit diagram showing a configuration of a semiconductor device according to an eighth embodiment of the present invention. FIG. 16 is a circuit diagram showing a configuration of a semiconductor device according to a ninth embodiment of the present invention. FIG. 17 is a circuit diagram showing a configuration of a semiconductor device according to a tenth embodiment of the present invention. FIG. 18 is a circuit diagram showing a configuration of a semiconductor device according to an eleventh embodiment of the present invention. FIG. 19 is a circuit diagram showing a configuration of a semiconductor device according to a twelfth embodiment of the present invention. FIG. 20 is a circuit diagram showing a configuration of a semiconductor device according to a thirteenth embodiment of the present invention. FIG. 21 is a circuit diagram illustrating a configuration of a conventional semiconductor device. FIG. 22 is a circuit diagram showing a configuration of a reference potential generation circuit in the semiconductor device. FIG. 23 is an explanatory diagram showing changes in a reference potential and an internal power supply voltage with respect to an external power supply voltage in the semiconductor device. [Description of Signs] 10 Differential amplifying sections 11, 40, 61, 82, 84, 85, 88, 89 Reference potential generating circuits 12, 63, 81, 83, 87, 91, 93, 97, 1
01, 103, 107 Control circuits 13 to 17 Bonding pads 21, 51 Detecting circuit 22, 32 Level shifter 23, 33 Differential amplifier 24 Transistor 50 Sense circuit 62 Reference potential control circuit 64 Sense amplifier circuit 86, 90, 96, 100 , 106, 110 Switching circuits 92, 94, 95, 98, 99 Substrate potential generating circuits 102, 104, 105, 108, 109 Boosting circuits F1, F2 Fuse

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masaru Koyanagi 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Pref. Toshiba Corporation Semiconductor System Technology Center (56) References A) JP-A-2-71491 (JP, A) JP-A-60-45997 (JP, A) JP-A-3-173465 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) G11C 11/407

Claims (1)

(57) Claims 1. A control input terminal connected to a bonding pad, discharging means for discharging the control input terminal, and a series connection between the control input terminal and the control output terminal. A first control signal is output from the control output terminal when the bonding pad is not connected to the power supply voltage terminal, and the bonding pad is connected to the control terminal without being connected to the power supply voltage terminal. A control circuit for outputting a second control signal from the control output terminal when a power supply voltage is not supplied and the discharging means discharges the first control signal; A first reference voltage generation circuit that outputs a reference voltage; a second reference voltage generation circuit that outputs a second reference voltage when the control circuit outputs the second control signal; The first and second reference voltage generating circuits are connected and controlled by one of the first and second control signals. When the control circuit outputs the first control signal, the first A semiconductor circuit, comprising: a switch circuit for receiving and outputting a reference voltage, and when the control circuit outputs the second control signal, for receiving and outputting the second reference voltage. .