JP3415516B2 - PLL circuit and semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control circuit for a semiconductor integrated circuit, and more particularly to a circuit for automatically correcting a phase error of a phase comparator of a PLL circuit.

[0002]

2. Description of the Related Art A PLL (Phase Locked Loop) circuit is used as one of clock synchronization circuits for synchronizing the phases of an externally supplied clock and an internal clock. FIG. 3 is a diagram schematically showing the configuration of a conventional PLL circuit provided in a semiconductor integrated circuit. Referring to FIG. 3, a PLL circuit 30 inside each LSI
2 is a clock from the outside of the LSI 301 and the LSI 301
Internal Clock Tree Synth
esis (hereinafter abbreviated as "CTS") synchronizes clock phases of flip-flops 313 to 315, etc., which are connected to each other, thereby realizing clock synchronization between a plurality of LSIs arranged on a board (not shown) Has been done.

Flip-flop 315 in LSI 301
The phase comparator 30 of the PLL circuit 302 determines whether or not the phase of the internal clock supplied to the clock input terminal FFCLK and the phase of the clock outside the LSI 301 are synchronized.
In step 3, the phase of the external clock is compared with that of the internal clock, and the internal clock output from the voltage controlled oscillator (VCO) is fed back to the phase comparator 303 via a loop filter provided in the subsequent stage of the phase comparator 303. By inputting, the phase synchronization operation is performed.

By the way, in order to make an accurate judgment of the phase comparison, the PLL 302 passes through two paths to the phase comparator 303, that is, the external input terminal RCLK of the LSI 301 and the interface (I / F) buffer 304.
Of the reference clock that reaches the first input terminal of the phase comparator 303 in the internal circuit and the delay time of the path 2 of the feedback clock from the input terminal CLKI of the PLL 302 to the second input terminal of the phase comparator 303 of the PLL 302. It is premised that they are the same, and when the PLL circuit is designed, matching is performed so that they are the same.

[0005]

[Problems to be Solved by the Invention]
Since the delay values of the two paths 1 and 2 are adjusted when the PLL is designed, the delays of the paths 1 and 2 may deviate from the same value due to manufacturing variations in mass production of LSI.

Further, when the LSI is designed at the chip level, the delay value from the outside of the LSI 301 to the phase comparator 303 may vary depending on the wiring condition of the LSI 301.

At present, no measures are taken to correct the deviation in the delay value due to the manufacturing variation of each LSI and the wiring condition inside the LSI in the input path of the phase comparator of the PLL. It's a reality. For this reason,
It is also a cause of malfunctions and failures of electrical equipment.

As a conventional technique of a PLL circuit, for example, Japanese Patent Application Laid-Open No. 10-093429 proposes a circuit configuration for controlling a delay circuit in the PLL to reduce a phase error when an internal clock and an external clock match. ing. FIG. 4 is a diagram showing a configuration of a PLL circuit described in Japanese Patent Laid-Open No. 10-093429. Referring to FIG. 4, the external clock CLKSYS becomes the internal clock CLKB via the delay circuit 21 and the clock buffer 22, and the phase comparator 23 detects the phase difference between the two clocks. The counter 24 changes the count value based on the comparison result of the phase comparator 23, and the least significant bit of the count value controls ON / OFF of the transmission gates 27-0 and 27-1 to determine the least significant bit of the count value. The other bits are input to the decoder 25, and the output of the decoder 25 controls ON / OFF of the transmission gates 26-0 to 26- (N-1).

Comparing the configuration shown in FIG. 4 with the circuit configuration shown in FIG. 3, the external terminal CLKSYS to the phase comparator 23 corresponds to the path 1, and the terminal CLKI to the phase comparator 23 corresponds to the path 2. Equivalent to. No measures are taken for the route 1 and the route 2 to correct the deviation in the delay value due to the manufacturing variation of each LSI and the wiring condition inside the LSI.

In order to match the delay values of these two paths at the time of PLL design, enormous energy is required to secure simulation resources, which leads to an increase in design cost.

Further, for example, in Japanese Patent Laid-Open No. 2-105910, there is provided a plurality of clock adjusting means for forming clocks that match each other based on frequency information and phase information supplied from a clock generating source, and the clock adjusting means comprises: A comparison clock (RE with phase information from the clock source
F) and the feedback signal (FB) for detecting the phase difference, and a clock (MC) according to the phase difference.
A configuration including a variable delay unit that delays K) is disclosed. In this Japanese Patent Laid-Open No. 2-105910, the comparison clock (REF) input to the phase comparison means is also used.
No consideration is given to the adjustment of the delay time between the signal and the feedback signal (FB).

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to improve the accuracy of phase synchronization of the PLL and to achieve phase comparison accuracy due to manufacturing variations and wiring conditions inside the LSI. It is an object of the present invention to provide a PLL circuit and a semiconductor integrated circuit device including the PLL circuit, which suppresses the deterioration of

[0013]

According to the present invention for achieving the above object, a first path from a reference clock input terminal to a first input terminal of a phase comparator of a PLL circuit and an output from the PLL circuit are provided. The PL for feedback input of the clock
First and second variable delay elements whose delay times are variably settable are respectively inserted in the second paths from the input end of the L circuit to the second input end of the phase comparator, The delay time of the first and second variable delay elements based on the measurement result of the delay time difference between the third and fourth paths for delay time measurement including the paths equivalent to the first and second paths, respectively. The phase error automatic correction means for setting the delay times of the first path and the second path to be equal to each other is provided.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described. The present invention, in one of its preferred embodiments,
PL with the reference clock input from the external terminal as the input
In a semiconductor integrated circuit device for generating an internal clock with an L circuit, a first terminal from the external terminal for inputting the reference clock to a first input terminal of a phase comparator of the PLL circuit.
And a second path from the input end of the PLL circuit for inputting the clock output from the PLL circuit as a feedback clock (feedback signal) to the second input end of the phase comparator. Delay times in third and fourth paths for delay time measurement, in which first and second variable delay elements whose time can be variably set are inserted, and paths equivalent to the first and second paths are included The phase error automatic correction means for setting the delay times of the first and second variable delay elements and equalizing the delay times of the first and second paths on the basis of the measurement result of the difference. The phase error automatic correction means includes a multiplied clock generator that generates a clock obtained by multiplying the reference clock input from the external terminal, and a delay time of the third path by the multiplied clock output from the multiplied clock generator. And a counter that counts the difference between the delay times of the fourth path, and sets the delay times of the first and second variable delay elements based on the count value of the counter. The delay times of the two paths are made equal.

In one embodiment of the present invention, in the first path, the reference clock input terminal is an interface buffer, and a first comparator of the phase comparator of the PLL circuit via the first variable delay element. The input terminal of the PLL circuit, which is connected to the first input terminal of the PLL circuit and is used to feed back the clock output from the PLL circuit in the second path, via the second variable delay element. Is connected to a second input terminal of the frequency converter, and the third path outputs the clock output from the multiplied clock generator to the outside of the semiconductor integrated circuit device from the first delay element and the first interface buffer. The output transmission path and the output clock are folded back and taken into the inside of the semiconductor integrated circuit device through the second interface buffer, and then the second delay buffer is provided. Through element consists feedback path to be input to the multiplication clock generator, the fourth path, the clock output from the multiplied clock generator, the third
And a feedback path which is routed to the end of the PLL circuit via the delay element and is turned back at the end and is input to the multiplied clock generator via the fourth delay element. And a clock output from the multiplied clock generator to the fourth path, and based on the time difference between the clocks returned to the return paths of the third path and the fourth path, the third and fourth The difference in the delay time of the path of is measured by the counter, based on the count value of the counter,
The delay times of the first and second variable delay elements are set.

In one embodiment of the present invention, the phase error automatic correction means, based on the measurement result of the delay time of the first path and the second path at power-on or reset, A correction process for equalizing the delay times of the first and second paths is performed.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. The present invention suppresses deterioration of phase comparison accuracy due to manufacturing variations and wiring conditions inside an LSI.

Referring to FIG. 1, when the power of the LSI 101 is turned on or the reset is executed, the clock multiplied by the multiplied clock generator 105 in the PLL 102
Two paths to the phase comparator 103, namely LSI1
02 external input terminal RCLK to I / F buffer 112
Path 1 of the reference clock reaching the phase comparator 103 in the PLL 102 through the input terminal CLK of the PLL 102
Path 2 of feedback clock from I to phase comparator 103
The difference in the delay time between the path 3 and the path 4 corresponding to the difference in the delay value is measured by counting with the counter 104 of the PLL 102. Are controlled so that the delay values of the path 1 and the path 2 are the same.

The LSI 101 includes interface buffers 112, 113, 114, a PLL 102, and a CTS (clock tree synthesis) buffer 120 including buffer groups 121 to 127 arranged and wired in a tree shape for equalizing clock delays. And flip flips 128, 129, 130. PLL102
Is a first comparator inserted between the phase comparator 103 for inputting the reference clock from the terminal RCLK and the internal clock from the terminal CLKI, and the interface buffer 112, and the first comparator inserted between the terminal CLKI and the input terminal of the phase comparator 103.
Second variable delay elements 106 and 107, and a multiplied clock generator 1 that receives a reference clock and generates a multiplied clock.
05, the counter 104, and the first to fourth delay elements 10
8 to 111 are provided. A low-pass filter that receives the output of the phase comparator in the PLL circuit and a voltage-controlled oscillator (VCO) that inputs the output voltage of the low-pass filter as a control voltage and outputs an internal clock are not shown.

The path 1 is the reference clock input terminal RCLK.
From I / F buffer 112, first variable delay element 106
Is a path of the reference clock to the first input end of the phase comparator 103, and the path 2 passes from the input terminal CLKI of the PLL 102 through the second variable delay element 107 to the second input of the phase comparator 103. This is the path of the feedback clock to the end.

The path 3 is folded back from the multiplied clock generator 105 to the input terminal of the I / F buffer 114 via the first delay element 108 and the output terminal of the I / F buffer 113, and the second delay element 109. Is a path for returning to the multiplied clock generator 105 again.

The path 4 is a path from the multiplied clock generator 105 to the end of the PLL 102 through the third delay element 110, and again to the multiplied clock 105 via the fourth delay element 111.

The delay values of the paths 3 and 4 are respectively counted by the counter 104 by the multiplied clock of the multiplied clock generator 105, and the delays of the first and second variable delay elements 106 and 107 are based on the counted values. Control the time.

The operation of the embodiment of the present invention will be described.

When the power of the LSI 101 is turned on or the reset is executed, a multiplied clock is generated from the multiplied clock generator 105 using the reference clock input from the external input terminal RCLK of the LSI 101 as an input, and the delay value of the clocks of the paths 3 and 4 is generated. Is measured by the counter 104, and the first and second variable delay elements 106 and 10 are measured according to the measurement result.
The delay amount of 7 is controlled so that the delay values of route 1 and route 2 are the same.

In measuring the delay times of the paths 3 and 4, the delay element 10 of the path 3 is fed from the multiplied clock generator 105.
8 and the clock pulse is simultaneously output to the delay circuit 110 on the path 4, and the counter 1 outputs the clock pulse when the clock pulse is fed back from the delay circuit 111 on the path 4, for example.
04 is started, and when the clock pulse is fed back from the delay circuit 109 on the path 3, the counter 104 is stopped. The delay amount of the path 3 and the path 4 is set as the count value of the counter 104. It is assumed that the route 4 has a smaller delay time than the route 3.

The delay times of the first and second delay elements 108 and 109 and the third and fourth delay elements 110 and 111 are equalized, and the delay characteristics of the I / F buffers 113 and 114 are I.
When the counter value is equal to that of the / F buffer 112, the count value of the counter 104 is equivalent to the difference between the delay times of the paths 3 and 4 being twice the difference between the delay times of the paths 1 and 2.

Therefore, is the delay time of the second variable delay element 107 set larger than the delay time of the first variable delay element 106 by a delay amount corresponding to ½ of the count value of the counter 104? , The delay time of the first variable delay element 106 is set smaller than the delay time of the second variable delay element 107 by a delay amount corresponding to ½ of the count value of the counter 104. Even if the manufacturing time and the wiring condition inside the LSI change, the phase comparison can always be performed with high accuracy.

The first and second variable delay elements 106,
Reference numeral 107 denotes, for example, a P-channel MOS transistor group connected in parallel between the source of the P-channel MOS transistor forming the CMOS inverter and the high potential power source, and CM.
An inverter including an N-channel MOS transistor source forming an OS inverter and an N-channel MOS transistor group connected in parallel between low-potential power supplies is provided as a unit delay circuit, and a gate of the N-channel MOS transistor group and a P-channel MOS transistor are provided. In the gate of the transistor group,
The delay amount may be variably set by connecting the count output of the counter 104 and its inverted signal to change the current driving capability.

FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. 2, in the second embodiment of the present invention, unlike the embodiment shown in FIG. 1, the counter 104A is configured as a counter to which an initial value is loaded, and the initial value is The terminal 115 for setting is provided.

By changing the initial value of the counter 104 from the terminal 115, the path 1 between the reference clock terminal RCLK of the LSI 101 and the input terminal of the phase comparator 102 is changed.
An arbitrary delay time difference (phase difference) can be provided between the path 2 and the path 2.

[0032]

As described above, according to the present invention,
The following effects are achieved.

The first effect of the present invention is that the phase synchronization accuracy of the PLL can be improved.

The reason is that in the present invention, the delay value of the two paths whose phases are compared by the phase comparator in the PLL is automatically corrected.

According to the present invention, it is possible to always perform highly accurate phase comparison even if manufacturing variations or wiring conditions inside the LSI change.

The second effect of the present invention is that the stability of the circuit operation of the LSI is improved because the accuracy of the phase synchronization by the PLL is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a diagram showing an example of a conventional circuit configuration.

FIG. 4 is a diagram showing another example of a conventional circuit configuration.

[Explanation of symbols]

21, 29 Delay element 22 Buffer 24 Up-down counter 25 Decoder 26, 27 Transfer gate 101, 201, 301 LSI 102 PLL 23, 103, 302 Phase comparator 104 Counter 105 Communication clock generator 106, 107 Variable delay element 108, 109 , 110, 111 Delay elements 112, 113, 114, 212, 304 Interface buffer 120 CTS buffers 121-127, 306-312 Buffers 128-130, 313-315 Flip-flops

Claims (10)

(57) [Claims] 1. A first path from a reference clock input terminal to a first input terminal of a phase comparator of a PLL circuit, and the PL.
The clock output from the L circuit is input as a feedback clock to the second path from the input end of the PLL circuit to the second input end of the phase comparator, and the delay time can be set variably. The first and second variable delay elements, and based on the measurement result of the difference in delay time in the third and fourth paths for delay time measurement including paths equivalent to the first and second paths, respectively, A PLL circuit comprising: a phase error automatic correction means for setting the delay times of the first and second variable delay elements and making the delay times of the first path and the second path equal to each other. . 2. The phase error automatic correction means uses the multiplied clock generator for generating a clock obtained by multiplying the input reference clock, and the multiplied clock output from the multiplied clock generator to provide the third path. A counter for counting the difference in delay time of the fourth path; and setting the delay times of the first and second variable delay elements based on the count value of the counter,
PLL circuit according to claim 1 wherein the path between, characterized in that equal the delay time of the second path. 3. In the first path, the reference clock input from the reference clock input terminal passes through an interface buffer and the first variable delay element, and a first input of a phase comparator of the PLL circuit. The feedback clock input to the end of the PLL circuit is input from the input end of the PLL circuit via the second variable delay element to the second input end of the phase comparator of the PLL circuit. The third path is folded back to the input terminal after the clock output from the multiplied clock generator is output from the output terminal through the first delay element and the first interface buffer. Is input to the multiplied clock generator via a second interface buffer and a second delay element, and the fourth path is A path in which the clock output from the multiplied clock generator is sent to the area end of the PLL circuit via the third delay element, folded back, and fed back to the multiplied clock generator via the fourth delay element. From the multiplied clock generator to the third path and the fourth path
The difference in the delay time until the clock sent to the path of (3) returns to the multiplied clock generator is measured by the counter, and the first and second
3. The PLL circuit according to claim 2 , wherein the delay time of the variable delay element is set. 4. When the power is turned on or when the power is reset, the phase error automatic correction means determines the first path and the second path based on the measurement results of the delay times of the third path and the fourth path. Perform adjustment processing to equalize the delay time of the route,
The PLL circuit according to any one of claims 1 to 3 , wherein: 5. The PLL circuit according to claim 2, wherein the initial value of the counter can be set externally. 6. A semiconductor integrated circuit device comprising a PLL circuit for generating and outputting an internal clock from a reference clock inputted from an external terminal, wherein the PL is inputted from the external terminal to which the reference clock is inputted.
From a first path to a first input terminal of the phase comparator of the L circuit and from an input terminal of the PLL circuit for inputting an internal clock as a feedback clock to an internal circuit of the semiconductor integrated circuit supplied from the PLL circuit. First and second variable delay elements whose delay times are variably settable are respectively inserted in the second paths to the second input terminal of the phase comparator, and the first and second paths are connected. The delay times of the first and second variable delay elements are set on the basis of the measurement results of the delay time differences in the third and fourth paths for delay time measurement each including an equivalent path, and the first and second variable delay elements are set. A semiconductor integrated circuit device comprising a phase error automatic correction means for equalizing the delay times of a path and the second path. 7. The phase error automatic correction means uses a multiplied clock generator for generating a clock obtained by multiplying the reference clock input from the external terminal, and the multiplied clock output from the multiplied clock generator. A counter that counts the difference between the delay time of the third path and the delay time of the fourth path, and sets the delay times of the first and second variable delay elements based on the count value of the counter. 7. The semiconductor integrated circuit device according to claim 6 , wherein the delay times of the first path and the second path are made equal to each other. 8. In the first path, the reference clock input from the reference clock input terminal is passed through an interface buffer and the first variable delay element to a first phase comparator of the phase comparator of the PLL circuit. The feedback clock input to the input end and input from the input end of the PLL circuit in the second path is input to the second input end of the phase comparator via the second variable delay element. And a sending path for outputting the clock output from the multiplied clock generator to the outside of the semiconductor integrated circuit device via the first delay element and the first interface buffer. , The output clock is returned to the semiconductor integrated circuit device via the second interface buffer as it is, and then the second delay element is used. And a feedback path input to the multiplied clock generator, and the fourth path sends the clock output from the multiplied clock generator to an end of the PLL circuit via a third delay element. It comprises a sending path and a feedback path for returning the clock sent to the end portion to the multiplied clock generator via a fourth delay element, and from the multiplied clock generator to the third path and the fourth path.
The difference in the delay time until the clock sent to the path is returned to the multiplied clock generator is measured by the counter, and the delay times of the first and second variable delay elements are set based on the count value of the counter. 8. The semiconductor integrated circuit device according to claim 7 , wherein: 9. The phase error automatic correction means, when the power is turned on or reset, based on the measurement result of the delay time of the third path and the fourth path, the first path and the second path. Performs correction processing to equalize the delay times of the routes,
The semiconductor integrated circuit device according to any one of claims 6 to 8, characterized in that. Claim 10. The initial value of the counter is freely set from the external terminal, and wherein the 7 or 8
The semiconductor integrated circuit device according to 1.