JP3409845B2 - Variable length bit string processing apparatus and variable length bit string processing method using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a variable length coding process in a processor such as MPU (microprocessor) or DSP (digital signal processor).
A variable length for storing the encoded variable-length codeword as a bitstream in a register or the like, or for extracting a variable-length codeword from the bitstream stored in the register or the like during variable-length decoding processing in a processor. The present invention relates to a bit string processing device and a variable length bit string processing method using the same, and more particularly to a variable length bit string processing device having a small hardware scale and a variable length bit string processing method using the same.

[0002]

2. Description of the Related Art Image signals and audio signals to be subjected to digital signal processing are coded into a plurality of code words and are further transmitted in a form in which the plurality of code words are connected (hereinafter referred to as a bit stream). It is done and accumulated.

When performing simple encoding and decoding processing for image signals and audio signals used in a system whose specifications are not changed in the future, hardware for exclusively performing the encoding and decoding processing is provided. Has been.

However, in recent years, MPs have been adopted so that encoding and decoding processes for data such as image signals and audio signals can be quickly adapted to complicated control and system specification changes.
There is a demand for a technique realized by software of a processor such as U or DSP.

Here, the encoding and decoding processes performed on the software of the processor such as MPU and DSP will be described.

In the encoding process for the image signal and audio signal data, the encoded image signal and audio signal data is converted into a code word by referring to a preset table. This codeword is then inserted into the bitstream being created on the register.

On the other hand, in the decoding process for a codeword, the codeword to be decoded is extracted from the bitstream stored in the register, and the extracted codeword (or a bit string including this codeword) is used as an address. The data of the image signal and the audio signal is reproduced with reference to the above table.

It should be noted that the bitstream contains a mixture of fixed-length codewords and variable-length codewords, and when the variable-length codeword is decoded by referring to a table, the decoded variable It is possible to reproduce the data of the image signal and the audio signal corresponding to the long codeword and at the same time obtain the bit string length of the variable length codeword.

Therefore, when the variable length code word is decoded by referring to the table, the variable length coded from the bit stream is decoded next based on the bit string length of the variable length code word decoded immediately before. Extract the codeword.

However, at the time of the variable length coding process, the coded variable length code word is inserted into the bitstream being created on the register, or at the time of the decoding process, the variable length code is changed from the bitstream stored in the register. When the process of extracting a word is implemented by software of a processor such as MPU or DSP, the efficiency of the variable length encoding and variable length decoding processes may be deteriorated.

Therefore, particularly when a variable length code word is inserted into a bit stream having a high bit rate or a variable length code word included in a bit stream having a high bit rate is extracted, these variable length code words are extracted. In many cases, a variable-length bit string processing device is provided for exclusive use in bit-string processing, and the variable-length bit string processing device is used to perform variable-length bit string processing.

The conventional variable length bit string processing device is realized as a dedicated hardware provided with a plurality of shifters, and its technique is disclosed in, for example, Japanese Unexamined Patent Publication No. 5-250139.

FIG. 9 is a block diagram showing an example of the configuration of a conventional variable length bit string processing device. In FIG. 9, the shift amount input 904 and the input bit string 905 are input from the outside.

As shown in FIG. 9, in this conventional example, a 32-bit buffer 901, a 32-bit shifter 902 that shifts an input bit string 905 based on a shift amount input 904, and outputs the shift result, and a buffer 901. And the shift result output from the shifter 902 are connected,
This concatenation result is shifted based on the shift amount input 904, and this shift result is output as an extracted bit string 906 and is composed of a 32-bit shifter 903.

The bit string 90 extracted from the shifter 903.
When 6 is output, the contents of the buffer 901 are changed to the shifter 9
03 is updated to the content of the extracted bit string 906.

In the variable length bit string processing device having the above-mentioned configuration, the shifter 902 shifts the input bit string 905 based on the shift amount input 904,
This shift result is output, the contents of the bit string buffer 901 and the shift result output from the shifter 902 are concatenated in the shifter 903, and the concatenation result is further shifted based on the shift amount input 904. The extracted bit string 906 is output.

A variable length bit string extraction process performed by using the conventional variable length bit string processing device shown in FIG. 9 on software of a processor such as MPU or DSP will be described below.

In the normal variable length bit string extraction processing, this variable length codeword is stored in a predetermined register so that the leading bit of the extracted variable length codeword matches the most significant bit in a predetermined register. To be done.

FIG. 10 is a diagram for explaining a variable length bit string extraction process using the conventional variable length bit string processing device shown in FIG. Here, the code word A is stored in the register 1004 so that the first bit of the code word A stored in the buffer 901 matches the most significant bit of the register 1004.
The variable-length bit string extraction processing for storing in the following will be described.

In FIG. 10, the buffer 901
Is a variable-length decoded codeword 1003a that has already been decoded and is extracted as a table reference address.
Then, it is assumed that the codeword 1003b consisting of the variable-length codeword A to be decoded next and a part of the variable-length codeword B is stored as a bit stream of 32 bits in total.

The shift amount register 1002 is assumed to store a bit string 1002a having the same bit string length as the bit string length LEN bits of the decoded codeword 1003a stored in the buffer 901. The bit string length of the bit string 1002a is based on the bit string length obtained when the decoded codeword 1003a is subjected to the decoding process by referring to the table.

Further, it is assumed that the external input buffer 1001 stores a codeword 1001a following the content of the codeword 1003b stored in the buffer 901. The codeword 1001a has a bit string length of 100
3a is the same as the bit string length LEN bits, and the code word B
And a codeword C.

First, the content of the external input buffer 1001 is input to the shifter 902 as an input bit string 905, and the content of the shift amount register 1002 is input to the shift amount 9
04 is input to the shifter 902 and the shifter 903.

Then, in the shifter 902, the external input buffer 1001 input as the input bit string 905 is input.
Of the bit string 100 based on the shift amount input 904.
The bit string length of 2a is shifted to the left, and the shift result is output to the shifter 903.

As a result, the codeword 1001a stored in the external input buffer 1001 is stored in the external input buffer 1001.
The codeword 1001a that has been swept out from 1 is input to the shifter 903.

Here, the contents of the buffer 901 are transferred to the shifter 9
Enter in 03.

Then, in the shifter 903, the code word 1001a swept from the external input buffer 1001 is concatenated from the least significant bit side of the contents of the buffer 901,
Further, the concatenation result is shifted to the left by the bit string length of the bit string 1002a based on the contents of the shift amount register 1002. The shift result is output to the outside of the device as a 32-bit extracted bit string 906, and then the content of the extracted bit string 906 output to the outside of the device is stored in the register 1004.

As a result, the first bit of the code word A is stored in the register 1004 in a state where it matches the most significant bit in the register 1004, and the code word A and the bit string for the table reference address used for decoding the code word A are stored. The extraction is complete.

After that, the contents of the buffer 901 are updated to the contents of the register 1004 in preparation for the next variable length bit string extraction processing.

[0030]

However, in the conventional variable-length bit string processing apparatus as described above, a plurality of shifters and internal buffers are provided, which increases the hardware scale. There is a point.

The present invention has been made in view of the problems of the above-mentioned conventional techniques, and a variable length bit string processing apparatus and a variable length bit string processing device capable of efficiently executing variable length bit string processing with a small hardware scale. An object is to provide a variable length bit string processing method using this.

[0032]

In order to achieve the above object, the present invention provides a variable length variable length codeword variable length codeword insertion process or variable length codeword insertion process or variable length codeword decoding process in a processor. In the bit string processor,
Is input first input bit string and the shift amount signal, an input bit sequence of the first shifted based on the shift amount signal, a shift means for outputting the shift result, the second input bit string is input, the Processing content in the processor
Selecting means for selecting either the second input bit string or the bit string of the lower half of the shift result output from the shift means based on the above, and outputting the selection result,
And a concatenation unit that concatenates the upper half bit string of the shift result output from the shift unit and the selection result output from the selection unit, and outputs the concatenation result as an output bit string.

[0033]

Further, the shift means is a barrel shifter.

Further, the selection means is a multiplexer.

A variable-length bit string processing method using the variable-length bit string processing device is characterized in that the processing in the connecting means is performed by the processor.

Further, by the processor, the first
Of the input bit string, the second input bit string, and the shift amount signal are preset and input to the variable length bit string processing device.

(Operation) In the present invention configured as described above, the selection means for switching the bit string to be selected based on the processing content in the processor is used as the selecting means for switching the bit string of the lower half of the shift result of the first input bit string and the second bit string. Input bit string of the first input bit string and the bit string selected by the selection means of both bit strings and the upper half bit string of the shift result of the first input bit string are connected by the connection means. Of the output bit string that is shifted based on the shift amount signal, or the output bit string in which the lower half bit string of the shift result obtained by shifting the first input bit string based on the shift amount signal is replaced with the second input bit string. Either of them will be output from the variable length bit string processing device.

Therefore, various variable length bit string processing can be performed by presetting the first input bit string, the second input bit string and the shift amount signal on the software of the processor and inputting them to the variable length bit string processing device. Next to
As a result, normal shift processing, variable-length bit string extraction processing, and variable-length bit string insertion processing are efficiently executed.

Further, in the case where the processor performs the processing in the connecting means, since the present variable length bit string processing device is constituted only by the shifting means and the selecting means, the hardware scale is reduced.

In the case where the shift means is a barrel shifter, when the variable length bit string processor is mounted on the processor equipped with the barrel shifter, the barrel shifter can be shared by the processor and the variable length bit string processor. .

As a result, when the variable length bit string processor is mounted on the processor equipped with the barrel shifter, the variable length bit string processor is connected to the barrel shifter mounted on the processor by one selecting means. As a result, the scale of hardware is significantly reduced.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a variable length bit string processing device of the present invention. Note that in FIG. 1, the shifted signal (A
[31: 0]) 105, shift amount signal 106, and 16-bit inserted signal (C [15: 0]) 10 that is the second input bit string.
It is assumed that 7 is input from the outside. Where (A [31: 1
6]} sign is bit 31 to bit 1 in signal A
6 shows a bit string up to 6, and the symbols {B [31:16], D [15: 0]} indicate that the signal D [1 is from the least significant bit side of the signal B [31:16].
5: 0] is a concatenated signal.

In the present embodiment, as shown in FIG. 1, the 32-bit shifted signal (A [31: 0]) 105 is changed to the shift amount signal 106.
The shift result (B [31: 0]) output from the shifter 101 and the 32-bit shifter 101 that outputs the shift result as a 32-bit shift result (B [31: 0]) 108. 108 is divided into a high-order 16-bit signal and a low-order 16-bit signal, and the respective divided signals are divided into a high-order 16-bit signal (B [31:16]) 109 and a low-order 16-bit signal (B [15: 0]). ) 110 as the distribution means 102 and the lower 16 output from the distribution means 102
Either the bit signal (B [15: 0]) 110 or the 16-bit inserted signal (C [15: 0]) 107 input from the outside is selected, and the selection result (D [15: 0]) 111
Multiplexer 103 for outputting as and distribution means 10
Upper 16-bit signal (B [31:16]) 1 output from 2
09 and the selection result (D [15: 0]) 111 output from the multiplexer 103 are connected, and the connection result is used as a 32-bit output bit string (B [31:16], D [15: 0]) 112. It is composed of a connecting means 104 for outputting to the outside of the device.

The shifter 101 is a normal 32-bit barrel shifter mounted on a processor such as MPU or DSP, and can perform arithmetic right shift, logical right shift, logical left shift and the like.

The distributing means 102 and the connecting means 104
Each of them simply divides or merges the signal line. For this reason, in practice, there is no dedicated hardware for the distribution means 102 and the connection means 104, and the shunting or merging processing of the signal lines is performed by the software of the processor such as MPU or DSP.

The operation of the variable length bit string processing device configured as described above will be described below.

In this embodiment, a shift operation mode in which the shifted signal 105 is shifted based on the shift amount signal 106 (arithmetic right shift, logical right shift and logical left shift).
And a bit string insertion operation mode in which the shifted signal 105 is shifted based on the shift amount signal 106, and the lower 16 bits of the shift result 108 are replaced with the inserted signal 107. The action is taken. Note that these operation modes are determined by the instruction type from the processor such as MPU or DSP.

First, the shift operation will be described with reference to FIG.

FIG. 2 is a diagram for explaining a shift operation in the variable length bit string processing device shown in FIG. In FIG. 2, signal lines selected during the shift operation are indicated by solid lines, and signal lines not selected during the shift operation are indicated by broken lines.

First, the 32-bit shifted signal (A [31:
0]) 105 and shift amount signal 106 are input to shifter 101, and 16-bit inserted signal 107 is input to multiplexer 103.

Next, in the shifter 101, the shifted signal (A [31: 0]) 105 is shifted based on the shift amount signal 106, and this shift result is a 32-bit shift result (B [31: 0]). ) 108 is output.

Next, in the distributing means 102, the shifter 1
The shift result (B [31: 0]) 108 output from 01 is distributed to the upper 16 bits and the lower 16 bits, and each of the distributed signals is the upper 16-bit signal (B [31:16]) 1
09 and the lower 16-bit signal (B [15: 0]) 110 are output.

Next, in the multiplexer 103, the lower 16-bit signal (B [1
5: 0]) 110 and the inserted signal 107 input from the outside
Of the two types of signals, the lower 16-bit signal (B [15: 0]) 110 output from the distribution means 102 is selected, and the selected lower 16-bit signal (B [15: 0]) 110 is selected. The result (B [15: 0]) 111 is output.

Next, in the connecting means 104, the selection result (B [15: 0]) 11 output from the multiplexer 103
1 is concatenated from the least significant bit side of the upper 16-bit signal (B [31:16]) 109 output from the distribution means 102,
This concatenation result is a 32-bit output bit string (B [31:16], B
[15: 0]) 112 is output.

As described above, in the shift operation mode, the output bit string (B
The contents of [31:16], B [15: 0]) 112 and the contents of the shift result (B [31: 0]) 108 output from the shifter 101 are the same. As a result, the content input as the shifted signal 105 is shifted based on the shift amount signal 106,
This shift result is output as an output bit string 112 to the outside of the variable length bit string processing device.

Since the inserted signal 107 does not affect the output bit string 112, any signal may be used as the inserted signal 107.

Next, the bit string inserting operation will be described with reference to FIG.

FIG. 3 is a diagram for explaining a bit string insertion operation in the variable length bit string processing device shown in FIG. In FIG. 3, signal lines selected during the bit string insertion operation are shown by solid lines, and other signal lines are shown by broken lines.

First, the 32-bit shifted signal (A [31:
0]) 105 and the shift amount signal 106 are input to the shifter 101, and the inserted signal (C [15: 0]) 107 is input to the multiplexer 103.

Next, in the shifter 101, the shifted signal (A [31: 0]) 105 is shifted based on the shift amount signal 106, and this shift result is a 32-bit shift result (B [31: 0]). It is output as 108.

Next, in the distributing means 102, the shifter 1
The shift result (B [31: 0]) 108 output from 01 is distributed to the upper 16-bit signal and the lower 16-bit signal, and each of the distributed signals is the upper 16-bit signal (B [31:16] ] 109 and lower 16-bit signal (B [15:
0]) 110 is output.

Next, in the multiplexer 103, the lower 16-bit signal (B [1
5: 0]) 110 and the signal to be inserted (C [1
5: 0]) 107, the inserted signal (C [15: 0]) 107 input from the outside is selected, and the selected inserted signal (C [15: 0]) 107 is selected. Is the selection result (C [15: 0])
It is output as 111.

Next, in the connecting means 104, the selection result (C [15: 0]) 11 output from the multiplexer 103 is output.
1 is concatenated from the least significant bit side of the upper 16-bit signal (B [31:16]) 109 output from the distribution means 102,
This concatenation result is a 32-bit output bit string (B [31: 0], C
[15: 0]) 112 is output to the outside of the device.

As described above, in the bit string insertion operation mode, the content input as the shifted signal 105 is shifted based on the shift amount signal 106, and the least significant bit of the upper 16-bit signal of the shift result is further shifted. The inserted signal 107 is concatenated from the side, and the concatenation result is output as an output bit string 112 to the outside of the variable length bit string processing device.

The variable length bit string processing performed by using the variable length bit string processing device of the present invention on the software of the processor such as MPU or DSP will be described below.

Here, as the variable length bit string processing, M
When a processor such as PU or DSP performs variable-length coding processing, a variable that inserts the coded variable-length codeword and the bit string for table reference address of this variable-length codeword into the bitstream being created on the register When the long bit string insertion process and the variable length decoding process are performed by the processor,
The variable length bit string extraction processing for extracting the variable length code word and the table reference address bit string of the variable length code word from the bit stream stored in the register will be described.

In the following description, as a register used for variable-length bit string processing, 3 registers installed in the processor are used.
A 2-bit general-purpose register is used, and the shifted signal 105 and the shift amount signal 106 are output from these general-purpose registers.
The inserted signal 107 and the inserted signal 107 are input into the variable length bit string extraction processing device, and the contents of the output bit string 112 output from the variable length bit string extraction processing device are stored in these general-purpose registers.

First, the variable length bit string extraction processing will be described with reference to FIG.

FIG. 4 is a diagram for explaining a variable length bit string extraction process using the variable length bit string processing circuit shown in FIG. Here, a variable length bit string extraction process of storing the code word 401c in the register 403 so that the leading bit of the code word 401c stored in the register 401 matches the most significant bit in the register 403 will be described.

In FIG. 4, the register 401
Is assumed to store a bitstream 401a including variable-length decoded codewords 401b and variable-length codewords 401c and 401d that have already been decoded and extracted as table reference addresses.

Further, the register 402 stores the bit string 402a having the same bit string length as the bit string length LEN bits of the decoded code word 401b obtained at the same time when the decoded code word 401b is decoded. And

In this state, the registers 401 and 40
The contents of 2 are input to the variable length bit string processing device as the shifted signal 105 and the shift amount signal 106, respectively,
The shift operation of the variable length bit string processing device is executed.

Then, in this variable length bit string processing device, the register 40 input as the shifted signal 105 is input.
The content of 1 is the bit string length 4 based on the shift amount signal 106.
It is shifted to the left by 02a, and the shift result is output to the outside of the device as an output bit string 112.

Next, the contents of the output bit string 112 output from this variable length bit string processing device are stored in the register 403.

As a result, the first bit of the code word 401c is stored in the register 403 in a state where the leading bit of the code word 401c matches the most significant bit of the register 403, and the code word 401c and the bit string for the table reference address used for the decoding process of the code word 401c are stored. The extraction is complete.

After that, the contents of the register 401 are updated to the contents of the register 403, and the bit string stored in the register 402 is updated to a bit string having the same bit string length as the code word 401c to extract the next variable length bit string. Prepare for processing.

In the above-described variable length bit string extraction processing, the bit stream 401a stored in the register 401 is gradually swept out to the left, so that finally all bit streams are swept out and stored in the register 401. There is a problem of running out of bitstream.

In the conventional variable length bit string processing device shown in FIG. 9, such a problem is caused because the code word is replenished from the outside of the device to the internal buffer every time the code word is extracted from the internal buffer. Does not happen.

Therefore, in the present invention, when the bit stream in the register which supplies the shifted signal becomes 16 bits or less when the variable length bit string extraction processing is performed next, the shifted signal is supplied. A register is newly supplemented with a 16-bit bit stream from another register, and then variable length bit string extraction processing is performed.

As a result, the bit stream of 16 bits or more is constantly stored in the register supplying the shifted signal, and the problem that the bit stream in this register is exhausted is avoided.

In the following description, FIG. 4 shows the variable length bit string extraction processing performed after a bit stream in a register supplying a shifted signal is newly supplemented with a 16-bit bit stream from another register. In order to distinguish from the illustrated variable length bit string extraction process, it is particularly referred to as a variable length bit string extraction process with bit stream supplementation.

A variable length bit string extraction process involving bit stream supplementation using the variable length bit string processing circuit shown in FIG. 1 will be described below with reference to FIG.

FIG. 5 is a diagram for explaining a variable length bit string extraction process involving bit stream supplementation using the variable length bit string processing circuit shown in FIG. Here, a variable-length bit string extraction process of storing the codeword 501c in the register 506 so that the leading bit of the codeword 501c stored in the register 501 matches the most significant bit in the register 506 will be described.

In FIG. 5, the register 501
Is assumed to store a bitstream 501a composed of variable-length decoded codewords 501b and variable-length codewords 501c and 501d that have already been decoded and extracted as table reference addresses. When the long bit string extraction processing is performed and the decoded codeword 501b is swept out, the bit stream 501a is in a state of 16 bits or less.

In order to avoid such a state, first, by deleting a part of the decoded codeword 501b stored in the register 501, the lower 1 in the register 501 is deleted.
With all 6 bits zeroed and the lower 16 bits in register 501 all zeros, register 50
A process of inserting the bit stream 503a stored in the register 503 into the lower 16 bits of 1 is performed.

Here, the contents of the registers 501 to 503 are changed to the shifted signal 105 and the shift amount signal 106, respectively.
And the signal 107 to be inserted into the variable length bit string processing device, and the bit string inserting operation of the variable length bit string processing device is executed.

The register 502 is the register 501.
It is assumed that the bit string 502a having the same bit string length as the bit string length LA bits of the bit stream remaining in the lower 16 bits of is stored. Register 502
The bit string 502a stored in is used to determine whether to newly supplement 16 bits, and the calculation method will be described later.

Further, the register 503 is the register 501.
It is assumed that the bitstream 503a following the contents of the bitstream 501a stored in the above is stored.

Then, in this variable length bit string processor, the register 50 input as the shifted signal 105 is input.
The content of 1 is shifted to the left by the bit string length 502a based on the shift amount signal 106. As a result, a part of the decoded codeword 501b stored in the register 501 is deleted as an intermediate result, and the lower 16 bits in the register 501 are all zero. Subsequently, the contents of the register 503 input as the inserted signal 107 are connected to the lower 16 bits that have become all zeros, and the connection result is output as an output bit string 112 to the outside of the device.

Next, the contents of the output bit string 112 output from this variable length bit string processing device are temporarily stored in the register 504.

As a result, the upper 16 bits of the register 504 stores the bitstream 501a in which a part of the decoded codeword 501b of the bitstream 501a stored in the register 501 is deleted,
In the lower 16 bits in register 504, register 5
The bit stream 503a stored in 03 is inserted.

At this time, the bitstream 501a stored in the register 504 contains the decoded codeword 501b.
Some of the remains.

Therefore, in order to sweep out the decoded codeword 501b remaining in the register 504, from the bit string length LEN bits of the decoded codeword 501b to the bit string 502.
By subtracting the bit string length of a, the bit string length LB bits of the decoded codeword 501b remaining in the register 504 is calculated, and the bit string 505a having the same bit string length as the calculated bit string length LB bits is registered in the register 50.
Store in 5.

Since the lower 16 bits in the register 504 are supplemented with the bit stream 503a, the bit string 502a stored in the register 502 is stored.
The bit string length of is updated to "16".

Here, the contents of the registers 504 and 505 are changed to the shifted signal 105 and the shift amount signal 10, respectively.
The value 6 is input again to the variable length bit string processor, and the shift operation of the variable length bit string processor is executed.

Then, in this variable length bit string processing device, the register 50 input as the shifted signal 105 is input.
4 is a bit string 5 based on the shift amount signal 106.
The bit string length of 05a is shifted to the left, and the shift result is output as an output bit string 112 to the outside of the device.

Next, the contents of the output bit string 112 output from the present variable length bit string processing device are stored in the register 506.

As a result, the first bit of the code word 501c is stored in the register 506 in a state where the leading bit of the code word 501c matches the most significant bit of the register 506, and the code word 501c and the bit string for the table reference address used in the decoding process of the code word 501c are stored. The extraction is complete.

After that, when the decoding process of the codeword 501c stored in the register 506 is performed by referring to the table, the data in which the codeword 501c is decoded is obtained and at the same time, the bit string length of the codeword 501c is obtained. It will be.

Here, a new bit string length LA bit is calculated by subtracting the bit string length of the codeword 501c from the bit string length of the bit string 502a (16 bits at this point) stored in the register 502, and the calculated bit string A bit string having the same bit string length as the long LA bits is stored in the register 502 as a new bit string 502a, and the contents of the register 501 are stored in the register 506.
Update to the contents of. This prepares for the next bit string extraction.

In the present invention, when performing the variable length bit string extraction process, which of the variable length bit string extraction processes shown in FIGS. 4 and 5 is to be executed is as follows. It is determined.

Of the bit stream 501a stored in the register 501, the lower 16 bits in the register 501
Bit stream length LA of bit stream remaining in bits
Bit string length LEN of decoded codeword 501b
The DIFF is calculated by subtracting the bits, and when the calculated DIFF is positive, the variable length bit string extraction processing shown in FIG. 4 is performed, and when the DIFF is zero or negative, the DIFF is calculated as shown in FIG. The variable-length bit string extraction processing with the bit stream supplementation shown in is performed.

Next, the variable length bit string insertion processing will be described with reference to FIG.

FIG. 6 is a diagram for explaining a variable length bit string insertion process using the variable length bit string processing circuit shown in FIG. Here, a variable length bit string insertion process of inserting the codeword 603a stored in the register 603 into the bitstream 601a stored in the register 601 will be described.

In FIG. 6, the register 601 is used.
Is assumed to store variable-length code words 601d, 601b, 601c. It is assumed that, of these code words, a bit stream 601a including a part of the code word 601b and the code word 601c is being created.

Further, the register 602 has a code word 601c.
It is assumed that a bit string 602a having the same bit string length as the bit string length LEN bit of is stored. In addition,
The bit string length LEN bits of the code word 601c is set to the code word 6 when the code word 601c is encoded by the table reference.
This is the value of the bit string length obtained at the same time as 01c.

Further, the register 603 is the register 601.
It is assumed that the variable-length codeword 603a to be newly inserted in the bitstream 601a being created above is stored in a state in which the first bit of the codeword 603a matches the most significant bit of the lower 16 bits in the register 603. .

As described above, when variable length coding processing is performed, data such as an audio signal or an image signal is usually converted into a variable length code word by referring to a table.
In a table having a 16-bit fixed-length memory area as a table element, the first bit of the variable-length codeword is 1 in the table.
The variable-length codeword is stored so that it matches the most significant bit in the 6-bit area.

By storing the variable-length codeword in the table as described above, when the variable-length codeword encoded by the table reference is stored in the lower 16 bits of the register 603, the stored variable-length codeword is stored. The leading bit of the register 603 matches the most significant bit of the lower 16 bits of the register 603.

Here, the contents of the registers 601 to 603 are changed to the shifted signal 105 and the shift amount signal 106, respectively.
And the signal 107 to be inserted into the variable length bit string processing device, and the bit string inserting operation of the variable length bit string processing device is executed.

Then, in this variable length bit string processor, the register 60 input as the shifted signal 105
The content of 1 is the bit string 60 based on the shift amount signal 106.
The bit string length of 2a is shifted to the left, and the shift result is output as an output bit string 112 to the outside of the device.
As a result, the lower 16 bits in the register 601 are all zero as an intermediate result. Subsequently, the contents of the register 503 input as the inserted signal 107 are connected to the lower 16 bits that have become all zeros, and the connection result is output as an output bit string 112 to the outside of the device.

Next, the contents of the output bit string 112 output from this variable length bit string processing device are stored in the register 604.

Next, the contents of the register 601 are changed to the register 6
The contents of 04 are updated to prepare for the next bit string insertion processing.

As a result, the code word 603a is inserted into the bit stream 601a being created by the register 601.

In the variable length bit string insertion processing described above, the bit stream being created by the register 601 is gradually swept to the left without being saved in the memory, so a certain amount of bit stream is accumulated in the register 601. In that case, it is necessary to save the accumulated bitstream in the memory.

Therefore, in the present invention, the bit stream being created is managed in units of 16 bits, and when 16 bits of the bit stream are accumulated, this bit stream is saved in the memory and then the variable length bit string is inserted. Perform processing.

In the following description, in order to distinguish the variable-length bit string insertion processing shown in FIG. 6 from the variable-length bit string insertion processing performed after saving the bit stream in the register that supplies the shifted signal to the memory. In particular, it is called a variable-length bit string extraction process involving saving of a bit stream.

A variable length bit string insertion process involving saving of a bit stream using the variable length bit string processing device shown in FIG. 1 will be described below with reference to FIG.

FIG. 7 is a diagram for explaining a variable length bit string insertion process involving saving of a bit stream using the variable length bit string processing device shown in FIG. Here, in the bit stream 701a being created by the register 701,
A variable length bit string insertion process for inserting the codeword 705a stored in the register 705 will be described.

In FIG. 7, the register 701 is used.
Is a variable-length codeword 701e, 701b, 701c, 7
01d is stored, and a bitstream 701a composed of the codewords 701b, 701c, and 701d among these codewords is being created and is not saved in the memory.

When the codeword 705a stored in the register 705 is inserted into the bitstream 701a being created by the register 701, a part of the bitstream 701a not saved in the memory is swept out from the register 701. It is in a state of closing.

In order to avoid such a state, first, of the bitstream 701a, the bitstream 701a is not swept out in the memory so that the bitstream 701a is not swept out.
A process of saving a 16-bit bit stream in a memory (not shown) is performed.

Here, the contents of the registers 701 and 702 are changed to the shifted signal 105 and the shift amount signal 10, respectively.
The value 6 is input to the variable length bit string processor, and the shift operation of the variable length bit string processor is executed.

The register 702 is the register 701.
It is assumed that a bit string 702a having the same bit string length as the bit string length LA bits of the codeword 701e stored in the above is stored. A detailed description of the method of calculating the bit string length LA bits of the code word 701e will be given later.

Then, in this variable length bit string processor, the register 70 input as the shifted signal 105 is input.
The contents of 1 are bit strings 70 based on the shift amount signal 106.
The bit string length of 2a is shifted to the left, and the shift result is output as an output bit string 112 to the outside of the device.

Next, the contents of the output bit string 112 output from this variable length bit string processing device are temporarily stored in the register 703.

As a result, the bit stream 701 that is being created on the register 701 and is not saved in the memory.
The contents of a are stored in the register 703 in a state where the leading bit of the bitstream 701a matches the most significant bit in the register 703.

Here, of the bitstream 701a being created on the register 703, the upper 16-bit bitstream is saved in the memory.

Next, the bit string length LB bits of the code word remaining in the lower 16 bits in the register 703 of the code word 701d stored in the register 703 is calculated, and the same bit string as the calculated bit string length LB bit is calculated. The bit string 704a having the length is stored in the register 704. This bit string length LB bit is calculated by subtracting the bit string length of the bit string 702a stored in the register 702 from the bit string length LEN bit of the code word 701d.

Since the upper 16 bits in the register 703 are saved in the memory, the bit string length of the bit string 702a stored in the register 702 is updated to "16".

Here, the contents of the registers 703 to 705 are changed to the shifted signal 105 and the shift amount signal 106, respectively.
And the signal 107 to be inserted is input again to the variable length bit string processing device, and the bit string inserting operation of the variable length bit string processing device is executed.

The register 705 corresponds to the register 701.
It is assumed that the codeword 705a to be inserted into the bitstream 701a being created above is stored so that the leading bit of the codeword 705a matches the most significant bit in the lower 16 bits of the register 705.

Then, in this variable length bit string processor, the register 70 input as the shifted signal 105 is input.
3 of the bit string 7 based on the shift amount signal 106.
The bit string length of 04a is shifted to the left. Thereby, as an intermediate result, the lower 16 bits in the register 703 are
All bits are zero. Then, the contents of the register 705 input as the inserted signal 107 are connected to the lower 16 bits that have become all zeros, and the connection result is output as an output bit string 112 to the outside of the device.

Next, the contents of the output bit string 112 output from this variable length bit string processing device are stored in the register 706.

Next, the contents of the register 701 are changed to the register 7
The bit string 704a stored in the register 704 is updated from the bit string length of the bit string 702a stored in the register 702 (16 bits at this point).
By reducing the bit string length of
A bit is calculated, and a bit string having the same bit string length as the calculated bit string length LA bit is newly stored in the register 702 to prepare for the next variable length bit string insertion process. The bit string length LA bit shown in FIG. 6 is updated to a value obtained by subtracting the bit string length LEN bit from the bit string length LA bit at the previous variable length bit string insertion processing.

As a result, the codeword 705a stored in the register 705 is inserted into the bitstream 701a being created in the register 701.

In the present invention, when performing the variable length bit string insertion process, which of the variable length bit string insertion processes shown in FIGS. 6 and 7 is to be executed is as follows. It is determined.

DIFF is obtained by subtracting the bit string length LEN bit of the code word remaining in the lower 16 bits in the register 701 from the bit string length LA bit of the code word already saved in the memory among the code words stored in the register 701. Is calculated, and if the calculated DIFF is positive, the variable length bit string insertion processing shown in FIG.
If DIFF is zero or negative, the variable-length bit string insertion process with the bitstream saving shown in FIG. 7 is performed.

In the present invention, the execution time of the variable length bit string extraction process performed at the time of the variable length decoding process is increased as compared with the conventional variable length bit string processing device shown in FIG. Since the buffer and has been reduced,
The amount of hardware can be reduced.

The execution time required for the variable length bit string insertion processing performed at the time of the variable length coding processing is the same as that of the present embodiment when the variable length bit string processing device of the present invention and the conventional variable length bit string processing are executed. It is almost the same as the device.

Next, in order to explain the effect of the variable-length bit string processing apparatus of the present invention, variable-length bit string processing which is performed without using the variable-length bit string processing apparatus of the present invention on software of a processor such as MPU or DSP. Will be described.

FIG. 8 is a diagram for explaining the variable length bit string processing performed on the software of the processor without using the variable length bit string processing device shown in FIG.
Here, a process of inserting the bitstream 804a stored in the register 804 into the content of the register 801 will be described. The variable-length bit string processing shown in FIG. 8 corresponds to the variable-length bit string insertion processing shown in FIG.

In FIG. 8, variable length bit string processing is performed using the barrel shifter 811, the OR gate 812 and the registers 801 to 805 mounted on the processor.

The register 801 is assumed to store the bit stream 801a being created. In addition,
Bitstream 801a being created by register 801
Among these, the bit string length of the bit stream stored in the lower 16 bits in the register 801 is LEN bits.

The register 802 is assumed to store a bit string 802a having the same bit string length as the LEN bit.

In the register 804, the upper 16 bits are all zero, and the lower 16 bits are set in the register 801.
It is assumed that the bitstream 804a to be newly inserted is stored in the bitstream 801a being created above.

In this state, the registers 801 and 80
The contents of 2 are input to the barrel shifter 811, and the shift operation in the barrel shifter 811 is executed.

Then, in the barrel shifter 811, the contents of the register 801 are shifted to the left by the bit string length of the bit string 802a based on the contents of the register 802,
The result of this shift is output.

Next, the contents of the shift result output from the barrel shifter 811 are stored in the register 803. At this time, the lower 16 bits in the register 803 are all zero.

Next, the contents of the registers 803 and 804 are set to O.
It is input to the R gate 812, and the logical sum (OR) operation in the OR gate 812 is executed.

Then, in the OR gate 812, the logical sum operation of the contents of the register 803 and the contents of the register 804 is performed, whereby the logical sum operation result is output.

Next, the contents of the logical sum operation result output from the OR gate 812 are stored in the register 806.

After that, the contents of the register 801 are updated to the contents of the register 805 to prepare for the next bit string insertion processing.

As a result, the bitstream 804a stored in the register 804 has been inserted into the bitstream 801a being created by the register 801.

As described above, when the variable length bit string processing is performed without using the variable length bit string processing device of the present invention, the variable length bit string processing device of the present invention is used to execute the variable length bit string processing. One cycle (one cycle / instruction execution) of instruction execution is additionally required as compared with the case of performing variable length bit string processing.

[0158]

As described above, in the present invention,
A selection unit that switches a bit string to be selected based on the processing content of the processor, and a connection unit that connects the bit string selected by the selection unit and the upper half bit string of the shift result of the first input bit string are provided. Since the selection means selects either the lower half bit string of the shift result of the 1 input bit string or the second bit string, the output bit string in which the first input bit string is shifted based on the shift amount signal Alternatively, one of the output bit strings in which the lower half bit string of the shift result obtained by shifting the first input bit string based on the shift amount signal is replaced with the second input bit string is output from the variable length bit string processing device. Will be.

As a result, various variable length bit string processing can be performed by presetting the first input bit string, the second input bit string and the shift amount signal on the software of the processor and inputting them to the variable length bit string processing device. Therefore, the normal shift processing, variable-length bit string extraction processing, and variable-length bit string insertion processing can be efficiently executed.

When the processor performs the processing in the connecting means, the variable length bit string processing device is constituted only by the shift means and the selecting means, so that the hardware scale can be reduced.

When the shift means is a barrel shifter, the processor and the variable length bit string processing device can share the barrel shifter when the variable length bit string processing device is mounted on the processor equipped with the barrel shifter.

Accordingly, when the variable length bit string processing device is mounted on the processor equipped with the barrel shifter, the variable length bit string processing device is connected by connecting one selecting means to the barrel shifter mounted on the processor. Since this is realized, the hardware scale can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a variable length bit string processing device of the present invention.

FIG. 2 is a diagram for explaining a shift operation in the variable length bit string processing circuit shown in FIG.

FIG. 3 is a diagram for explaining a bit string insertion operation in the variable length bit string processing circuit shown in FIG.

FIG. 4 is a diagram for explaining a variable length bit string extraction process using the variable length bit string processing circuit shown in FIG. 1.

5 is a diagram for explaining a variable length bit string extraction process involving bit stream supplementation using the variable length bit string processing circuit shown in FIG. 1;

FIG. 6 is a diagram for explaining variable-length bit string insertion processing using the variable-length bit string processing circuit shown in FIG. 1.

FIG. 7 is a diagram for explaining variable-length bit string insertion processing involving bitstream saving using the variable-length bit string processing device shown in FIG. 1;

8 is a diagram for explaining variable length bit string processing performed on software of a processor without using the variable length bit string processing device shown in FIG. 1. FIG.

FIG. 9 is a block diagram showing a configuration example of a conventional variable length bit string processing device.

10 is a diagram for explaining a variable length bit string extraction process using the conventional variable length bit string processing device shown in FIG.

[Explanation of symbols] 101 shifter 102 distribution means 103 multiplexer 104 Connection means 105 Shifted signal 106 shift amount signal 107 Inserted signal 108 shift result 109 upper 16-bit signal 110 lower 16-bit signal 111 selection result 112 output bit string

Claims (5)

(57) [Claims] 1. A variable-length bit string processing device for performing variable-length codeword insertion processing or extraction processing during variable-length coding or variable-length decoding processing in a processor, wherein a first input bit string and shift amount signal are Shift means for inputting and shifting the first input bit string based on the shift amount signal and outputting the shift result; and a second input bit string for inputting to the processor.
That processing content selects one of the input bit string or the bit string of the lower half of the shift result output from said shift means the second on the basis of a selection means for outputting the selection result outputted from said shift means A variable length bit string processing device comprising: a concatenation unit that concatenates the upper half bit string of the shifted result and the selection result output from the selecting unit and outputs the concatenation result as an output bit string. 2. The variable length bit string processing device according to claim 1 , wherein the shift means is a barrel shifter. 3. The variable length bit string processing device according to claim 1 , wherein the selection unit is a multiplexer. 4. A variable-length bit string processing method using a variable length bit string processing apparatus according to any one of claims 1 to 3, by the processor, and characterized by performing the process in the connecting means Variable length bit string processing method. 5. The variable length bit string processing method according to claim 4 , wherein the processor presets the first input bit string, the second input bit string, and the shift amount signal. A variable-length bit string processing method characterized by inputting to a device.