JP3408342B2 - Sampling rate converter - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention resamples data sampled using a clock pulse having a first sampling frequency using a clock pulse having a second sampling frequency different from the first sampling frequency. The present invention relates to a sampling rate conversion device.

[0002]

BACKGROUND OF THE INVENTION Data sampled using a clock pulse having a first sampling frequency is
When resampling using a clock pulse having a second sampling frequency different from the sampling frequency of, it is necessary that each sampling time point does not coincide with the data switching portion. In order to prevent each sampling time from matching the data switching portion, it is necessary to make the first sampling frequency and the second sampling frequency a simple integer ratio and to establish the phase relationship.

However, when the frequency ratio between the first sampling frequency and the second sampling frequency is not a simple integer ratio and the phase relationship is not fixed, the clock pulse of the first sampling frequency is Since the clock pulse of the second sampling frequency gradually shifts in phase, the data switching time and the rising timing of the lock pulse of the second sampling frequency may almost coincide with each other. May occur.

An RS flip-flop may be used in the sampling rate converter, but when a pulse signal having a short width is input to the RS flip-flop, oscillation may occur.

[0005]

DISCLOSURE OF THE INVENTION According to the present invention, the frequency ratio between the first sampling frequency and the second sampling frequency is not a simple integer ratio, and the phase relationship between the first sampling frequency and the second sampling frequency is fixed. An object of the present invention is to provide a sampling rate conversion device capable of converting a sampling frequency from a first sampling frequency to a second sampling frequency without causing racing even if the sampling rate conversion is not performed.

According to a first aspect of the invention, the phase of the first data is obtained by sampling the first clock pulse having the first sampling frequency to obtain individual data. Has a second sampling frequency different from the first sampling frequency and a first switching timing at which individual data in the first data changes Sampling timing in the second clock pulse is substantially the same, or the second switching timing at which the individual data of the second data changes and the sampling timing in the second clock pulse are substantially the same. Timing coincidence detection means for generating and outputting a timing coincidence detection signal indicating that And the timing coincidence detection signal output from the timing coincidence detection means is input, and the timing coincidence detection signal is substantially coincident with the first switching timing and the sampling timing of the second clock pulse. The second data is sampled using the second clock pulse, and the timing coincidence detection signal indicates that the second switching timing and the second clock.
The second clock if the sampling timings of the pulses are almost the same.
In a sampling rate conversion device equipped with resampling means for sampling the first data by using pulses, the timing coincidence detection signal output from the timing coincidence detection means and the frequency of the first clock pulse It is characterized by comprising a delay circuit for inputting a clock pulse having a frequency twice and for delaying and outputting the input timing coincidence detection signal for a half cycle of the input clock pulse.

The phase of the first data is shifted by the half cycle of the first clock pulse to generate the second data. Further, the timing coincidence detection signal is generated.
This timing coincidence detection signal is the first clock
It is delayed by a half cycle of a clock pulse having a frequency twice the frequency of the pulse and applied to the resampling means. When the timing coincidence detection signal indicates that the first switching timing and the sampling timing of the second clock pulse substantially coincide with each other, the second data changes the second clock pulse to the second clock pulse. When the timing coincidence detection signal indicates that the second switching timing and the sampling timing in the second clock pulse substantially coincide with each other, the first data is the second data. Are sampled using the clock pulses of. As a result, data with a converted sampling rate is obtained.

When sampling (resampling) the first data using the second clock pulse, the resampling timing of the second clock pulse and the timing at which individual data in the first data changes If and match, resampling may not be relatively accurate. Therefore, it is detected whether or not the resampling timing of the second clock pulse and the timing at which the individual data in the first data changes match. If they match, the second data is resampled by the second clock pulse. If they do not match, the first data is
Resampled by pulse.

Preferably, the delay circuit is a digital delay circuit.

In such a situation, if it is determined that they match, the second data is resampled by the second clock pulse, but at the time when it is determined that they match (timing match detection signal At the rising edge or the falling edge), the timing at which the individual data of the second data changes may coincide. For this reason, at the time when it is determined that they match, the timing match detection signal is set to 2 times the frequency of the first clock pulse so that the first data is resampled without resampling the second data. Clock with double frequency
It is delayed for half a pulse period. Since the timing coincidence detection signal is delayed for a half cycle of the clock pulse having a frequency twice the frequency of the first clock pulse, the timing coincidence after the resampling time by the second clock pulse is delayed. It is possible to prevent the detection signal from rising or falling at the same time.

[0011]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention and is a block diagram showing an electrical configuration of a sampling rate conversion apparatus.

The sampling rate conversion device shown in FIG. 1 uses the first data Din obtained by sampling using the first clock pulse CK1 having the first sampling frequency f1 as the first sampling frequency. a second clock having a second frequency f2 different from f1
Resampling is performed using the pulse CK2.
The sampling rate converter shown in FIG. 1 resamples the first data Din by using the second clock pulse CK2 regardless of which of the first frequency f1 and the second frequency f2 is higher. However, the case where the first frequency f1 is higher than the second frequency f2 will be described first.

In the sampling rate converter shown in FIG. 1, in addition to the first data Din, the first clock pulse CK1 and the second clock pulse CK2, the frequency f of the first clock pulse CK is _A clock pulse 2CK1 having a frequency of twice ₁ is provided.

The first data Din supplied to the sampling rate converter is supplied to the data input terminals of the first flip-flops 19 and 20.

The first clock pulse CK1 is applied to the clock input terminal of the first flip-flop 19.
Also, the first clock pulse CK1 is the second flip pulse
It is inverted and given to the clock input terminal of the flop 20.
As a result, the first flip-flop 19 has the first
The first data D during one cycle of the clock pulse CK1 of
in is retained. The output of the first flip-flop 19 is provided as output data Data to the multiplexer 22 included in the sampling circuit 21. The second flip-flop 20 holds the first data Din for one cycle of the first clock pulse CK1. The output of the second flip-flop 20 is supplied to the multiplexer 22 included in the sampling circuit 21 as the output data Dataab.

The first clock pulse CK1 is also applied to the timing coincidence detection circuit 10. A second clock pulse CK2 having a second frequency f2 different from the first frequency f1 of the first clock pulse CK1 is inverted by the inverting circuit 13 and applied to the timing coincidence detection circuit 10. . The timing coincidence detection circuit 10 detects and detects that the first switching timing at which the output data Data of the first flip-flop 19 changes and the rising timing of the second clock pulse CK2 coincide with each other. If the timing coincidence detection signal AL becomes L level,
It outputs T.

The timing coincidence detection signal includes the falling edge of the first clock pulse CK1 and the second clock pulse C.
Rise of K2 (inverted second clock pulse CK2
When it is closest to the falling edge of b, the rising edge rises to the H level, the rising edge of the first clock pulse CK1 and the rising edge of the second clock pulse CK2 (falling edge of the inverted second clock pulse CK2b). ) And L fall to the L level when they are closest to each other. When the second switching timing at which the output data Datatab of the second flip-flop 20 changes and the rising timing of the second clock pulse CK2 match, the timing match detection signal becomes H level.

The timing coincidence detection signal output from the timing coincidence detection circuit 10 is applied to the flip-flop 18. A clock pulse 2CK1 having a frequency twice that of the first clock pulse CK1 is also inverted and applied to the clock input terminal of the flip-flop 18. This causes the flip-flop 18 to output the timing coincidence detection signal ALT with a delay of half the half cycle of the first clock pulse CK1.
The output of the flip-flop 18 is given as the data ALTD to the multiplexer 22 included in the sampling circuit 21.

The multiplexer 22 selects and outputs the data Data output from the first flip-flop 19 when the applied timing detection signal ALTD is at L level, and outputs the second data when it is at H level. The data Dataab output from the flop 20 is selected and output. Therefore, when the rising timing of the second clock pulse CK2 and the switching timing of the first data Din coincide with each other, the data D obtained by inverting the first data Din
atab is output from the multiplexer 22. In other cases, the first data Din is output as the first clock pulse CK1.
Data that has been delayed by the period of
It is output from 22. Therefore, it is possible to prevent the switching timing of individual data of the data Dalt output from the multiplexer 22 and the rising timing of the second clock pulse CK2 from matching.

The data Dalt output from the multiplexer 22 is applied to the data input terminal of the flip-flop 23. The second clock pulse CK2 is also applied to the clock input terminal of the flip-flop 23. As a result, the input data Din from the flip-flop 23 becomes
The resampled data Dout is output at the timing of the second clock pulse CK2. This data D
out includes the interpolation data that is output partially overlapping.

In the sampling rate converter shown in FIG. 1, the timing coincidence detection signal ALT output from the timing coincidence detection circuit 10 is delayed by a half cycle of the first clock pulse CK1. Therefore, it is possible to prevent the switching timing of the data represented by the timing coincidence signal and the switching timing of the individual data Data and Dataab from matching.

Next, the detection operation of the timing coincidence detection circuit 10 will be described.

In FIG. 1, the timing coincidence detection circuit 10
Includes a first phase comparison circuit 11 and a second phase comparison circuit
12 included. Both the first phase comparison circuit 11 and the second phase comparison circuit 12 have the first clock pulse CK.
It is a circuit that compares the phase difference between 1 and the second clock pulse CK2 and outputs a signal indicating the phase difference. The first phase comparison circuit 11 has a falling edge of the first clock pulse CK1 and an inverted pulse CK2 of the second clock pulse CK2.
Compare with the falling edge of b, the first clock pulse CK1
Is a circuit that outputs a signal representing the phase difference between the second clock pulse CK2 and the second clock pulse CK2. The second phase comparison circuit 12 is the first
Rising of the clock pulse CK1 of the second clock
It is a circuit that compares the falling edge of the inverted pulse CK2b of the pulse CK2 and outputs a signal indicating the phase difference between the first clock pulse CK1 and the second clock pulse CK2.

The first phase comparison circuit 11 outputs signals U1 and D1 representing the phase difference, and the second phase comparison circuit 11
Signals U2 and D2 representing the phase difference are output from 12. Of these signals, the signals D1 and D2 are used when there is a relation of f1 <f2 between the first frequency f1 and the second frequency f2, and the signals of the first frequency f1 and the second frequency f2 are used. Signals D1 and D2 are used when there is a relationship of f2 <f1. Since f1 <f2 in the time chart shown in FIG. 2, signals D1 and D2
Is used.

The phase difference comparison signal D1 output from the first phase comparison circuit 11 is applied to the NAND circuit 15. The phase difference comparison signal D1 is also inverted and given to the NAND circuit 16. The phase difference comparison signal D2 output from the second phase comparison circuit 12 is given to the NAND circuit 16. Further, the phase difference comparison signal D2 is inverted and also applied to the NAND circuit 15.

The signal A output from the NAND circuit 15 and the signal B output from the NAND circuit 16 are applied to the flip-flop 17. The output of the flip-flop 17 becomes the timing coincidence detection signal ALT. This timing coincidence detection signal ALT is the first clock pulse CK1.
When the phase difference between the first frequency f1 of the second clock pulse CK2 and the second frequency f2 of the second clock pulse CK2 is in the range of 0 ° to 180 °, this phase difference is 180 ° to 36 °.
L level when the range is up to 0 °. This timing coincidence detection signal ALT is applied to the flip-flop 18 as described above, and is delayed by 1/2 cycle of the first clock pulse CK1 to become the delayed timing coincidence detection signal ALTD.

FIG. 3 shows a configuration example of the phase comparison circuit. This phase comparison circuit is the first phase comparison circuit 11 and 12 included in the sampling rate converter shown in FIG.
Commonly used for.

FIG. 4 is a time chart showing input / output signals of the phase comparison circuit shown in FIG.

In FIG. 3, R and V are provided in the phase comparison circuit.
Input terminals and output terminals of U and D are included. R
The first clock pulse CK1 or an inverted pulse of the first clock pulse CK1 is applied to the input terminal of
An inverted pulse of the second clock pulse CK2 is applied to the V input terminal. As a result, the phase comparison circuit outputs signals representing the phase difference from the output terminals U and D. The signal output from the output terminal U is the first clock
The frequency f1 of the pulse CK1 is the second clock pulse C
It is used as a signal representing a phase difference when the frequency is higher than the frequency f2 of K2, and the signal output from the output terminal D is used as a signal representing a phase difference when the frequency f1 is lower than the frequency f2. Is. This phase difference signal is applied to NAND circuits 15 and 16 shown in FIG.

FIG. 5 shows a modification of the flip-flop. This flip-flop is a flip-flop 17 and a phase comparison circuit 11 or 12 included in the timing coincidence detection circuit 10 of the sampling rate converter shown in FIG.
Used in the flip-flops included in.

The flip-flop included in the timing coincidence detection circuit 10 or the phase comparison circuit 11 or 12 has two NANs as can be seen from the flip-flop 17 of FIG.
It is composed of a D circuit. The input terminal of one NAND circuit is a set input terminal, and the input terminal of the other NAND circuit is a reset input terminal. Also one NAND
The output of the circuit is given to the input terminal of the other NAND circuit, and the output of the other NAND circuit is given to the input terminal of the one NAND circuit.

In the flip-flop 17 having the configuration as shown in FIG. 1, when spike noise having a pulse width shorter than the delay amount of two NAND circuits is inputted to the set input terminal, the NAND as shown in FIG. The outputs Q and QB of the circuit may oscillate.

In the flip-flop shown in FIG. 5, the input of one NAND circuit 41 is connected to the set input terminal, and the output of the other NAND circuit 42 is applied to the input. In the other NAND circuit 42, the signal applied to the reset input terminal and one N
In addition to the output of the AND circuit 41 being given as it is, the output of one NAND circuit 41 is delayed and input in the buffer circuit 40.

One NAND is provided in the other NAND circuit 42.
A wide pulse in which the output of the circuit 41 and the output delayed by the buffer circuit 40 are combined is input.
Therefore, it is possible to prevent oscillation even when narrow spike noise is mixed in the flip-flop.

FIG. 8 is a time chart showing signals flowing in each circuit of the sampling rate converter shown in FIG. The time chart shown in FIG. 8 corresponds to the time chart shown in FIG. 2, but the time chart shown in FIG. 8 shows that the first frequency f1 of the first clock pulse CK1 is the second clock. .Second of pulse CK2
The frequency f2 is larger than the frequency f2.

When the second frequency f2 is higher than the first frequency f1, interpolation is performed for specific data of the data Dout output from the sampling rate converter, but the first frequency f1 is Second frequency f
If it is larger than 2, the data Dout output from the sampling rate converter is thinned out for specific data.

Since the time chart shown in FIG. 2 and the time chart shown in FIG. 8 have no substantial difference except the difference between the first frequency f1 and the second frequency f2, there is no further overlap. Avoid the explanation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a sampling rate conversion device.

FIG. 2 is a time chart showing signals flowing in each circuit of the sampling rate conversion device shown in FIG.

FIG. 3 is a block diagram showing an electrical configuration of a phase comparison circuit.

FIG. 4 shows input / output signal waveforms of a phase comparison circuit.

FIG. 5 shows a configuration example of a flip-flop.

FIG. 6 shows input / output signal waveforms when the flip-flop shown in FIG. 5 does not include a buffer circuit.

FIG. 7 shows input / output signal waveforms of the flip-flop shown in FIG.

8 is a block diagram showing an electrical configuration of the sampling rate conversion device shown in FIG. 1. FIG.

[Explanation of symbols]

10 Timing match detection circuit 11, 12 phase comparison circuit 18 flip-flops (delay means) 20 flip-flops (phase shift means) 21 Sampling circuit

Claims (2)

(57) [Claims] 1. The phase of the first data obtained as individual data by sampling with a first clock pulse having a first sampling frequency is said first phase .
Phase shift means for generating a second data by shifting a half cycle of the clock pulse of the first data, the first data changing the individual data in the first data
And a second clock having a second sampling frequency different from the first sampling frequency.
That the sampling timing in the pulse is substantially the same or that the second switching timing at which the individual data of the second data changes and the sampling timing in the second clock pulse are substantially the same. The timing coincidence detection means for generating and outputting the represented timing coincidence detection signal and the timing coincidence detection signal output from the timing coincidence detection means are input, and the timing coincidence detection signal is the first
Of the second clock pulse and the sampling timing of the second clock pulse substantially coincide with each other, the second data is sampled using the second clock pulse, and the timing When the coincidence detection signal indicates that the second switching timing and the sampling timing of the second clock pulse are substantially coincident with each other, the second clock pulse is used for the first clock pulse. In a sampling rate conversion device equipped with resampling means for sampling data, the timing coincidence detection signal output from the timing coincidence detection means and the first clock pulse
Input a clock pulse with twice the frequency
Then, input the above timing coincidence detection signal to the above
A sampling rate conversion device comprising: a delay circuit for delaying and outputting the clock pulse for a half cycle . 2. The sampling rate conversion device according to claim 1, wherein the delay circuit is a digital delay circuit.