JP3407604B2 - Latch miss detection circuit and PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch error detection circuit for a logic circuit which operates with a high-speed clock signal, so that the frequency of the oscillator and the phase of the oscillator are synchronized with the frequency of the input signal. The present invention relates to a PLL (Phase Locked Loop) circuit that feedback-controls a phase difference.

[0002]

2. Description of the Related Art In recent years, with progress in semiconductor process technology, LSIs in which digital circuits and analog circuits coexist have been put to practical use. PLL circuits including analog circuits such as charge pumps and voltage-controlled oscillators are no exception.
It is integrated into one chip together with a digital circuit that operates using the output signal of the LL circuit as a clock. A PLL circuit having a general configuration is shown in FIG. The oscillation output fvco from the voltage controlled oscillator 8 is divided into 1 / M by the frequency divider 9 to obtain a divided output signal fp. The phase comparator 5 compares the phases of the input signal fin and the frequency-divided output signal fp. The charge pump 6 charges or discharges the low-pass filter (LPF) 7 according to the phase comparison output. The low-pass filter 7 smoothes charge / discharge of electric charge and outputs a DC voltage Vcnt. The voltage controlled oscillator 8 has an oscillation output fvc having a frequency corresponding to the control voltage Vcnt.
Output o. By configuring the closed loop circuit in this way, the divided output fp can be synchronized with the input signal fin.

For the frequency divider 9, a toggle flip-flop (T-FF) or a counter circuit using a plurality of flip-flops is used. As an example, FIG. 4 shows a divide-by-2 circuit using a D flip-flop. Inverted output NQ is input D
The output Q and NQ are inverted at each rising edge of the clock input fvco by feeding back to the clock input fvco. Also,
FIG. 5 shows a so-called Johnson counter using two flip-flops, which operates as a divide-by-4 circuit.

[0004]

The control voltage Vcnt vs. oscillation output fvco characteristic of the voltage controlled oscillator 8 varies depending on environmental temperature conditions, power supply voltage conditions, individual differences and the like. In a voltage controlled oscillator that is realized on an LSI process that has undergone fine processing, it is necessary to see this variation range larger than when it is configured with individual components. Due to this variation range, the maximum oscillating frequency of the voltage controlled oscillator 8 may exceed the upper limit of the stable operating frequency of the flip-flop that constitutes the frequency divider 9. Normally, this is not the case when the PLL circuit is in a locked state, but the output Vcnt of the low-pass filter 7 rises or falls when the power is turned on or noise from the outside, which results in an abnormal oscillation frequency. There is a great risk of rising.

When the oscillation frequency of the voltage controlled oscillator 8 exceeds the stable operation frequency of the flip-flop, so-called latch miss occurs, and the output of the flip-flop is not updated at every rising edge of the oscillation output fvco. Figure 4
The output is not updated when a latch miss occurs in the toggle flip-flop shown in (4), but the output is restarted when it is latched correctly again. In the Johnson counter shown in FIG. 5 as well, the logic levels of the two flip-flops are not updated when a latch miss occurs, but the output is restarted when the latch is correctly performed again.

That is, in the unstable region where the latch miss occurs or does not occur, the output fp of the frequency divider 9 becomes lower than the output frequency when the frequency is normally divided. In this case, the PLL circuit is in a pseudo lock state in which it is synchronized with an erroneous frequency, or is in a deadlock state in which the oscillation frequency is stuck to the upper limit.

When a PLL circuit is constructed by using a voltage controlled oscillator having a wide variation range as described above, there is a problem that a pseudo lock or deadlock occurs.

In a so-called frequency synthesizer for obtaining an arbitrary frequency division output or multiplication output from a reference frequency signal obtained from a crystal oscillator by using a PLL circuit, a phase error which is an output of a phase comparator is monitored and unlocked. Has been proposed, and a method of determining a deadlock state if the unlock state continues is proposed. For example, JP-A-63-260320 and JP-A-63-2
See Japanese Patent No. 60321.

However, in the case where the frequency of the input signal fluctuates and further has jitter, it is possible to detect only the unlocked state accurately because the state is locked while having a large phase error in an instant. It is difficult and such a method cannot be applied.

In view of the above problems, the present invention automatically detects the instability of the operation of the flip-flops constituting the frequency divider, and automatically based on the determination result of the latch error detection circuit. PL to initialize the loop
It is intended to provide an L circuit.

[0011]

The latch error detection circuit of the present invention is a latch error detection circuit provided with a determination circuit for determining whether the output of a frequency divider repeats two logic levels or is fixed at a constant level. Yes, the PLL of the present invention
The circuit determines that the frequency divider is in an unstable operation state based on the output of the latch error detection circuit, and forcibly changes the output voltage of the low-pass filter to control the charge pump to lower the oscillation frequency. PL with control circuit
It is an L circuit.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION
The frequency divider circuit that stops the frequency division operation when the operation becomes unstable, and the discrimination circuit that determines whether the output of the frequency divider circuit keeps changing or is fixed. It is determined that the latch miss has occurred when the logic level of has not changed.

The frequency dividing circuit operates with a first flip-flop set to a logic level of 1 or 0 at initialization and a clock common to the first flip-flop, and the first flip-flop at initialization. And a second flip-flop set to an exclusive logic level, the output of the first flip-flop is connected to the input of the second flip-flop, and the output of the second flip-flop is the first It is configured to be fed back to the input of the flip-flop.

In the frequency divider circuit, if the frequency of the clock signal of the flip-flop becomes abnormally high and the flip-flop causes a latch miss even once, the logic levels of the two flip-flops are fixed and the frequency division operation is performed. Stop.

The operation does not stop when two flip-flops simultaneously make a latch miss, but it is not considered that the two flip-flops always make a latch miss at the same time in an unstable operation region. Therefore, the above configuration is sufficiently unstable. Can detect motion.

Further, the PLL circuit of the present invention comprises the above-mentioned latch miss detection circuit and the initialization control circuit, and inputs the oscillation output of the voltage controlled oscillator as the operation clock of the latch miss detection circuit, and the latch miss detection circuit causes the latch miss of the flip-flop. Is detected, the initialization control circuit controls the charge pump to forcibly change the output voltage of the low-pass filter.

When the latch error detection circuit detects that the oscillation output of the voltage controlled oscillator rises and the flip flop causes the latch error, it is determined that the operation of the frequency divider is unstable. Since the initialization control circuit controls so as to lower the oscillation frequency, no pseudo lock or deadlock occurs.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the latch error detection circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a latch error detection circuit of the present invention. In FIG. 1, 1 and 2 are flip-flops, which are initialized to exclusive logic levels by an initialization signal RESET. Here, the flip-flop 1 is initialized to the logic level 1 and the flip-flop 2 is initialized to the logic level 0. However, the flip-flop 1 is initialized to the logic level 0 and the flip-flop 2 is initialized to the logic level 1. Good. Three
The frequency divider divides the output signal of the flip-flop 2 into 1 / N. Reference numeral 4 denotes a cycle measuring device which measures the cycle of the output signal of the frequency divider 3 and outputs a detection flag DET when the cycle becomes longer than a predetermined value.

The flip-flops 1 and 2 operate with a common operation clock fvco, and latch and output inputs at the rising edge of the operation clock fvco. The Q output of the flip-flop 1 is connected to the D input of the flip-flop 2, and the Q output of the flip-flop 2 is connected to the D input of the flip-flop 1 to form a closed loop.

Since the flip-flops 1 and 2 are initialized to exclusive logic levels, their outputs are the operation clock fv.
The inversion is repeated in synchronization with the rising edge of co. That is, the outputs of the flip-flops 1 and 2 are the operation clock f
Inversion is repeated at a cycle twice as long as vco, which means that a divide-by-2 circuit is formed.

When the frequency of the operation clock fvco is in the stable operation area of the flip-flop, the above-described frequency division operation is performed. The frequency of the operating clock fvco increases,
When the operation of the flip-flop becomes unstable, so-called latch miss occurs and the output logic level of the flip-flop cannot be updated.

When a latch miss occurs in either one of the flip-flops 1 and 2, the Q outputs of the flip-flops 1 and 2 become the same logic level at that moment, and the operation as the frequency divider halves. The relationship that the Q output is exclusive when the latch misses occur simultaneously in the flip-flops 1 and 2 is maintained, but in such an unstable operation region,
The two flip-flops cannot always make a latch miss at the same time, and if a latch miss occurs, the dividing operation is surely stopped.

The Q output of the flip-flop 2 is divided by the frequency divider 3 into 1 / N (N is an arbitrary integer). Since the signal input to the frequency divider 3 has already been frequency-divided by the flip-flops 1 and 2, there is no concern that a latch miss will occur here. The cycle of the output signal of the frequency divider 3 is the operation clock fvc.
2N times o. The frequency division ratio N is
The cycle of the output signal of the frequency divider 3 is selected to be a value that can be measured with the fixed clock fxtl. If a latch miss occurs in the flip-flops 1 and 2 and the operation as the frequency divider 2 stops, the frequency divider 3
Output also stops and the logic level is fixed.

In the period measuring device 4, the period of the input signal is
When it becomes longer than the predetermined value, the detection flag DET is output. This predetermined value is set to a value longer than the range of the output signal cycle of the frequency divider 3 determined by the lowest value of the variable range of the operation clock fvco.

When a latch error occurs in the flip-flops 1 and 2, and as a result, the output of the frequency divider 3 is stopped, the period measuring device 4 outputs the detection flag DET because the period of the input signal becomes longer than a predetermined value.

For example, fvc that is assumed to be normal operation
The range of o is 10 to 80 MHz, and the fixed clock fxtl is 10 MHz. When fvco is 80 MHz, the output cycle of the frequency divider 3 may be measured by fxtl of 10 MHz. That is, the value of N may be selected so that 80 MHz / 2N> 10 MHz, and N> 4. If N = 8 is set, the output of the frequency divider 3 is 0.625 to 5 MHz. When this is cycle-measured with fxtl of 10 MHz, the measured value becomes 2 to 16 counts. Therefore, when the measured value exceeds 16 counts, it is determined that a latch miss has occurred in the flip-flops 1 and 2.

Next, an embodiment of the PLL circuit of the present invention will be described with reference to the drawings. FIG. 2 shows the PL of the present invention.
It is a block diagram of one example of an L circuit. In FIG.
Reference numeral 5 is a phase comparator that outputs a phase error between the two input signals fin and fp, 6 is a charge pump that charges or discharges charges, and 7 is a low-pass filter that smoothes charge / discharge of charges and outputs a DC voltage Vcnt ( LPF), 8 is a voltage controlled oscillator that outputs an oscillation output fvco having a frequency according to the DC voltage Vcnt,
Reference numeral 9 is a frequency divider for dividing the oscillation output fvco into 1 / M (M is an arbitrary integer), and 10 is a detection flag DE when a flip-flop causes a latch miss due to an increase in the oscillation output fvco.
A latch error detection circuit that outputs T, and an initialization control circuit 11 that controls the charge pump 6 to forcibly reduce the oscillation frequency of the voltage controlled oscillator 8.

Normally, the oscillation output fv of the voltage controlled oscillator 8
The phase difference between the signal obtained by dividing co by fp and the input signal fin is also detected by the phase comparator 5, and the charge pump 6 charges or discharges the low-pass filter 7 in accordance with the phase error. The charge / discharge of charges is smoothed by the low-pass filter 7, and the voltage controlled oscillator 8 changes the oscillation frequency according to the output voltage Vcnt. By constructing such a closed loop,
The frequency division output fp can be synchronized with the input signal fin.

The output voltage Vcnt of the low-pass filter 7 may exceed the normal control voltage range of the voltage controlled oscillator 8 when the power is turned on or when noise is injected from the outside. If the oscillation frequency exceeds the control voltage range in the increasing direction, the frequency divider 9 exceeds the frequency range in which it operates stably. In such a frequency range, the operation of the flip-flop in the latch error detection circuit 10 becomes unstable, and the latch error detection circuit 10 outputs the detection flag DET.

The unstable operation of the flip-flop is eliminated by forcibly changing the control voltage Vcnt to the normal control range and lowering the oscillation frequency of the voltage controlled oscillator 8. When the detection flag DET is input, the initialization control circuit 11 instructs the charge pump 6 to forcibly charge or discharge electric charges so as to decrease the oscillation frequency of the voltage controlled oscillator 8. When the voltage controlled oscillator 8 has a positive gain characteristic (the oscillation frequency also rises as the control voltage rises), it is discharged, and when it has a negative gain, it is charged.

Further, the latch error detection circuit 10 is initialized. The flip-flops 1 and 2 shown in FIG. 1 are set to exclusive logic levels to operate again as a frequency-dividing circuit, the detection flag DET is cleared, and a latch miss detection waiting state is set.

When the initialization operation is completed, the oscillation frequency of the voltage controlled oscillator 8 is forcibly lowered, and the closed loop operation is performed so that the frequency division output fp synchronized with the input signal fin can be obtained again.

In this embodiment, the latch error detection circuit 1
Although it has been described that the frequency divider 9 is provided separately from the frequency divider in 0 (the flip-flops 1 and 2 and the frequency divider 3 in FIG. 1), the frequency divider in the latch miss detection circuit 10 is divided into frequency dividers 9 and 9. Alternatively, the output of the frequency divider in the latch error detection circuit 10 may be further divided.

[0034]

As described above, according to the latch error detection circuit of the present invention, the latch error of the logic circuit due to the increase of the operating frequency can be detected with certainty, which is very effective in practice. Further, according to the PLL circuit of the present invention, it is possible to recover from the deadlock or the pseudo lock by detecting the deadlock or the pseudo lock when the power is turned on or when the noise is applied and automatically initializing the loop. It is very effective in practice.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a latch error detection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 4 is a circuit diagram showing a configuration example of a frequency divider using a toggle flip-flop.

FIG. 5 is a circuit diagram showing a configuration example of a frequency divider using a Johnson counter.

[Explanation of symbols]

1 and 2 flip flops 3 frequency divider 4 period measuring instrument 5 Phase comparator 6 Charge pump 7 Low-pass filter 8 Voltage controlled oscillator 9 divider 10 Latch miss detection circuit 11 Initialization control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03L ^7/ 00-7/14 H03K 21/40

Claims (2)

(57) [Claims] 1. A first flip-flop that is set to a logic level of 1 or 0 at initialization, and a first flip-flop that operates with an input clock common to the first flip-flop and that is initialized at initialization. A second flip-flop set to an exclusive logic level, the output of the first flip-flop is connected to the input of the second flip-flop, and the output of the second flip-flop is the A first frequency division circuit is configured to be fed back to the input of the flop circuit, and a determination circuit for determining whether the output of the frequency division circuit repeats two logic levels or is fixed at a constant level. Latch miss detection circuit. 2. A voltage controlled oscillator, a frequency divider for dividing an oscillation output of the voltage controlled oscillator, a phase comparator for comparing a phase difference between an input signal and an output signal of the frequency divider, and the phase comparison. And a low-pass filter for smoothing the output of the charge pump and outputting the control voltage of the voltage-controlled oscillator, the oscillation output of the voltage-controlled oscillator being an input clock. The latch miss detection circuit according to claim 1, and an initial stage for controlling the charge pump to forcibly change the output voltage of the low pass filter when the output of the latch miss detection circuit indicates that a latch miss has occurred. PLL circuit including an activation control circuit.