JP3402956B2 - VTR motor controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of a video tape recorder (hereinafter, referred to as "VTR"), and more particularly to interrupt processing of a system control microcomputer. 2. Description of the Related Art Generally, when a motor speed control in a VTR is performed by a microcomputer, an F terminal generated by rotation of a capstan motor and a drum motor is provided to an interrupt terminal of the microcomputer.
The G signal is input, the period of the FG signal is measured and detected by the timer counter for each interrupt from the interrupt generation time of the FG signal, and the detected value is compared with a target period value to obtain a period difference. The motor speed control signal is created by calculating the gain suitable for the motor. [0003] When speed control is performed by a microcomputer, processing from input of an FG signal to output of a motor control signal is performed by software operation, and if there is another higher-order interrupt, the operation processing is postponed. It may take a long processing time to output a control signal. If the time is extremely long, a case may occur in which the captured FG signal deviates from the FG signal for interrupt processing. That is, a so-called "interruption missing" in which interrupt processing cannot be performed on a captured FG signal.
Occurs. In this case, the difference between the measured FG cycle and the target value becomes large, and the microcomputer outputs a motor control signal in accordance with the difference, which causes a problem that the rotation of the motor becomes uneven. Usually, as a method for solving this problem, an FG signal such that the next FG signal is not captured from the capture of the FG signal to the output of the control signal with respect to the operation speed of the microcomputer or the delay time caused by the occurrence of another higher-order interrupt. There is a method in which control is performed by a cycle and a control is performed by an FG signal having a long capture cycle without any problem, and a method of increasing the priority of interrupt processing which causes a problem when an interrupt is lost. However, in the former case, if the FG period to be controlled is lengthened, the control frequency becomes lower, so that the gain of the control system cannot be increased. Therefore, the disturbance suppression capability of the motor decreases, and the stability of the control system decreases. Gets worse. In the latter case, it is necessary to change the interrupt priority order and to cope with the microcomputer such as arbitration with other interrupt processing. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and when an interrupt process cannot be performed on a captured FG signal (a so-called interrupt missing), a motor disturbance is generated. It is a technical object to perform control so as not to cause suppression of motor rotation unevenness without lowering the suppression capability and changing the interrupt priority order. According to the present invention, there is provided a motor control device of a VTR for controlling the rotation of a drum on which a magnetic head is mounted, which generates a signal having a frequency corresponding to the rotation of a motor for driving the drum. A frequency generator, a counter that counts a reference clock, a latch circuit that latches the output of the counter based on the output of the frequency generator, and a microcomputer that uses the output of the frequency generator as an interrupt input.
A read / write storage unit, wherein the microcomputer reads an output value of the latch circuit for each interruption of the frequency generator, and calculates a difference between the output value and a value (to) read from the storage unit. An output signal cycle value (T) of the frequency generator is obtained, the storage unit enables reading and writing of a plurality of values, the output signal cycle value (T) is sequentially written to the storage unit, and the output cycle value (T) is written. ) Is larger than a predetermined value, the control signal is created by averaging a plurality of values read from the storage unit. An embodiment of a control device according to the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a motor control circuit of a VTR according to the present invention. In the figure, reference numeral (1) denotes a microcomputer, which generates a capstan motor drive signal (CPWM) and a drum motor drive signal (DPWM) by an arithmetic operation by interrupt processing according to each signal input to the interrupt terminals INT0 to INT3. And output. A capstan motor driver (2) supplies a drive current to the capstan motor (3) according to the CPWM signal from the microcomputer (1). A drum motor driver (4) supplies a drive current to the drum motor (5) according to a DPWM signal from the microcomputer (1). (6) is a capstan FG, which generates a CFG signal pulse by the rotation of the capstan motor (3). (7) is a drum FG, which generates a DFG signal pulse by rotation of the drum motor (5). A capstan (8) is driven by a capstan motor (3) and feeds a magnetic tape (9). A rotary drum (10) records / reproduces a video signal on a video track of a magnetic tape (9) by a plurality of magnetic heads attached to the drum. Reference numeral (11) denotes a drum PG, which generates one pulse for one rotation of the drum motor (5). The DFG signal is counted based on this signal, and the RFSW for determining the switching timing of the magnetic head is determined.
Create a pulse. A control head (12) extracts a CTL signal from a control track of the magnetic tape (9). These RFSW signal, CTL signal, CF
Each signal of G signal and DFG signal is converted into INT of microcomputer (1).
0, INT1, INT2, and INT3 are input to respective interrupt terminals. When the above-mentioned device is driven, each of the above-mentioned signals is generated as shown in a, b, c and d of the timing chart shown in FIG. A counter (13) is counted by a reference clock. A latch circuit (14) latches the value of the counter (13) at the rising edge of the DFG signal. This latch output is input to the microcomputer (1). Thus, the microcomputer (1) operates at the falling edge of the RFSW signal, the rising edge of the CTL, and the CFG.
Interrupt processing is performed at the rising edge of the signal and the rising edge of the DFG signal. Here, the priority of the interrupt processing is in the order of the RFSW signal, the CTL signal, the CFG signal, and the DFG signal.
It is performed until the interrupt processing with the higher priority is completed. In FIG. 2, there is a case where other interrupts are concentrated around the fall of the RFSW signal. In this case, as shown by A, B, and C in the figure, the RFSW interrupt (A), the CTL interrupt (B), and the CFG interrupt (C)
Is performed. Since the interrupt processing of the DFG has a low priority, the processing is performed after the upper interrupt is completed. At this time, the interrupt processing wait time is DFG
Since one cycle of the signal is exceeded, the processing for the interrupt of (1) is not performed. Here, the period of the DFG signal is obtained by latching the value of the counter for counting the reference clock at the rising edge of the DFG signal and reading this value in the interrupt processing.
Since the difference from the value at the time of the previous interrupt processing is calculated, the capture value of the FG signal read in the interrupt processing is changed to the FG signal one cycle after the original capture value when an interrupt is lost. FG
The cycle is about twice the target cycle. Therefore, the FG signal cycle used for the previous generation of the control signal is always held, and if the measured FG cycle is equal to or more than a predetermined number (for example, 1.5 times the target cycle), an interrupt is missed. Then, the control signal is generated in the held FG cycle of the previous measurement. This makes it possible to correct fluctuations in the measured FG cycle due to missing interrupts, and to prevent uneven rotation of the motor. FIG. 3 shows a flowchart of the interrupt control operation by the DFG signal of the present invention. When the DFG signal is input to the interrupt terminal INT3 of the microcomputer (1), the control shifts to this interrupt processing routine. First, in step 1, the value t of the counter is read. Next, in step 2, the difference from the output value t0 of the value latch circuit (14) obtained in the previous processing is obtained, and this difference is set as the period T of the DFG signal. Thereafter, the value t is stored as a new t0. In step 3, the value of T obtained in step 2 is compared with a predetermined value T1. The predetermined value T1 is, for example, 1.
It is assumed to be five times the value. If it is determined that T1 <T, in step 4, the control cycle value Tc is set to T, and in step 5, a speed control signal is generated. If it is determined that T1.gtoreq.T, a speed control signal is generated in step 5 using the control cycle value Tc used at the time of the previous interrupt. In step 6, PW is used as the speed control signal.
Output M signal. After the cycle of the drum FG is calculated by the above-described processing, the predetermined value is compared with the cycle. If the measurement cycle is equal to or longer than the predetermined value, this measured value is not used for generating the speed control signal. Is used to generate a speed control signal. As a result, it is possible to prevent the occurrence of uneven rotation of the drum motor due to the interruption. As shown in the flowchart of FIG. 4, if a plurality of periods of the DFG signal used for the calculation are continuously held and a control signal is created using an average value of the plurality of held FG periods, More stable correction for missing interrupts. According to the present invention, it is possible to correct the fluctuation of the measured FG cycle due to the missing interruption, and to prevent the rotation of the motor from being uneven. Furthermore, if a plurality of measurement periods used for the calculation are continuously held and a control signal is created using an average value of the held FG periods of the number of nuclei, more stable correction for missing interrupts is obtained. With the configuration according to the present invention, in the control of the motor by the microcomputer, it is possible to prevent the rotation unevenness of the motor due to the occurrence of the interruption.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a VTR control device of the present invention. FIG. 2 is a diagram showing timing of an interrupt signal of the VTR control device of the present invention. FIG. 3 is a flowchart of an interrupt processing routine. FIG. 4 is a flowchart of an interrupt processing routine. Microcomputer 2. 2. Capstan motor driver Capstan motor 4. 4. Drum motor driver Drum motor 6. Capstan FG 7. Drum FG 8. Capstan 9. Magnetic tape10. Rotating drum 11. Drum PG 12. Control head 13. Counter 14. Latch circuit

Claims (1)

(1) In a motor control device of a VTR for controlling rotation of a drum on which a magnetic head is mounted, a frequency for generating a signal having a frequency corresponding to the rotation of a motor for driving the drum. A generator, a counter that counts a reference clock, a latch circuit that latches the output of the counter with the output of the frequency generator, a microcomputer that uses the output of the frequency generator as an interrupt input, and a readable and writable storage unit. The microcomputer reads the output value of the latch circuit every time the frequency generator interrupts, and calculates the output of the frequency generator based on the difference between the output value and the value (to) read from the storage unit. Calculating a signal period value (T), the storage unit enables reading and writing of a plurality of values, and sequentially writing the output signal period value (T) in the storage unit; If the force period value (T) is larger than the predetermined value, the motor control apparatus of a VTR, characterized in that to create the control signal by averaging the plurality of values read from the storage unit.