JP3399042B2 - Hall element - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Hall element including a group III-V compound semiconductor heterojunction, and more particularly to a processing standard to be maintained in order to maintain the high mobility characteristic of the heterojunction.

[0002]

2. Description of the Related Art Hall elements have been known as magnetic sensors. Silicon (S
In addition to elemental semiconductors such as i) and germanium (Ge), indium antimonide (InSb), indium arsenide (InAs), gallium arsenide (GaAs), etc. A III-V group binary compound semiconductor formed by combining two elements belonging to V group is also used.

Recently, even in III-V group compound semiconductors, a ternary mixed crystal of gallium-indium-arsenide (GaInAs) and indium phosphide (In).
Attempts have also been made to apply a heterojunction composed of P) as a material for a new high-sensitivity Hall element equipped with a InP single crystal substrate (Okuyama Shinobu et al., Autumn 1992 53rd Applied Physics Society). Academic Lecture Proceedings No. 3
(Published by Japan Society of Applied Physics, 1992), 16a-SZC-1
6, pages 1078). It is said that this new GaInAs heterojunction Hall element brings about an unprecedented excellent product sensitivity because the characteristic temperature change is relatively small and the room temperature electron mobility is extremely high.

Other heterojunction structures that are considered to be applicable as Hall elements include GaAs / GaInAs and A.
There is a 1GaAs / GaInAs system. These hetero systems are lattice mismatched systems, unlike the above InP / GaInAs system. For the purpose of manufacturing Hall elements, GaA
It is suitable to have a laminated structure in which GaInAs is deposited as a magnetic sensing part layer on a buffer layer such as GaAs or AlGaAs on the s substrate. Because GaInAs is GaAs or AlG
This is because the band gap is smaller than that of aAs and an ohmic electrode is easily obtained. Therefore, for Hall elements, it is a good idea to provide GaInAs on the outermost surface layer on which electrodes are formed.

[0005]

However, GaAs, A
The GaInAs layer deposited on lGaAs has a rough surface because the lattice does not match the underlying layer.

GaAs or AlGaAs and GaInA
The lattice-mismatched heterostructure with s may be obtained by continuously laminating each layer from the viewpoint of crystal growth. For example, GaAs
In order to obtain a / GaInAs lattice mismatch heterostructure, the conventional method is to first deposit a GaAs layer on a GaAs single crystal substrate and then deposit a GaInAs layer continuously. Also, after stacking the lattice-mismatched heterostructures, Ga of the outermost surface layer
It is a conventional practice that the InAs layer is not thermally processed and the process proceeds directly to the element forming process. Therefore, GaI
Since the nAs layer has a lattice mismatch, the surface roughness during crystal growth remains. When the ohmic input / output electrodes of the Hall element are formed on such a rough surface, the position of the alloy front is not constant within the layer, causing instability in the ohmic characteristics, resulting in non-uniformity of the unbalance ratio of the Hall element. There was a problem that caused.

The unbalance rate is the output voltage (V
₀ ) and the Hall output voltage (V) under a certain magnetic flux density. That is, it is expressed by the following equation (1). Imbalance ratio (%) = V ₀ / (V−V ₀ ) × 100 (%).
.. (1) The unbalance ratio represents, so to speak, the S / N ratio, and if it becomes large, the sensitivity characteristics deteriorate and it is not convenient to operate the Hall element. Therefore, in the lattice mismatched hetero system such as GaAs / GaInAs, it is important to improve the surface roughness of GaInAs as the outermost surface layer. However, it has been
There is no method to improve the surface roughness of the lattice mismatch layer after each layer is laminated, which hinders the improvement of characteristics such as the unbalance ratio of the Hall element.

Regardless of the material used, a plurality of elements are formed on one single crystal substrate, and after a number of element forming processes, finally the Hall elements are diced so as to be individually cut. do. In this dicing, a cutting jig such as a diamond blade is used to mechanically cut the base material to separate it into individual elements. Traditionally, this cutting technique for singulation of the elements has, of course, focused solely on cutting the matrix material to obtain the individual elements. Therefore, whether or not the elements can be cut and separated surely, for example, the dicing method is unsuitable in that cutting is incomplete and individual elements are not completely separated, and adjacent elements are connected to each other. Was there. For this reason, in the past, in order to improve the yield of separation cutting with almost no influence of the dicing process on the change in the characteristics of the base material of the Hall element, the technology has been dicing under more severe conditions. It cannot be denied that it was facing.

However, in the Hall element that utilizes the high electron mobility characteristic developed by the heterojunction as described above, strain is introduced into the heterojunction portion due to the mechanical pressure required for dicing, and as a result, the hetero interface It was feared that the physical properties would be greatly adversely affected and the electron mobility would be lowered. In order to know the degree of electrical damage to the base material including the heterojunction due to this dicing, there has been no conventional method for quantitatively determining it easily. That is, the complicated work of actually measuring the electrical characteristics of each of the individually separated elements is required.

The inventor of the present invention has found that such conventional GaInAs
Deterioration of unbalance ratio of Hall element using lattice mismatch layer,
The subject of the present invention was earnestly studied to find a new method for preventing the fluctuation of the characteristics of the Hall element due to dicing, especially the deterioration of the characteristics of the Hall element including the heterojunction. As a result, it was found that the characteristics of the Hall element can be easily and easily prevented from deteriorating by defining the surface roughness of the epitaxially grown layer serving as the magnetic sensing layer and the surface roughness of the side surface of the substrate on which the element is formed. It came to.

[0011]

The present invention is based on GaInAs /
In a Hall element including a lattice-mismatched heterojunction such as InP or GaInAs / GaAs, the surface roughness of the magnetic sensing part layer is set to a PV value of less than 0.07 μm to prevent deterioration of the unbalance ratio. It is a thing. In addition, the mechanical condition for separating and cutting each element is limited, and the surface roughness of the side surface of the substrate forming the Hall element is defined as a PV value of less than 10 μm. By these, a high-quality heterojunction Hall element can be stably obtained without impairing the high electron mobility characteristic originally possessed by the above-mentioned base material.

The effect of the present invention is exerted, for example, G
a single heterojunction made of aInAs / InP, AlGaAs / GaAs or GaInAs / AlInAs,
Alternatively, in manufacturing a heterojunction Hall element composed of a double heterojunction composed of GaAs / GaInAs / AlGaAs, an elementization process similar to that of a conventional GaAs Hall element or the like is adopted. Therefore, although not described in detail, a brief description will be added here in the order of steps for forming the device.

First, in order to deposit such a heterojunction, a single crystal made of a high-resistance III-V group compound semiconductor having a semi-insulating property is used from the viewpoint of the electrical insulating property of the operating portion that performs the device function. A substrate is used. Substrates corresponding to this include GaAs and InP crystals exhibiting semi-insulating properties, and may be selected in consideration of the lattice matching of a compound semiconductor layer forming a desired heterojunction. For example, G
When forming an aAs / GaInAs heterojunction, a GaAs single crystal is adopted as a substrate. GaIn
When an As / InP heterojunction is desired, a semi-insulating InP single crystal is generally adopted as the substrate. Next, regarding the specific resistance showing the degree of insulation, which is one of the qualities of the single crystals used as these substrates, there is no great difference from the conventional GaAs Hall element for the Hall element, and the specific resistance is 10 ⁴ Ω ・ cm or more 10 ⁸ Ω ・
It is common to use single crystals of less than cm.

An AlGaAs layer or a GaInAs layer is epitaxially grown on these single crystal substrates. For example, in the case of forming a GaInAs / InP heterojunction, the GaInAs layer, which is the magnetic sensitive section, usually has a high electron mobility. Therefore, the InP epitaxial growth layer is generally deposited as a buffer layer on the InP single crystal substrate. By providing this buffer layer, In
Since the effect of suppressing diffusion of Fe impurities from the P single crystal substrate into the GaInAs epitaxial growth layer and suppressing the propagation of crystal defects and the like to the epitaxial growth layer are produced, the electron mobility of the GaInAs layer is not reduced. This is because it brings about an advantage that the high sensitivity characteristics of the Hall element can be maintained. Further, in the GaInAs / GaAs hetero system, a GaInAs layer is laminated on the GaAs buffer layer. In this case, GaInAs and GaAs are not lattice-matched. Therefore, the surface of the GaInAs layer is generally rougher than the surface of the lattice matching layer. Other buffer layers that lattice match GaInAs include AlInAs. Ga
AlGa is used as a buffer layer that does not lattice match with InAs.
As and the like can also be used. There is no particular limitation on the method of growing the epitaxial layer forming the heterojunction. Liquid phase epitaxial growth method, molecular beam epitaxial growth method, metalorganic pyrolysis vapor phase growth method, so-called MOVPE can be used. In addition, MO that combines both MOVPE and MBE
・ MBE method etc. can be applied.

Since GaInAs lattice-matches with InP, in such a lattice-matched heterojunction system, Ga _x In
_It is desirable that the mixed crystal ratio X of _1-x As Ga is 0.47 ± 0.10. Because X = lattice-matched to InP
Ga _x In _1-x As and In with the deviation from 0.47
This is because the difference in the lattice constant with P, that is, the degree of lattice mismatching becomes remarkable, which induces a large amount of crystal defects and the like, resulting in deterioration of crystallinity. Further, the electrical characteristics such as a decrease in electron mobility are also deteriorated, and the characteristics of the Hall element greatly impair the product sensitivity. On the other hand, GaAs or AlGaAs and GaI
When forming a heterojunction with nAs, Ga is
_{Since x} In _{1 -x} As does not have a lattice match with these, there is no strict limitation on X, and rather, X which gives good electrical results may be selected and adjusted by utilizing the lattice constant change layer.

The film thickness of the epitaxial layer forming the heterojunction according to the present invention is not particularly limited. However, in the actual manufacture of Hall elements, a process for removing a crystal layer in a specific region called mesa etching is generally adopted in order to electrically insulate elements from each other. Therefore, the total film thickness of the heterojunction system is approximately 5 μm.
Good results can be obtained with thinner settings. This is because an increase in the total thickness of the epitaxial growth layer inevitably leads to an increase in the time required for mesa etching, and is usually III-V.
<0 bar 11> which is the cleavage direction of the Group compound semiconductor crystal
Then, the difference due to the crystal orientation of the etching cross-sectional shape of the so-called Hall cross portion formed along <0 bar 1 bar 1> orthogonal to it becomes remarkable. This difference is partly responsible for increasing the unbalance ratio, which is one of the important characteristics of the Hall element, hindering the improvement of the quality of the element characteristics and lowering the yield of non-defective elements.

Particularly in the case of the lattice-mismatched hetero-laminated structure, a treatment for reducing the unbalance ratio of the Hall element is performed after the growth. This treatment is intended to improve the surface roughness of the GaInAs lattice mismatch layer surface. That is, the mismatched layer is heat-treated in an atmosphere containing arsenic (As) to smooth the surface. The PV value can be made 0.07 μm or less by heat treatment at a temperature of around 600 ° C. for about 30 minutes. FIG. 8A shows G deposited on the GaAs layer before heat treatment.
showing the way of the measurement results of the surface roughness of a _0.48 In _0.52 As layer. The PV value before heat treatment was 0.086 μm, but the temperature was 520 ° C in an air stream containing arsine (AsH ₃ ).
The surface roughness after heat treatment for 15 minutes was improved to a PV value of 0.032 μm as shown in FIG. 8B. As sources other than AsH ₃ can be used to create a heat treatment atmosphere containing As. In addition, Ga stacked on the InP layer
_{The 0.46} In _0.54 As lattice-mismatched layer can also have a surface with excellent flatness due to the heat treatment, resulting in Ga
This contributes to the reduction of the unbalance ratio of the InAs / InP heterojunction Hall element. As a specific example, a PV value becomes 0.02 μm or less by heat-treating a lattice mismatched layer of Ga _0.46 In _0.54 As having a mixed crystal ratio of 0.46 at a temperature of 680 ° C. for 30 minutes. When the mixed crystal ratio gives a larger degree of mismatch, the PV value can be easily set within an appropriate range by adding an idea such as increasing the heat treatment temperature or prolonging the heat treatment time. . The PV value is regulated by GaInAs / I
In the nP heterojunction system, there is no significant change depending on the mixed crystal ratio of Ga.

Here, the PV value is one of the indexes quantitatively representing the surface roughness. PV (Peak to Val)
The ley) value means the maximum value of the difference in height between the apex of the convex portion of the unevenness and the bottom point of the concave portion existing on the surface. For example,
It is assumed that the unevenness shown in FIG. 4 exists on the surface. Letting δ1, δ2, ... δn be the height difference of each unevenness, the maximum value among these δn values becomes the PV value. Therefore, assuming that the maximum value among certain numerical values is represented by max (), the PV value is expressed by the following equation (2). PV = max (δ1, δ2, δ3, ... δn) ... Equation (2) For example, a Ga _0.55 In _0.45 As layer having a Ga mixed crystal ratio of 0.55 on the GaAs layer and a film thickness of 1 μm. PV value is 0.0
In the conventional example, the thickness is about 8 to 0.12 μm. FIG. 9 shows the relationship between the PV value of the lattice mismatched layer and the absolute value of the unbalance ratio in the Ga _0.48 In _0.52 As / GaAs lattice mismatched system. From the figure, if PV value is 0.07 μm or less,
It can be seen that the unbalance rate is within ± 10%.

A heterojunction Hall element is formed by using the heterojunction epitaxial wafer grown on the single crystal substrate as described above as a base material. There is no particular difference in the manufacturing process when making elements, as in the case of conventional Hall elements, and it is possible to use known photolithography technology, etching technology, etc., and make full use of these technologies to form input and output electrodes and separate A scribe line etc. for separating the elements into elements will be implemented. In dicing for actually separating individual Hall elements, scribing is performed along dicing lines. This scribe is actually performed using a diamond needle or diamond blade. In the present invention, the flatness of the side surface of the semiconductor wafer constituting the Hall element after separation is 10 μm in PV value.
The dicing process is performed so that it is less than the above. The reason for defining the PV value in this way will be described by taking a GaInAs / InP heterojunction Hall element as an example.
This is because when the V value is 10 μm or more, it is recognized that the electron mobility sharply decreases with this value as a critical value as shown in FIG. Conversely speaking, dicing processing that gives a PV value of less than 10 μm is indispensable for maintaining the superior characteristics of the heterojunction Hall element.

In order to obtain the element side surface having such a PV value after the dicing step, for example, when a diamond needle is used for dicing, the needle pressure, the dicing speed, the angle with the material to be cut, etc. The basic factors involved may be optimized. In addition, the shape of the tip of the diamond needle to be used and the number of points at the point of contact between the material to be cut and the needle also affect the PV value on the side surface of the obtained element, so care must be taken. Generally, it is desirable to reduce the stylus pressure as much as possible within a range sufficient for cleavage and slow the dicing speed.

Here, the difference in the flatness of the side surface of the device even though the flatness is less than 10 μm is mainly due to the dicing line forming direction, that is, the III-V group compound semiconductor crystal exhibits the cleavage property. It also depends on how the dicing line is formed parallel to the [110] crystal axis. The closer to the cleavage direction, the smaller the surface roughness of the side surface of the device. Further, the dicing line has a certain line width because the scriber at the time of scribing needs to run along this line. Therefore, even when the dicing line is formed so as to be exactly aligned with the cleavage direction, the traveling direction of the scriber changes within the line width of the dicing line. It is good to match the traveling direction of the scriber exactly with the cleavage direction. Specifically, good results are obtained when the angle is matched within ± 0.5 degrees with respect to the crystal axis direction which exhibits cleavage.

On the other hand, at the time of separation into individual elements, the above-mentioned operation is not performed, but the surface of the side surface constituting the element is roughly processed with chipping as in the conventional case, and then, etching or the like is performed. When the PV value on the side surface of the device is less than 10 μm, the electron mobility of the Hall device is not prevented from being lowered. It is essential to protect the GaInAs / InP heterojunction that exhibits high electron mobility from damage due to mechanical shock or pressure during element isolation. It is important to perform careful dicing to keep the flatness of the element side surface within an appropriate range, and the characteristics of the heterojunction contained in the base material that was once destroyed during separation are simply the side surface layer in the subsequent process. This is because the recovery cannot be achieved by flattening only this.

[0023]

The dicing lines are generally formed in the cleavage directions orthogonal to each other. This is because, when the elements are separated by dicing, the elements can be separated by utilizing the intrinsic property of the crystal called cleavage, which is a property that the crystal originally has, without applying excessive mechanical pressure to the dicing jig.
For the III-V group compound semiconductor crystal, the cleavage direction is [110], so that it is usually <0 bar 11> and <0 bar 11>.
A dicing groove is formed along 0 bar 1 bar 1>.
A dicing jig such as a diamond needle is passed along this groove. However, when forming the groove by etching, a difference occurs in the cross-sectional shape of the groove depending on the crystal orientation. More specifically, the cross section of the groove formed along the <0 bar 11> direction is an inverted triangular shape, so-called forward mesa,
The cross-sectional shape of the dicing line groove formed in parallel with the <0 bar 1 bar 1> orientation is a so-called reverse mesa whose bottom surface widens toward the depth direction of the triangular etching. By investigating the relationship between the cross-sectional shape of such a groove and the PV value of the side surface of the element obtained after dicing, in the case of scribing along a cross section showing a forward mesa, the PV value of the scribe surface of the line of the reverse mesa cross section In comparison with the above, a surface having a large PV value, that is, a surface having a rough surface is often obtained. This is because in a scribe that uses a groove of a forward mesa composed of crystal planes that are inclined at a certain angle, the contact surface of the diamond needle is stable because the surface that the dicing jig such as the diamond needle contacts is inclined. This is because it does not.

That is, the groove (601) of the forward mesa is shown in FIG. 6 (a).
Is schematically shown. In this case, a slight movement of the dicing jig (604) (the moving direction is indicated by an arrow in FIG. 6) is different in that the jig (604) contacts, and in some cases, the crystal plane The bottom (6) of the groove where (602) intersect
03) is brought into contact with the diamond needle (604), and in some cases also comes into contact with the inclined surface of the crystal plane (602),
The dicing point is not stable, and as a result, it becomes worse than the PV value due to the dicing of the inverted mesa line. On the other hand, in the case of the reverse mesa dicing groove, as shown schematically in FIG. 6B, although there is an inclined crystal plane (602), it has a divergent shape and a lower surface of the mesa (605). ) Is not inclined and is almost horizontal. Therefore, even if the dicing jig (604) moves to some extent, the contact between the jig (604) and the mesa bottom surface (605) is stable, and a PV value with little fluctuation can be obtained. Therefore, in obtaining the PV value according to the present invention, the PV value is 10 μm in the scribe of the line exhibiting the forward mesa.
When it is less than the above, the PV value naturally caused by the scribe of the reverse mesa line satisfies the requirement of the present invention. By controlling the surface roughness of the semiconductor that constitutes the element as described above, the amount of strain in the crystal is reduced, and thus the reduction of the unbalance ratio and the high mobility characteristics originally possessed by the heterojunction are reduced. Has a function that can be retained.

[0025]

EXAMPLES GaIn as an example of a heterojunction Hall element
The present invention will be described in detail with reference to examples with reference to a heterojunction Hall element including an As / InP heterojunction. (Example 1) FIG. 1 shows GaInAs / In according to the present invention.
It is a schematic plan view of a Hall element including a P heterojunction. 2 is a broken line A- of the schematic plan view shown in FIG.
FIG. 6 is a schematic view of a vertical cross section along the direction of A ′, and also after being separated into individual elements by scribe. In forming an epitaxial wafer, first, a semi-insulating high resistance InP single crystal substrate (101) having a specific resistance of about 10 ⁶ Ω · cm and a plane orientation of (100), which is obtained by adding iron (Fe), is used. Undoped InP as first layer
Layer (102) was epitaxially grown to a thickness of about 100 nm. As a result of measuring the carrier concentration of the InP layer (102) by the Hall effect method, it was about 2 × 10 ¹⁵ cm ⁻³ .

After that, on the above InP crystal layer (102), the carrier concentration was 2 × 10 ¹⁶ cm ^-3 and the Ga mixed crystal ratio was 0.1.
Undoped n-type Ga _0.47 In _0.53 As (10
3) was deposited to a thickness of 250 nm. In this example, Ga _0.47 In _0.53 As (103) and InP crystal layer (10
Both of 2), atmospheric pressure MOV using cyclopentadienyl indium (C ₅ H ₅ In) having a monovalent valence as an In source.
It was grown by the PE method. The surface roughness of the n-type Ga _0.47 In _0.53 As epitaxial growth layer (103) was 0.50 μm in PV value.

Next, a Ga _0.47 In _0.53 As layer (103)
Was covered with a normal organic photoresist material, and then the well-known photolithography technology and etching technology were used to process the regions where the input / output electrodes were to be formed and the regions (104) to be the magnetic sensitive parts into mesa shapes. . In this example, an inorganic acid was used for the mesa etching process. Then Ga
_The entire surface of the _0.47 In _0.53 As layer (103) was coated again with the organic resist material.

Next, only the resist material existing in the regions where the pair of input electrodes (105) and output electrodes (106) are to be formed is removed by using a known photolithography technique, and Ga _0.47 In _0.53 As is removed. The surface of layer (103) was exposed. Then, a gold (Au) .Ge alloy containing germanium (Ge) by about 13% by weight was vacuum-deposited.
Then, the wafer was dipped in an organic solvent mixed solution to remove the resist material, and at the same time, the Au / Ge alloy film, which is unnecessary for manufacturing the element deposited on the resist material by vapor deposition, was removed by the lift-off method. Next, in order to obtain an ohmic electrode, the wafer on which the alloy film to be the electrode is adhered is heated to a temperature of 420.
It was heat-treated at ℃ for several minutes. Furthermore, input / output electrodes (10
5 and 106) and electrically connected to the pad electrode (10
7) was provided on each electrode. The pad electrode (107) is an InP single crystal substrate (10 exposed by mesa etching).
It was placed on the surface layer of 1). This is Ga when alloying
_This is to prevent the strain from being directly introduced into the heterojunction of the _0.47 In _0.53 As layer (103) and the InP layer (102). Further, a region other than the input / output electrode portions on the surface of the heterojunction material that has undergone the above steps was covered with a silicon dioxide film (108) by a plasma CVD method. The thickness of the oxide film deposited was about 400 nm.

Further, the dicing lines (109) for covering the entire surface of the device with a general photoresist material again and separating the Hall devices formed on the entire surface of the wafer into individual Hall device chips are orthogonal to each other. <0 bar 11
> And <0 bar 1 bar 1> were patterned to be formed parallel to the crystal axis direction. After that, the dicing line (1
09), the oxide film (108) immediately below the line, the Ga _0.47 In _0.53 As layer (10)
3) and the InP buffer layer (102) were sequentially removed by etching. Further, the etching was advanced to remove the constituent materials up to the surface layer portion of the InP single crystal substrate (101) to form a dicing line (109). After that, a GaInAs Hall element formed on one main surface of the base material was separated into individual elements by using a scribing device. At the time of this separation, a diamond needle having a polyhedral diamond grain at its tip was used. The contact angle θ of the diamond needle with the dicing line (109) was set to an angle of 80 degrees with respect to the horizontal direction. The needle pressure was set to 11 g / cm ² . The side surface (1) that constitutes the GaInAs Hall element obtained under this separation condition
The flatness of 10) is 2 μm at minimum and 9.8 μm at maximum when expressed by PV value, and the total number of elements subjected to inspection is 10 μm.
It had a value of less than m.

The electrical characteristics of the thus obtained Hall element, particularly room temperature electron mobility, are shown in FIG. 3 in comparison with those of the conventional Hall element. What is a conventional Hall element? GaInAs
The surface flatness of the magnetic sensing part layer is 0.8 to 1.5 μm in PV value.
The roughness of the side surface of the element means a Hall element having a PV value of 25 μm. As shown in FIG. 3, in the Hall element of the present invention, no deterioration in electron mobility of the base material was observed before and after device formation. On the other hand, in the conventional Hall element, the average room temperature electron mobility before the separation processing was 10,000 cm ² / V · S, but after the separation processing, it was 8,000 cm ² / V · S.
And a decrease of about 20%. Furthermore, according to the result of the environmental reliability test by implementing the thermal cycle from low temperature to high temperature,
In the GaInAs Hall element having flatness according to the present invention, 93% of the Hall elements tested did not show any change in characteristics. On the other hand, in contrast to this, in the conventional Hall element, in the environmental test, the characteristics deteriorate and the pass rate is delayed to about 78%, and the present invention is also a conventional example from the viewpoint of reliability. It was clearly shown that they were superior in comparison.

(Embodiment 2) Here, Ga is composed of a heterojunction system containing GaInAs that does not lattice match with InP.
The InAs / InP lattice mismatched heterojunction Hall element will be specifically described based on Examples. GaInAs / I
The plane of the nP lattice mismatch heterostructure Hall element is the same as that in FIG. A schematic view of the cross section is shown in FIG. In the figure (701)
Is a semi-insulating InP single crystal having a plane orientation of (100) added with iron (Fe) used for forming the heterojunction. The substrate crystal had a thickness of about 350 μm. In this embodiment, the specific resistance is about 10 ⁷ Ω.
A cm crystal was used. In the figure, (702) is a crystal substrate (7
01) is an InP epitaxial crystal layer grown under the same conditions as in Example 1.

Next, on the InP layer (702), an n-type Ga _0.47 In _0.53 As epitaxial layer (7 having a mixed crystal ratio of 0.47 and a film thickness of about 10 nm, which lattice-matches with InP, is formed.
03) was provided by the atmospheric pressure MOCVD growth method described above. The carrier concentration of this layer (703) is 2. according to the Hall effect method.
It was 0 × 10 ¹⁶ cm ⁻³ . Furthermore, Ga _0.47 In _0.53 A
On the s epitaxial layer (703), a Ga _0.48 In _0.52 As lattice mismatch layer (704) having a mixed crystal ratio of 0.48 was grown to a film thickness of 400 nm. The carrier concentration of the Ga _0.48 In _0.52 As lattice mismatch layer (704) is the same as that of Ga _0.47 In described above.
1.9 × 10 ¹⁶ cm, which is almost the same as the _0.53 As layer (703)
^-3 . PV value of the same layer at this point is 0.074 μm
Met. The unbalance rate in this state was about ± 5%. Then, this wafer was heat-treated in the same thin film growth apparatus at a temperature of 700 ° C. for 25 minutes in an atmosphere containing As. As a result, the PV value of the surface of the layer (704) was improved to about 0.036 μm. After that, Ga _0.48
The above Ga _0.47 In _{0.53 is formed} on the In _0.52 As layer (704).
Ga having a carrier concentration similar to that of the As layer (703)
_{A 0.47} In _0.53 As layer (705) was grown. The film thickness of the same layer was 380 nm. The surface of the same layer (705), that is,
The PV value of the outermost surface of the laminated structure was 0.040 μm.

Using the wafer having such a structure, a Hall element was processed in the same procedure as in Example 1. Further, dicing was performed along the dicing line (708) under the conditions described in Example 1, and the PV value of the side surface was 2 to 9.5 μ.
m individual chips. Chip size is very general 3
The size was 50 μm × 350 μm. The Hall element produced as described above was subjected to electrical characteristic evaluation. Table 1 shows the evaluated items and characteristic values in comparison with the case of the present invention and the conventional example. The conventional example is the above-mentioned Ga _0.47 In
_{Although the} Ga _0.48 In _0.52 As lattice mismatch layer is inserted in the _0.53 As layer, the PV value of the outermost GaInAs layer is 0.5.
8 μm heterojunction Hall element. As shown in Table 1, a significant difference was found in the unbalance ratio between the Hall element according to the present invention and the conventional Hall element, indicating the superiority of the present invention.

[0034]

[Table 1]

[0035]

By defining the flatness of the surface of the epitaxial growth layer and the side surface of the substrate immediately after dicing, a stable supply of the Hall element with high sensitivity and low unbalance rate can be obtained. In the embodiments of the present invention, the description has been given by taking the heterojunction Hall element made of GaInAs and InP as an example.
The present invention is not limited to this Hall element, and other Hall elements having a heterojunction, for example, GaInAs / AlGaA.
heterojunction Hall element having s or GaInAs / GaAs heterojunction, or GaAs / GaInAs / A
It can also be applied to a heterojunction Hall element composed of a double heterojunction composed of 1GaAs.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a Hall element according to the present invention.

FIG. 2 is a cross-sectional view of the Hall element shown in FIG. 1 taken along the broken line AA ′.

FIG. 3 is a diagram showing changes in electron mobility before and after separation into individual devices.

FIG. 4 is a diagram for schematically explaining the concept of PV value.

FIG. 5 is a diagram showing a relationship between a PV value on the side surface of the device and electron mobility.

FIG. 6 is a schematic view of a cross section of a dicing line.
(A) shows the case of forward mesa, (b) shows the case of reverse mesa.

FIG. 7 is a schematic view of a cross section of the Hall element shown in Example 2.

FIG. 8: GaIn before (a) and after (b) heat treatment
It is a figure which shows the surface roughness of an As epitaxial growth layer.

FIG. 9 is a diagram showing the relationship between the roughness of the outermost surface of GaInAs and the absolute value of the imbalance ratio.

[Explanation of symbols]

(101) InP single crystal substrate (102) InP crystal layer (103) Ga _0.47 In _0.53 As crystal layer (104) Mesa region (105) Input electrode (106) Output electrode (107) Pad electrode (108) Oxide film (109) ) Dicing line (110) Side surface of the Hall element (601) Scribe groove (602) Slanted crystal plane (603) forming a normal mesa shape Bottom of groove corresponding to intersection of slanted crystal plane (604) Dicing jig (605) Flat bottom surface of groove having a reverse mesa shape (701) InP semi-insulating single crystal substrate (702) InP crystal layer (703) Ga _0.47 In _0.53 As layer (704) Ga _0.48 In _0.54 As layer (705) Ga _0.47 In _0.53 As layer (706) Ohmic input / output electrode (707) SiO ₂ insulating film (708) Dicing line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-198877 (JP, A) JP-A-57-128087 (JP, A) JP-A-57-128086 (JP, A) JP-A-56- 167378 (JP, A) JP 57-188890 (JP, A) JP 58-106883 (JP, A) JP 57-197884 (JP, A) JP 6-350158 (JP, A) JP-A-6-349887 (JP, A) JP-A-2-97075 (JP, A) JP-A-52-87993 (JP, A) Electrotechnical Laboratory News, No. 511, pp. 6-10 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 43/06 JISST file (JOIS)

Claims (6)

(57) [Claims] 1. A Hall element comprising a heterojunction containing GaInAs, wherein the surface roughness of an epitaxially grown layer serving as a magnetic sensing layer is less than 0.07 μm in PV value. . 2. The roughness of the side surface of the device immediately after dicing is PV.
The Hall element according to claim 1, wherein the value is less than 10 μm. 3. The heterojunction comprises gallium indium arsenide and indium phosphide.
Alternatively, the hall element according to item 2. 4. The Hall element according to claim 1, wherein the heterojunction is made of gallium arsenide / aluminum and gallium arsenide / indium arsenide. 5. The Hall element according to claim 1, wherein the heterojunction is composed of gallium arsenide and gallium indium arsenide. 6. The Hall element according to claim 1, wherein the heterojunction has a double heterostructure composed of gallium arsenide and gallium arsenide / aluminum and gallium arsenide / indium arsenide.